From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Chen-Yu Tsai <wens@csie.org>
Cc: "Boris BREZILLON" <boris.brezillon@free-electrons.com>,
"Randy Dunlap" <rdunlap@infradead.org>,
"Emilio López" <emilio@elopez.com.ar>,
"Mike Turquette" <mturquette@linaro.org>,
"Linus Walleij" <linus.walleij@linaro.org>,
devicetree <devicetree@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-doc@vger.kernel.org
Subject: Re: [PATCH 00/15] ARM: sunxi: add A31 PL pins support
Date: Thu, 10 Apr 2014 10:10:31 +0200 [thread overview]
Message-ID: <20140410081031.GM28585@lukather> (raw)
In-Reply-To: <CAGb2v67+YNhw2MXSu9DTKSUfXH=v+uD7KEaxyiPezyf9CYtmPw@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 991 bytes --]
On Thu, Apr 10, 2014 at 12:27:32AM +0800, Chen-Yu Tsai wrote:
> >> > Let me know if these changes are too intrusive.
> >>
> >> I wonder if we should do a separate driver for the new PIO controller.
> >> Clearly it's a separate IP block, with it's own clock and reset controls.
> >
> > It's been merged together in the A23, hence why we did it like that.
>
> I'm not sure I understand. The clock gate and reset control are still separate,
> are they not?
On the A31 the "regular" port controler handles PA to PH banks, while
the R_PIO handles the PL and PM banks.
On the A23, the regular port controler handles PA to PL banks, and the
R_PIO and PM bank doesn't exist.
So we're not quite in the same situation. The A31 is troublesome,
while the A23 (except for the external interrupts), is pretty much
what we've seen so far with the A10/A20/...
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
next prev parent reply other threads:[~2014-04-10 8:10 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-09 13:51 [PATCH 00/15] ARM: sunxi: add A31 PL pins support Boris BREZILLON
2014-04-09 13:51 ` [PATCH 01/15] ARM: sunxi: dt: list all pinctrl compatible strings Boris BREZILLON
[not found] ` <1397051478-4113-2-git-send-email-boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-04-09 14:43 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 02/15] ARM: sunxi: dt: document pinctrl clock related properties Boris BREZILLON
2014-04-09 14:45 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 03/15] ARM: sunxi: dt: add pinctrl clock-names properties Boris BREZILLON
2014-04-09 13:51 ` [PATCH 04/15] pinctrl: sunxi: specify clk name when retrieving pinctrl pio clk Boris BREZILLON
[not found] ` <1397051478-4113-5-git-send-email-boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-04-10 18:14 ` Linus Walleij
2014-04-10 18:16 ` Linus Walleij
2014-04-10 21:17 ` Boris BREZILLON
2014-04-09 13:51 ` [PATCH 05/15] clk: sunxi: add A31 APB0 clk gate defintions Boris BREZILLON
2014-04-09 14:49 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 06/15] clk: sunxi: add A31 APB0 gates compatible string to the documentation Boris BREZILLON
2014-04-09 13:59 ` Chen-Yu Tsai
2014-04-09 14:45 ` Boris BREZILLON
2014-04-09 14:51 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 07/15] ARM: sunxi: dt: define A31's APB0 clk gates node Boris BREZILLON
2014-04-09 14:06 ` Emilio López
2014-04-09 14:43 ` Boris BREZILLON
2014-04-09 15:08 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 08/15] reset: sunxi: document sunxi's reset controllers bindings Boris BREZILLON
2014-04-09 13:51 ` [PATCH 09/15] clk: sunxi: add A31 APB0 reset line defintions Boris BREZILLON
2014-04-09 13:51 ` [PATCH 10/15] pinctrl: sunxi: add PL pin definitions Boris BREZILLON
2014-04-09 13:51 ` [PATCH 11/15] pinctrl: sunxi: add support for A31 PL pins Boris BREZILLON
2014-04-09 13:51 ` [PATCH 12/15] pinctrl: sunxi: retrieve and enable PL clk gate for A31 SoC Boris BREZILLON
2014-04-09 15:33 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 13/15] pinctrl: sunxi: retrieve and enable PL reset line " Boris BREZILLON
2014-04-09 15:34 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 14/15] pinctrl: sunxi: define A31 PL0/PL1 pins Boris BREZILLON
2014-04-09 15:38 ` Maxime Ripard
2014-04-09 13:51 ` [PATCH 15/15] ARM: sunxi: dt: add support for A31's PL pins Boris BREZILLON
2014-04-09 14:53 ` [PATCH 00/15] ARM: sunxi: add A31 PL pins support Chen-Yu Tsai
2014-04-09 15:17 ` Maxime Ripard
2014-04-09 15:45 ` Maxime Ripard
2014-04-09 16:27 ` Chen-Yu Tsai
2014-04-10 8:10 ` Maxime Ripard [this message]
2014-04-10 9:56 ` Chen-Yu Tsai
2014-04-09 16:14 ` Boris BREZILLON
2014-04-09 17:14 ` Chen-Yu Tsai
2014-04-09 18:04 ` Boris BREZILLON
2014-04-10 8:16 ` Maxime Ripard
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20140410081031.GM28585@lukather \
--to=maxime.ripard@free-electrons.com \
--cc=boris.brezillon@free-electrons.com \
--cc=devicetree@vger.kernel.org \
--cc=emilio@elopez.com.ar \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@linaro.org \
--cc=rdunlap@infradead.org \
--cc=wens@csie.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).