From: "Antoine Ténart" <antoine.tenart@free-electrons.com>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: "Antoine Ténart" <antoine.tenart@free-electrons.com>,
sebastian.hesselbarth@gmail.com, tj@kernel.org,
alexandre.belloni@free-electrons.com,
thomas.petazzoni@free-electrons.com, zmxu@marvell.com,
jszhang@marvell.com, linux-arm-kernel@lists.infradead.org,
linux-ide@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 1/6] phy: add a driver for the Berlin SATA PHY
Date: Wed, 14 May 2014 12:21:22 +0200 [thread overview]
Message-ID: <20140514102122.GA11140@kwain> (raw)
In-Reply-To: <537341AF.5030105@ti.com>
Hi,
On Wed, May 14, 2014 at 03:43:03PM +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Wednesday 14 May 2014 03:18 PM, Antoine Ténart wrote:
[…]
> > +#define to_berlin_sata_phy_priv(desc) \
> > + container_of((desc), struct phy_berlin_priv, phys[(desc)->index])
> > +
> > +struct phy_berlin_desc {
> > + struct phy *phy;
> > + u32 val;
> > + unsigned index;
> > +};
> > +
> > +struct phy_berlin_priv {
> > + void __iomem *base;
> > + spinlock_t lock;
> > + struct phy_berlin_desc phys[BERLIN_SATA_PHY_NB];
>
> Can't we do away with hardcoding BERLIN_SATA_PHY_NB?
We can't if we want to be able to use the container_of macro in
to_berlin_sata_phy_priv(). And we want a common structure to store the
common spinlock and base address.
[…]
> > + /*
> > + * By default the PHY node is used to request and match a PHY.
> > + * We describe one PHY per sub-node here. Use the right node.
> > + */
> > + phy->dev.of_node = child;
> > +
> > + priv->phys[phy_id].phy = phy;
> > + priv->phys[phy_id].val = desc[phy_id].val;
> > + priv->phys[phy_id].index = phy_id;
> > + phy_set_drvdata(phy, &priv->phys[phy_id]);
> > +
> > + /* Make sure the PHY is off */
> > + phy_berlin_sata_power_off(phy);
> > +
> > + phy_provider = devm_of_phy_provider_register(&phy->dev,
> > + of_phy_simple_xlate);
> > + if (IS_ERR(phy_provider))
> > + return PTR_ERR(phy_provider);
>
> was this intentional? registering multiple PHY providers?
Yes. Each sub-node describe a PHY and register as a PHY provider. This
allow to reference the PHY as <&sata_phy0> and not <&sata_phy 0>. It
would be confusing to have a sub-node sata_phy0 and to use its parent
to access it.
Antoine
--
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
next prev parent reply other threads:[~2014-05-14 10:21 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-14 9:48 [PATCH v3 0/6] ARM: berlin: add AHCI support Antoine Ténart
2014-05-14 9:48 ` [PATCH v3 1/6] phy: add a driver for the Berlin SATA PHY Antoine Ténart
2014-05-14 10:13 ` Kishon Vijay Abraham I
2014-05-14 10:21 ` Antoine Ténart [this message]
2014-05-15 6:15 ` Kishon Vijay Abraham I
2014-05-14 13:02 ` Arnd Bergmann
2014-05-14 14:50 ` Antoine Ténart
2014-05-14 15:31 ` Arnd Bergmann
2014-05-14 15:49 ` Antoine Ténart
2014-05-14 16:11 ` Arnd Bergmann
2014-05-14 16:57 ` Antoine Ténart
2014-05-14 17:57 ` Sebastian Hesselbarth
2014-05-14 18:12 ` Arnd Bergmann
2014-05-14 18:42 ` Sebastian Hesselbarth
2014-05-14 18:51 ` Arnd Bergmann
2014-05-14 18:56 ` Sebastian Hesselbarth
2014-05-14 19:10 ` Arnd Bergmann
2014-05-15 6:45 ` Kishon Vijay Abraham I
2014-05-15 7:02 ` Sebastian Hesselbarth
2014-05-15 8:46 ` Kishon Vijay Abraham I
[not found] ` <53747F03.5030206-l0cyMroinI0@public.gmane.org>
2014-05-15 9:17 ` Sebastian Hesselbarth
2014-05-15 9:25 ` Kishon Vijay Abraham I
2014-05-14 9:48 ` [PATCH v3 2/6] Documentation: bindings: add " Antoine Ténart
[not found] ` <1400060942-10588-1-git-send-email-antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-05-14 9:48 ` [PATCH v3 3/6] ata: ahci: add AHCI support for the Berlin BG2Q Antoine Ténart
2014-05-14 9:49 ` [PATCH v3 4/6] Documentation: bindings: add the berlin-ahci compatible to the ahci platform Antoine Ténart
2014-05-14 9:49 ` [PATCH v3 5/6] ARM: berlin: add the AHCI node for the BG2Q Antoine Ténart
2014-05-14 9:49 ` [PATCH v3 6/6] ARM: berlin: enable the eSATA interface on the BG2Q DMP Antoine Ténart
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