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From: "Antoine Ténart" <antoine.tenart@free-electrons.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: linux-arm-kernel@lists.infradead.org,
	"Antoine Ténart" <antoine.tenart@free-electrons.com>,
	thomas.petazzoni@free-electrons.com, zmxu@marvell.com,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	kishon@ti.com, linux-ide@vger.kernel.org,
	alexandre.belloni@free-electrons.com, jszhang@marvell.com,
	tj@kernel.org, sebastian.hesselbarth@gmail.com
Subject: Re: [PATCH v3 1/6] phy: add a driver for the Berlin SATA PHY
Date: Wed, 14 May 2014 17:49:29 +0200	[thread overview]
Message-ID: <20140514154929.GA8016@kwain> (raw)
In-Reply-To: <31922167.uMVzxsQNIT@wuerfel>

On Wed, May 14, 2014 at 05:31:24PM +0200, Arnd Bergmann wrote:
> On Wednesday 14 May 2014 16:50:02 Antoine Ténart wrote:
> > On Wed, May 14, 2014 at 03:02:34PM +0200, Arnd Bergmann wrote:
> > > On Wednesday 14 May 2014 11:48:57 Antoine Ténart wrote:
> > > > +static int phy_berlin_sata_power_on(struct phy *phy)
> > > > +{
> > > > +       struct phy_berlin_desc *desc = phy_get_drvdata(phy);
> > > > +       struct phy_berlin_priv *priv = to_berlin_sata_phy_priv(desc);
> > > > +       u32 regval;
> > > > +
> > > > +       spin_lock(&priv->lock);
> > > > +
> > > > +       /* Power up PHY */
> > > > +       writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
> > > > +       regval = readl(priv->base + HOST_VSA_DATA);
> > > > +       regval &= ~(desc->val);
> > > > +       writel(regval, priv->base + HOST_VSA_DATA);
> > > > +
> > > > +       /* Configure MBus */
> > > > +       writel(MBUS_SIZE_CONTROL, priv->base + HOST_VSA_ADDR);
> > > > +       regval = readl(priv->base + HOST_VSA_DATA);
> > > > +       regval |= MBUS_WRITE_REQUEST_SIZE_128 | MBUS_READ_REQUEST_SIZE_128;
> > > > +       writel(regval, priv->base + HOST_VSA_DATA);
> > > > +
> > > > +       spin_unlock(&priv->lock);
> > > > +
> > > > +       return 0;
> > > > +}
> > > > +
> > > > +static int phy_berlin_sata_power_off(struct phy *phy)
> > > > +{
> > > > +       struct phy_berlin_desc *desc = phy_get_drvdata(phy);
> > > > +       struct phy_berlin_priv *priv = to_berlin_sata_phy_priv(desc);
> > > > +       u32 regval;
> > > > +
> > > > +       spin_lock(&priv->lock);
> > > > +
> > > > +       /* Power down PHY */
> > > > +       writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
> > > > +       regval = readl(priv->base + HOST_VSA_DATA);
> > > > +       regval |= desc->val;
> > > > +       writel(regval, priv->base + HOST_VSA_DATA);
> > > > +
> > > > +       spin_unlock(&priv->lock);
> > > > +
> > > > +       return 0;
> > > 
> > > I don't get this part: you have a reference to the phy here,
> > > but then you go poking the phy registers from the SATA driver
> > > rather than calling a PHY API function.
> > 
> > The v1 only introduced an AHCI driver. I somewhat agree the PHY
> > operations done in the AHCI driver could be in there.
> > 
> > I can move the initialization done in the AHCI driver here, but I'll
> > still need the driver: the Berlin AHCI needs to call the framework
> > generic functions with a custom mask and has custom pm_ops. So I'll
> > end up with a nearly empty AHCI driver, not able to control the port
> > parameters.
> > 
> > Or I can put all this in the AHCI driver, but then we'll need to
> > describe the PHYs there (to be able to enable each PHY independently)
> > and add bindings to the SATA ones.
> > 
> > What do you think? I prefer the first solution, but we'll have SATA
> > port related configuration in the PHY and a very tiny AHCI driver
> > because I can't really use the default behaviour of the ahci_platform.
> 
> I just noticed I quoted the wrong driver with my comment, but I think
> you got what I meant.
> 
> Why do you need a custom mask? Is that something you could pass
> as the argument in the phy descriptor using #phy-cells=<1>?

I meant a custom mask in the AHCI driver, when calling the
ahci_platform_init_host() function. Otherwise we'll have problems on the
BG2Q DMP (it only has one PHY available, and not initializing it is not
enough).

> 
> > > > +                * By default the PHY node is used to request and match a PHY.
> > > > +                * We describe one PHY per sub-node here. Use the right node.
> > > > +                */
> > > > +               phy->dev.of_node = child;
> > > > +
> > > > +               priv->phys[phy_id].phy = phy;
> > > > +               priv->phys[phy_id].val = desc[phy_id].val;
> > > > +               priv->phys[phy_id].index = phy_id;
> > > > +               phy_set_drvdata(phy, &priv->phys[phy_id]);
> > > 
> > > And here, you set a driver specific value into a structure used by the
> > > PHY.
> > 
> > Values in priv->phys[] are related to the PHYs. phy_set_drvdata() allows
> > to store PHY related data, which is what I'm doing there. Nearly all PHY
> > drivers are doing this.
> > 
> > Or am I missing something?
> 
> This part is really ok, I got confused when I replied to the wrong email.
> Sorry about this.
> 
> > > Both of these are layering violations. You should either use the PHY
> > > interfaces correctly so the SATA driver doesn't have to know about the
> > > specific, or not use a PHY device node at all and do everything in
> > > the SATA front-end.
> > 
> > To be sure: you mean using the PHY init() interface in the AHCI driver?
> 
> If this PHY is specific to the ahci-berlin hardware and not shared with
> anything else, you don't really need to split out a phy driver. That
> would somewhat simplify what you ahve here.

I don't have lots of info about that, but we set the PHY to
PHY_MODE_SATA in the AHCI driver. So I guess there are other modes.

Maybe Jisheng can help us with this?

> 
> The alternative is to make it as generic as you can. If you can manage
> to move all the phy code into phy-berlin-sata driver, it should be
> possible to just extend the ahci-platform driver resume function to
> reinitialize the phy if there is one.

It is possible to move all the PHY code the phy-berlin-sata. Then I'll
need to hack a bit the AHCI framework so it can handle more than one
PHY. But as I said, I'll still need to set a custom mask, and adding a
quirk to the AHCI platform or framework does not seem to be a very good
idea, imho.

Or I can add a computed mask to the ahci-platform driver, like I did in
the Berlin one, but I don't know what would be the consequences. For
each PHY I have:

+	mask |= 1 << i;


Antoine

-- 
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

  reply	other threads:[~2014-05-14 15:49 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-14  9:48 [PATCH v3 0/6] ARM: berlin: add AHCI support Antoine Ténart
2014-05-14  9:48 ` [PATCH v3 1/6] phy: add a driver for the Berlin SATA PHY Antoine Ténart
2014-05-14 10:13   ` Kishon Vijay Abraham I
2014-05-14 10:21     ` Antoine Ténart
2014-05-15  6:15       ` Kishon Vijay Abraham I
2014-05-14 13:02   ` Arnd Bergmann
2014-05-14 14:50     ` Antoine Ténart
2014-05-14 15:31       ` Arnd Bergmann
2014-05-14 15:49         ` Antoine Ténart [this message]
2014-05-14 16:11           ` Arnd Bergmann
2014-05-14 16:57             ` Antoine Ténart
2014-05-14 17:57               ` Sebastian Hesselbarth
2014-05-14 18:12                 ` Arnd Bergmann
2014-05-14 18:42                   ` Sebastian Hesselbarth
2014-05-14 18:51                     ` Arnd Bergmann
2014-05-14 18:56                       ` Sebastian Hesselbarth
2014-05-14 19:10                         ` Arnd Bergmann
2014-05-15  6:45                     ` Kishon Vijay Abraham I
2014-05-15  7:02                       ` Sebastian Hesselbarth
2014-05-15  8:46                         ` Kishon Vijay Abraham I
     [not found]                           ` <53747F03.5030206-l0cyMroinI0@public.gmane.org>
2014-05-15  9:17                             ` Sebastian Hesselbarth
2014-05-15  9:25                               ` Kishon Vijay Abraham I
2014-05-14  9:48 ` [PATCH v3 2/6] Documentation: bindings: add " Antoine Ténart
     [not found] ` <1400060942-10588-1-git-send-email-antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-05-14  9:48   ` [PATCH v3 3/6] ata: ahci: add AHCI support for the Berlin BG2Q Antoine Ténart
2014-05-14  9:49   ` [PATCH v3 4/6] Documentation: bindings: add the berlin-ahci compatible to the ahci platform Antoine Ténart
2014-05-14  9:49 ` [PATCH v3 5/6] ARM: berlin: add the AHCI node for the BG2Q Antoine Ténart
2014-05-14  9:49 ` [PATCH v3 6/6] ARM: berlin: enable the eSATA interface on the BG2Q DMP Antoine Ténart

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