* [PATCH v3 1/6] ARM: Add platform support for LSI AXM55xx SoC
2014-05-14 18:37 [PATCH v3 0/6] Add platform support for LSI AXM55xx Anders Berg
@ 2014-05-14 18:37 ` Anders Berg
2014-05-14 18:37 ` [PATCH v3 2/6] clk: Add clock driver for " Anders Berg
` (5 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Anders Berg @ 2014-05-14 18:37 UTC (permalink / raw)
To: Arnd Bergmann, Olof Johansson
Cc: Linus Walleij, Russell King, devicetree, linux-arm-kernel,
linux-kernel, Anders Berg
From: Anders Berg <anders.berg@lsi.com>
The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15
cores (in a 4x4 cluster configuration). The cores within each cluster share an
L2 cache, and the clusters are connected to each other via a CCN-504 cache
coherent interconnect.
This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located
above 4GB in the memory map.
Signed-off-by: Anders Berg <anders.berg@lsi.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
Documentation/devicetree/bindings/arm/axxia.txt | 12 ++++
arch/arm/Kconfig | 2 +
arch/arm/Makefile | 2 +
arch/arm/mach-axxia/Kconfig | 16 +++++
arch/arm/mach-axxia/Makefile | 2 +
arch/arm/mach-axxia/axxia.c | 28 ++++++++
arch/arm/mach-axxia/platsmp.c | 89 +++++++++++++++++++++++++
7 files changed, 151 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/axxia.txt
create mode 100644 arch/arm/mach-axxia/Kconfig
create mode 100644 arch/arm/mach-axxia/Makefile
create mode 100644 arch/arm/mach-axxia/axxia.c
create mode 100644 arch/arm/mach-axxia/platsmp.c
diff --git a/Documentation/devicetree/bindings/arm/axxia.txt b/Documentation/devicetree/bindings/arm/axxia.txt
new file mode 100644
index 0000000..7b4ef9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/axxia.txt
@@ -0,0 +1,12 @@
+Axxia AXM55xx device tree bindings
+
+Boards using the AXM55xx SoC need to have the following properties:
+
+Required root node property:
+
+ - compatible = "lsi,axm5516"
+
+Boards:
+
+ LSI AXM5516 Validation board (Amarillo)
+ compatible = "lsi,axm5516-amarillo", "lsi,axm5516"
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index db3c541..5dba814 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -951,6 +951,8 @@ source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-at91/Kconfig"
+source "arch/arm/mach-axxia/Kconfig"
+
source "arch/arm/mach-bcm/Kconfig"
source "arch/arm/mach-berlin/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 41c1931..6721fab 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -138,10 +138,12 @@ endif
textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000
textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
+textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_AT91) += at91
+machine-$(CONFIG_ARCH_AXXIA) += axxia
machine-$(CONFIG_ARCH_BCM) += bcm
machine-$(CONFIG_ARCH_BERLIN) += berlin
machine-$(CONFIG_ARCH_CLPS711X) += clps711x
diff --git a/arch/arm/mach-axxia/Kconfig b/arch/arm/mach-axxia/Kconfig
new file mode 100644
index 0000000..8be7e0a
--- /dev/null
+++ b/arch/arm/mach-axxia/Kconfig
@@ -0,0 +1,16 @@
+config ARCH_AXXIA
+ bool "LSI Axxia platforms" if (ARCH_MULTI_V7 && ARM_LPAE)
+ select ARCH_DMA_ADDR_T_64BIT
+ select ARM_AMBA
+ select ARM_GIC
+ select ARM_TIMER_SP804
+ select HAVE_ARM_ARCH_TIMER
+ select MFD_SYSCON
+ select MIGHT_HAVE_PCI
+ select PCI_DOMAINS if PCI
+ select ZONE_DMA
+ help
+ This enables support for the LSI Axxia devices.
+
+ The LSI Axxia platforms require a Flattened Device Tree to be passed
+ to the kernel.
diff --git a/arch/arm/mach-axxia/Makefile b/arch/arm/mach-axxia/Makefile
new file mode 100644
index 0000000..ec4f68b
--- /dev/null
+++ b/arch/arm/mach-axxia/Makefile
@@ -0,0 +1,2 @@
+obj-y += axxia.o
+obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-axxia/axxia.c b/arch/arm/mach-axxia/axxia.c
new file mode 100644
index 0000000..19e5a1d
--- /dev/null
+++ b/arch/arm/mach-axxia/axxia.c
@@ -0,0 +1,28 @@
+/*
+ * Support for the LSI Axxia SoC devices based on ARM cores.
+ *
+ * Copyright (C) 2012 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <asm/mach/arch.h>
+
+static const char *axxia_dt_match[] __initconst = {
+ "lsi,axm5516",
+ "lsi,axm5516-sim",
+ "lsi,axm5516-emu",
+ NULL
+};
+
+DT_MACHINE_START(AXXIA_DT, "LSI Axxia AXM55XX")
+ .dt_compat = axxia_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-axxia/platsmp.c b/arch/arm/mach-axxia/platsmp.c
new file mode 100644
index 0000000..959d4df
--- /dev/null
+++ b/arch/arm/mach-axxia/platsmp.c
@@ -0,0 +1,89 @@
+/*
+ * linux/arch/arm/mach-axxia/platsmp.c
+ *
+ * Copyright (C) 2012 LSI Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+
+/* Syscon register offsets for releasing cores from reset */
+#define SC_CRIT_WRITE_KEY 0x1000
+#define SC_RST_CPU_HOLD 0x1010
+
+/*
+ * Write the kernel entry point for secondary CPUs to the specified address
+ */
+static void write_release_addr(u32 release_phys)
+{
+ u32 *virt = (u32 *) phys_to_virt(release_phys);
+ writel_relaxed(virt_to_phys(secondary_startup), virt);
+ /* Make sure this store is visible to other CPUs */
+ smp_wmb();
+ __cpuc_flush_dcache_area(virt, sizeof(u32));
+}
+
+static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ struct device_node *syscon_np;
+ void __iomem *syscon;
+ u32 tmp;
+
+ syscon_np = of_find_compatible_node(NULL, NULL, "lsi,axxia-syscon");
+ if (!syscon_np)
+ return -ENOENT;
+
+ syscon = of_iomap(syscon_np, 0);
+ if (!syscon)
+ return -ENOMEM;
+
+ tmp = readl(syscon + SC_RST_CPU_HOLD);
+ writel(0xab, syscon + SC_CRIT_WRITE_KEY);
+ tmp &= ~(1 << cpu);
+ writel(tmp, syscon + SC_RST_CPU_HOLD);
+
+ return 0;
+}
+
+static void __init axxia_smp_prepare_cpus(unsigned int max_cpus)
+{
+ int cpu_count = 0;
+ int cpu;
+
+ /*
+ * Initialise the present map, which describes the set of CPUs actually
+ * populated at the present time.
+ */
+ for_each_possible_cpu(cpu) {
+ struct device_node *np;
+ u32 release_phys;
+
+ np = of_get_cpu_node(cpu, NULL);
+ if (!np)
+ continue;
+ if (of_property_read_u32(np, "cpu-release-addr", &release_phys))
+ continue;
+
+ if (cpu_count < max_cpus) {
+ set_cpu_present(cpu, true);
+ cpu_count++;
+ }
+
+ if (release_phys != 0)
+ write_release_addr(release_phys);
+ }
+}
+
+static struct smp_operations axxia_smp_ops __initdata = {
+ .smp_prepare_cpus = axxia_smp_prepare_cpus,
+ .smp_boot_secondary = axxia_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(axxia_smp, "lsi,syscon-release", &axxia_smp_ops);
--
1.8.3.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 2/6] clk: Add clock driver for AXM55xx SoC
2014-05-14 18:37 [PATCH v3 0/6] Add platform support for LSI AXM55xx Anders Berg
2014-05-14 18:37 ` [PATCH v3 1/6] ARM: Add platform support for LSI AXM55xx SoC Anders Berg
@ 2014-05-14 18:37 ` Anders Berg
2014-05-14 20:08 ` Mike Turquette
2014-05-14 18:37 ` [PATCH v3 3/6] ARM: dts: Device tree for AXM55xx Anders Berg
` (4 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Anders Berg @ 2014-05-14 18:37 UTC (permalink / raw)
To: Arnd Bergmann, Olof Johansson
Cc: Linus Walleij, Russell King, devicetree, linux-arm-kernel,
linux-kernel, Anders Berg, Mike Turquette, Mark Rutland
From: Anders Berg <anders.berg@lsi.com>
Add clk driver to support clock blocks found on the AXM55xx devices. The driver
provides clock implementations for three different types of clock devices on
the AXM55xx device: PLL clock, a clock divider and a clock mux.
Signed-off-by: Anders Berg <anders.berg@lsi.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
.../devicetree/bindings/clock/clk-axxia.txt | 88 +++++++
drivers/clk/Makefile | 1 +
drivers/clk/clk-axxia.c | 281 +++++++++++++++++++++
3 files changed, 370 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/clk-axxia.txt
create mode 100644 drivers/clk/clk-axxia.c
diff --git a/Documentation/devicetree/bindings/clock/clk-axxia.txt b/Documentation/devicetree/bindings/clock/clk-axxia.txt
new file mode 100644
index 0000000..94eb840
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-axxia.txt
@@ -0,0 +1,88 @@
+* Axxia clock driver bindings
+
+This document contains bindings for the Axxia PLL, clock divider and mux. The
+binding uses the common clock binding found in:
+
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+* Axxia PLL
+
+Required properties:
+- #clock-cells : shall be set to 0.
+- compatible : shall be "lsi,axxia-pll-clock"
+- clocks : parent clock phandle
+- reg - specifies PLL control registers
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+
+ clk_ref0: clk_ref0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clk_cpu_pll: clk_cpu_pll@2010022000 {
+ compatible = "lsi,axxia-pll-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_ref0>;
+ clock-output-names = "clk_cpu_pll";
+ reg = <0x20 0x10022000 0 0x2c>;
+ };
+
+
+* Axxia clock divider
+
+Required properties:
+- #clock-cells : shall be set to 0.
+- compatible : shall be "lsi,axxia-div-clock"
+- clocks : parent clock phandle
+- reg - clock divider control register
+- lsi,bit-shift : bit position of the divider control field.
+- lsi,bit-mask : width of the divider control field.
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+
+ clk_cpu_div: cpu {
+ compatible = "lsi,axxia-div-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_cpu_pll>;
+ clock-output-names = "clk_cpu_div";
+ reg = <0x20 0x10030008 0 0x4>;
+ lsi,bit-shift = <0>;
+ lsi,bit-width = <4>;
+ };
+
+
+* Axxia clock mux
+
+Required properties:
+- #clock-cells : shall be set to 0.
+- compatible : shall be "lsi,axxia-mux-clock"
+- clocks : phandle of parent clocks (max 4)
+- reg - clock divider control register
+- lsi,bit-shift : bit position of the divider control field.
+- lsi,bit-mask : width of the divider control field.
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+
+ clk_cpu: clk_cpu0@2010030000 {
+ compatible = "lsi,axxia-mux-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_ref0>,
+ <&clk_cpu_pll>,
+ <&clk_cpu_div>,
+ <&clk_cpu_div>;
+ clock-output-names = "clk_cpu";
+ reg = <0x20 0x10030000 0 0x4>;
+ lsi,bit-shift = <0>;
+ lsi,bit-width = <2>;
+ };
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5f8a287..ff28168 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-composite.o
# hardware specific clock types
# please keep this section sorted lexicographically by file/directory path name
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
+obj-$(CONFIG_ARCH_AXXIA) += clk-axxia.o
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
diff --git a/drivers/clk/clk-axxia.c b/drivers/clk/clk-axxia.c
new file mode 100644
index 0000000..996b8f2
--- /dev/null
+++ b/drivers/clk/clk-axxia.c
@@ -0,0 +1,281 @@
+/*
+ * arch/arm/mach-axxia/clock.c
+ *
+ * Provides clock implementations for three different types of clock devices on
+ * the Axxia device: PLL clock, a clock divider and a clock mux.
+ *
+ * Copyright (C) 2012 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk-provider.h>
+
+
+static void __iomem *
+parse_and_map_reg(struct device_node *node, u32 *shift, u32 *width)
+{
+ void __iomem *reg;
+
+ if (of_property_read_u32(node, "lsi,bit-shift", shift)) {
+ pr_err("%s: no 'lsi,bit-shift' property\n", node->name);
+ return NULL;
+ }
+
+ if (of_property_read_u32(node, "lsi,bit-width", width)) {
+ pr_err("%s: no 'lsi,bit-width' property\n", node->name);
+ return NULL;
+ }
+
+ reg = of_iomap(node, 0);
+ if (!reg)
+ pr_err("%s: failed to map register\n", node->name);
+
+ return reg;
+}
+
+/**
+ * struct axxia_pllclk - Axxia PLL generated clock.
+ * @hw: clk_hw for the PLL
+ * @regs: Pointer to control registers
+ */
+struct axxia_pllclk {
+ struct clk_hw hw;
+ void __iomem *regs;
+};
+
+#define to_axxia_pll(_hw) container_of(_hw, struct axxia_pllclk, hw)
+
+static unsigned long
+axxia_pllclk_recalc(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct axxia_pllclk *pll = to_axxia_pll(hw);
+ unsigned long rate, fbdiv, refdiv, postdiv;
+ u32 control;
+
+ control = readl(pll->regs);
+ postdiv = ((control >> 0) & 0xf) + 1;
+ fbdiv = ((control >> 4) & 0xfff) + 3;
+ refdiv = ((control >> 16) & 0x1f) + 1;
+ rate = (parent_rate / (refdiv * postdiv)) * fbdiv;
+
+ return rate;
+}
+
+static const struct clk_ops clk_pll_ops = {
+ .recalc_rate = axxia_pllclk_recalc,
+};
+
+static struct clk *
+register_axxia_pllclk(struct device *dev, const char *name,
+ const char *parent_name, void __iomem *regs)
+{
+ struct clk_init_data init;
+ struct axxia_pllclk *pll;
+ struct clk *clk;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &clk_pll_ops;
+ init.flags = 0;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ pll->regs = regs;
+ pll->hw.init = &init;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
+
+
+/**
+ * struct axxia_divclk - Axxia clock divider
+ * @hw: clk_hw for the divider
+ * @regs: Pointer to control registers
+ */
+struct axxia_divclk {
+ struct clk_hw hw;
+ void __iomem *regs;
+ int shift;
+ int width;
+};
+
+#define to_axxia_divclk(_hw) container_of(_hw, struct axxia_divclk, hw)
+
+static unsigned long
+axxia_divclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct axxia_divclk *divclk = to_axxia_divclk(hw);
+ u32 ctrl, div;
+
+ ctrl = readl(divclk->regs);
+ div = 1 + ((ctrl >> divclk->shift) & GENMASK(divclk->width-1, 0));
+
+ return parent_rate / div;
+}
+
+const struct clk_ops axxia_divclk_ops = {
+ .recalc_rate = axxia_divclk_recalc_rate,
+};
+
+static struct clk *
+register_axxia_divclk(struct device *dev, const char *name,
+ const char *parent_name, void __iomem *regs,
+ int shift, int width)
+{
+ struct axxia_divclk *div;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ div = kzalloc(sizeof(struct axxia_divclk), GFP_KERNEL);
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &axxia_divclk_ops;
+ init.flags = CLK_IS_BASIC;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ div->regs = regs;
+ div->shift = shift;
+ div->width = width;
+ div->hw.init = &init;
+
+ /* register the clock */
+ clk = clk_register(dev, &div->hw);
+ if (IS_ERR(clk))
+ kfree(div);
+
+ return clk;
+}
+
+/**
+ * axxia_pll_clk_init - Axxia PLL clock setup function
+ * @node: pointer to device tree node
+ */
+static void __init
+axxia_pll_clk_init(struct device_node *node)
+{
+ struct clk *clk;
+ const char *parent_name;
+ void __iomem *regs;
+ const char *clk_name = node->name;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ if (!parent_name) {
+ pr_err("%s: no parent clock\n", node->name);
+ return;
+ }
+
+ regs = of_iomap(node, 0);
+ if (!regs) {
+ pr_err("%s: failed to map register\n", node->name);
+ return;
+ }
+
+ clk = register_axxia_pllclk(NULL, clk_name, parent_name, regs);
+ if (IS_ERR(clk)) {
+ pr_err("%s: register failed (%ld)\n", clk_name, PTR_ERR(clk));
+ iounmap(regs);
+ return;
+ }
+
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(axxia_pll_clk, "lsi,axxia-pll-clock", axxia_pll_clk_init);
+
+
+/**
+ * axxia_div_clk_init - Axxia clock divider setup function
+ * @node: device tree node for this clock
+ */
+static void __init
+axxia_div_clk_init(struct device_node *node)
+{
+ const char *parent_name;
+ void __iomem *reg;
+ u32 shift, width;
+ struct clk *clk;
+ const char *clk_name = node->name;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ if (!parent_name) {
+ pr_err("%s: no parent clock\n", node->name);
+ return;
+ }
+
+ reg = parse_and_map_reg(node, &shift, &width);
+ if (!reg)
+ return;
+
+ clk = register_axxia_divclk(NULL, clk_name, parent_name, reg,
+ shift, width);
+ if (IS_ERR(clk)) {
+ pr_err("%s: register failed (%ld)\n", clk_name, PTR_ERR(clk));
+ iounmap(reg);
+ return;
+ }
+
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(axxia_div_clk, "lsi,axxia-div-clock", axxia_div_clk_init);
+
+
+/**
+ * axxia_mux_clk_init - Clock mux setup function
+ * @node: device tree node for this clock
+ */
+static void __init
+axxia_mux_clk_init(struct device_node *node)
+{
+ void __iomem *reg;
+ struct clk *clk;
+ const char *parents[4];
+ int num_parents;
+ const char *clk_name = node->name;
+ u32 shift, width;
+ int i;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ for (i = 0; i < ARRAY_SIZE(parents); ++i) {
+ parents[i] = of_clk_get_parent_name(node, i);
+ if (!parents[i])
+ break;
+ }
+ num_parents = i;
+
+ reg = parse_and_map_reg(node, &shift, &width);
+ if (!reg)
+ return;
+
+ clk = clk_register_mux(NULL, clk_name, parents,
+ num_parents, 0, reg, shift, width,
+ CLK_MUX_READ_ONLY, NULL);
+ if (IS_ERR(clk)) {
+ pr_err("%s: register failed (%ld)\n", clk_name, PTR_ERR(clk));
+ iounmap(reg);
+ return;
+ }
+
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(pll_mux_clock, "lsi,axxia-mux-clock", axxia_mux_clk_init);
--
1.8.3.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 2/6] clk: Add clock driver for AXM55xx SoC
2014-05-14 18:37 ` [PATCH v3 2/6] clk: Add clock driver for " Anders Berg
@ 2014-05-14 20:08 ` Mike Turquette
2014-05-14 22:22 ` Anders Berg
0 siblings, 1 reply; 15+ messages in thread
From: Mike Turquette @ 2014-05-14 20:08 UTC (permalink / raw)
To: Anders Berg, Arnd Bergmann, Olof Johansson
Cc: Linus Walleij, Russell King, devicetree, linux-arm-kernel,
linux-kernel, Anders Berg, Mark Rutland
Quoting Anders Berg (2014-05-14 11:37:57)
> +Example:
> +
> + clk_ref0: clk_ref0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
Hi Anders,
The driver looks good. As for the DT binding, I am starting to request
that bindings for new hardware move away from the one-clock-per-node
method. I am not forcing anyone with stable bindings to migrate that
way, but it tends to make maintenance easier in the long run (e.g.
setting per-clock flags, etc).
Your clk_ref0 example looks good, assuming that it is an off-chip clock
that feeds into the rest of the clock generator.
> +
> + clk_cpu_pll: clk_cpu_pll@2010022000 {
> + compatible = "lsi,axxia-pll-clock";
> + #clock-cells = <0>;
> + clocks = <&clk_ref0>;
> + clock-output-names = "clk_cpu_pll";
> + reg = <0x20 0x10022000 0 0x2c>;
> + };
I assume the rest of your clocks are part of a clock generator IP block
inside of your chip. Have you looked at the QCOM binding? It is my
favorite binding these days. Here are some highlights:
See Documentation/devicetree/bindings/clock/qcom,gcc.txt.
>From arch/arm/boot/dts/qcom-msm8974.dtsi:
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8974";
#clock-cells = <1>;
#reset-cells = <1>;
reg = <0xfc400000 0x4000>;
};
...
serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <0 108 0x0>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
};
>From drivers/clk/qcom/gcc-msm8974.c:
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0704,
.clkr = {
.enable_reg = 0x0704,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_names = (const char *[]){
"blsp1_uart2_apps_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
>From include/dt-bindings/clock/qcom,gcc-msm8974.h:
#define GCC_BLSP1_UART2_APPS_CLK 103
Using this type of binding you only need to declare your clock generator
IP node in dts, and then define a mapping in the DT include chroot. Then
you can define your per-clock data inside of your clock driver instead
of putting all of the details inside of DT.
If you have a strong reason to do it the way that you originally posted
then let me know.
Regards,
Mike
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v3 2/6] clk: Add clock driver for AXM55xx SoC
2014-05-14 20:08 ` Mike Turquette
@ 2014-05-14 22:22 ` Anders Berg
2014-05-14 22:36 ` Mike Turquette
0 siblings, 1 reply; 15+ messages in thread
From: Anders Berg @ 2014-05-14 22:22 UTC (permalink / raw)
To: Mike Turquette
Cc: Arnd Bergmann, Olof Johansson, Linus Walleij, Russell King,
devicetree, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Anders Berg, Mark Rutland
On Wed, May 14, 2014 at 10:08 PM, Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> Quoting Anders Berg (2014-05-14 11:37:57)
>> +Example:
>> +
>> + clk_ref0: clk_ref0 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + };
>
> Hi Anders,
>
> The driver looks good. As for the DT binding, I am starting to request
> that bindings for new hardware move away from the one-clock-per-node
> method. I am not forcing anyone with stable bindings to migrate that
> way, but it tends to make maintenance easier in the long run (e.g.
> setting per-clock flags, etc).
>
> Your clk_ref0 example looks good, assuming that it is an off-chip clock
> that feeds into the rest of the clock generator.
>
>> +
>> + clk_cpu_pll: clk_cpu_pll@2010022000 {
>> + compatible = "lsi,axxia-pll-clock";
>> + #clock-cells = <0>;
>> + clocks = <&clk_ref0>;
>> + clock-output-names = "clk_cpu_pll";
>> + reg = <0x20 0x10022000 0 0x2c>;
>> + };
>
> I assume the rest of your clocks are part of a clock generator IP block
> inside of your chip. Have you looked at the QCOM binding? It is my
> favorite binding these days. Here are some highlights:
>
[...]
>
> Using this type of binding you only need to declare your clock generator
> IP node in dts, and then define a mapping in the DT include chroot. Then
> you can define your per-clock data inside of your clock driver instead
> of putting all of the details inside of DT.
>
> If you have a strong reason to do it the way that you originally posted
> then let me know.
>
No strong reason... I just happened to pick the keystone-clocks.dtsi
as an example when I wrote this. But I can rework this according to
your suggestions. I'll post it as a separate patch (thus dropping the
clk patch from this series). Ok?
Thanks,
Anders
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v3 2/6] clk: Add clock driver for AXM55xx SoC
2014-05-14 22:22 ` Anders Berg
@ 2014-05-14 22:36 ` Mike Turquette
0 siblings, 0 replies; 15+ messages in thread
From: Mike Turquette @ 2014-05-14 22:36 UTC (permalink / raw)
To: Anders Berg
Cc: Mark Rutland, devicetree, Russell King, Arnd Bergmann,
Anders Berg, Linus Walleij, linux-kernel, Olof Johansson,
linux-arm-kernel
Quoting Anders Berg (2014-05-14 15:22:16)
> On Wed, May 14, 2014 at 10:08 PM, Mike Turquette <mturquette@linaro.org> wrote:
> > Quoting Anders Berg (2014-05-14 11:37:57)
> >> +Example:
> >> +
> >> + clk_ref0: clk_ref0 {
> >> + compatible = "fixed-clock";
> >> + #clock-cells = <0>;
> >> + clock-frequency = <125000000>;
> >> + };
> >
> > Hi Anders,
> >
> > The driver looks good. As for the DT binding, I am starting to request
> > that bindings for new hardware move away from the one-clock-per-node
> > method. I am not forcing anyone with stable bindings to migrate that
> > way, but it tends to make maintenance easier in the long run (e.g.
> > setting per-clock flags, etc).
> >
> > Your clk_ref0 example looks good, assuming that it is an off-chip clock
> > that feeds into the rest of the clock generator.
> >
> >> +
> >> + clk_cpu_pll: clk_cpu_pll@2010022000 {
> >> + compatible = "lsi,axxia-pll-clock";
> >> + #clock-cells = <0>;
> >> + clocks = <&clk_ref0>;
> >> + clock-output-names = "clk_cpu_pll";
> >> + reg = <0x20 0x10022000 0 0x2c>;
> >> + };
> >
> > I assume the rest of your clocks are part of a clock generator IP block
> > inside of your chip. Have you looked at the QCOM binding? It is my
> > favorite binding these days. Here are some highlights:
> >
> [...]
> >
> > Using this type of binding you only need to declare your clock generator
> > IP node in dts, and then define a mapping in the DT include chroot. Then
> > you can define your per-clock data inside of your clock driver instead
> > of putting all of the details inside of DT.
> >
> > If you have a strong reason to do it the way that you originally posted
> > then let me know.
> >
>
> No strong reason... I just happened to pick the keystone-clocks.dtsi
> as an example when I wrote this. But I can rework this according to
> your suggestions. I'll post it as a separate patch (thus dropping the
> clk patch from this series). Ok?
Sounds great. Thanks for reworking it.
Regards,
Mike
>
> Thanks,
> Anders
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 3/6] ARM: dts: Device tree for AXM55xx.
2014-05-14 18:37 [PATCH v3 0/6] Add platform support for LSI AXM55xx Anders Berg
2014-05-14 18:37 ` [PATCH v3 1/6] ARM: Add platform support for LSI AXM55xx SoC Anders Berg
2014-05-14 18:37 ` [PATCH v3 2/6] clk: Add clock driver for " Anders Berg
@ 2014-05-14 18:37 ` Anders Berg
2014-05-14 18:37 ` [PATCH v3 4/6] ARM: axxia: Adding defconfig " Anders Berg
` (3 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Anders Berg @ 2014-05-14 18:37 UTC (permalink / raw)
To: Arnd Bergmann, Olof Johansson
Cc: devicetree, Russell King, Anders Berg, Linus Walleij,
linux-kernel, linux-arm-kernel
From: Anders Berg <anders.berg@lsi.com>
Add device tree for the Amarillo validation board with an AXM5516 SoC.
Signed-off-by: Anders Berg <anders.berg@lsi.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/axm5516-amarillo.dts | 51 ++++++
arch/arm/boot/dts/axm5516-cpus.dtsi | 204 ++++++++++++++++++++++
arch/arm/boot/dts/axm55xx.dtsi | 306 +++++++++++++++++++++++++++++++++
4 files changed, 562 insertions(+)
create mode 100644 arch/arm/boot/dts/axm5516-amarillo.dts
create mode 100644 arch/arm/boot/dts/axm5516-cpus.dtsi
create mode 100644 arch/arm/boot/dts/axm55xx.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index fbebf73..9672ca3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -50,6 +50,7 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
+dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
diff --git a/arch/arm/boot/dts/axm5516-amarillo.dts b/arch/arm/boot/dts/axm5516-amarillo.dts
new file mode 100644
index 0000000..a9d6047
--- /dev/null
+++ b/arch/arm/boot/dts/axm5516-amarillo.dts
@@ -0,0 +1,51 @@
+/*
+ * arch/arm/boot/dts/axm5516-amarillo.dts
+ *
+ * Copyright (C) 2013 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00400000;
+
+#include "axm55xx.dtsi"
+#include "axm5516-cpus.dtsi"
+
+/ {
+ model = "Amarillo AXM5516";
+ compatible = "lsi,axm5516-amarillo", "lsi,axm5516";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0x02 0x00000000>;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&serial3 {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/axm5516-cpus.dtsi
new file mode 100644
index 0000000..b85f360
--- /dev/null
+++ b/arch/arm/boot/dts/axm5516-cpus.dtsi
@@ -0,0 +1,204 @@
+/*
+ * arch/arm/boot/dts/axm5516-cpus.dtsi
+ *
+ * Copyright (C) 2013 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ core1 {
+ cpu = <&CPU1>;
+ };
+ core2 {
+ cpu = <&CPU2>;
+ };
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+ core1 {
+ cpu = <&CPU5>;
+ };
+ core2 {
+ cpu = <&CPU6>;
+ };
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+ cluster2 {
+ core0 {
+ cpu = <&CPU8>;
+ };
+ core1 {
+ cpu = <&CPU9>;
+ };
+ core2 {
+ cpu = <&CPU10>;
+ };
+ core3 {
+ cpu = <&CPU11>;
+ };
+ };
+ cluster3 {
+ core0 {
+ cpu = <&CPU12>;
+ };
+ core1 {
+ cpu = <&CPU13>;
+ };
+ core2 {
+ cpu = <&CPU14>;
+ };
+ core3 {
+ cpu = <&CPU15>;
+ };
+ };
+ };
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x00>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x01>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x02>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x03>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x100>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x101>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x102>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x103>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU8: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x200>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU9: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x201>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU10: cpu@202 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x202>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU11: cpu@203 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x203>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU12: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x300>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU13: cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x301>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU14: cpu@302 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x302>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ CPU15: cpu@303 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x303>;
+ clock-frequency= <1400000000>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
new file mode 100644
index 0000000..5d63887
--- /dev/null
+++ b/arch/arm/boot/dts/axm55xx.dtsi
@@ -0,0 +1,306 @@
+/*
+ * arch/arm/boot/dts/axm55xx.dtsi
+ *
+ * Copyright (C) 2013 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton64.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ timer = &timer0;
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* Reference clocks */
+
+ clk_ref0: clk_ref0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clk_ref1: clk_ref1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clk_ref2: clk_ref2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ /* PLLs */
+
+ clk_fab_pll: clk_fab_pll@2010021800 {
+ compatible = "lsi,axxia-pll-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_ref0>;
+ clock-output-names = "clk_fab_pll";
+ reg = <0x20 0x10021800 0 0x2c>;
+ };
+
+ clk_cpu_pll: clk_cpu_pll@2010022000 {
+ compatible = "lsi,axxia-pll-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_ref0>;
+ clock-output-names = "clk_cpu_pll";
+ reg = <0x20 0x10022000 0 0x2c>;
+ };
+
+ clk_sys_pll: clk_sys_pll@2010022800 {
+ compatible = "lsi,axxia-pll-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_ref0>;
+ clock-output-names = "clk_sys_pll";
+ reg = <0x20 0x10022800 0 0x2c>;
+ };
+
+ clk_sm0_pll: sm0_pll@2010023000 {
+ compatible = "lsi,axxia-pll-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_ref2>;
+ clock-output-names = "clk_sm0_pll";
+ reg = <0x20 0x10023000 0 0x2c>;
+ };
+
+ clk_sm1_pll: sm1_pll@2010023800 {
+ compatible = "lsi,axxia-pll-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_ref1>;
+ clock-output-names = "clk_sm1_pll";
+ reg = <0x20 0x10023800 0 0x2c>;
+ };
+
+ /* CPU clock */
+
+ clk_cpu_div: cpu {
+ compatible = "lsi,axxia-div-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_cpu_pll>;
+ clock-output-names = "clk_cpu_div";
+ reg = <0x20 0x10030008 0 0x4>;
+ lsi,bit-shift = <0>;
+ lsi,bit-width = <4>;
+ };
+
+ clk_cpu: clk_cpu0@2010030000 {
+ compatible = "lsi,axxia-mux-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_ref0>,
+ <&clk_cpu_pll>,
+ <&clk_cpu_div>,
+ <&clk_cpu_div>;
+ clock-output-names = "clk_cpu";
+ reg = <0x20 0x10030000 0 0x4>;
+ lsi,bit-shift = <0>;
+ lsi,bit-width = <2>;
+ };
+
+ /* Peripheral clock */
+
+ clk_per_div: peripheral {
+ compatible = "lsi,axxia-div-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_sm1_pll>;
+ clock-output-names = "clk_per_div";
+ reg = <0x20 0x1003000c 0 0x4>;
+ lsi,bit-shift = <12>;
+ lsi,bit-width = <4>;
+ };
+
+ clk_per: clk_per@2010030004 {
+ compatible = "lsi,axxia-mux-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_ref1>, <&clk_per_div>;
+ clock-output-names = "clk_per";
+ reg = <0x20 0x10030004 0 0x4>;
+ lsi,bit-shift = <6>;
+ lsi,bit-width = <1>;
+ };
+
+ /* MMC clock */
+
+ clk_mmc_div: emmc {
+ compatible = "lsi,axxia-div-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_sm1_pll>;
+ clock-output-names = "clk_mmc_div";
+ reg = <0x20 0x1003000c 0 0x4>;
+ lsi,bit-shift = <16>;
+ lsi,bit-width = <4>;
+ };
+
+ clk_mmc: clk_mmc@2010030004 {
+ compatible = "lsi,axxia-mux-clock";
+ #clock-cells = <0>;
+ clocks = <&clk_ref1>, <&clk_mmc_div>;
+ clock-output-names = "clk_mmc";
+ reg = <0x20 0x10030004 0 0x4>;
+ lsi,bit-shift = <9>;
+ lsi,bit-width = <1>;
+ };
+
+ };
+
+ gic: interrupt-controller@2001001000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x20 0x01001000 0 0x1000>,
+ <0x20 0x01002000 0 0x1000>,
+ <0x20 0x01004000 0 0x2000>,
+ <0x20 0x01006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts =
+ <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ device_type = "soc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ syscon: syscon@2010030000 {
+ compatible = "lsi,axxia-syscon", "syscon";
+ reg = <0x20 0x10030000 0 0x2000>;
+ };
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ serial0: uart@2010080000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x20 0x10080000 0 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_per>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ serial1: uart@2010081000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x20 0x10081000 0 0x1000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_per>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ serial2: uart@2010082000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x20 0x10082000 0 0x1000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_per>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ serial3: uart@2010083000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x20 0x10083000 0 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_per>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ timer0: timer@2010091000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x20 0x10091000 0 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_per>;
+ clock-names = "apb_pclk";
+ status = "okay";
+ };
+
+ gpio0: gpio@2010092000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x20 0x10092000 0x00 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_per>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio1: gpio@2010093000 {
+ #gpio-cells = <2>;
+ compatible = "arm,pl061", "arm,primecell";
+ gpio-controller;
+ reg = <0x20 0x10093000 0x00 0x1000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_per>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
+
+/*
+ Local Variables:
+ mode: C
+ End:
+*/
--
1.8.3.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 4/6] ARM: axxia: Adding defconfig for AXM55xx
2014-05-14 18:37 [PATCH v3 0/6] Add platform support for LSI AXM55xx Anders Berg
` (2 preceding siblings ...)
2014-05-14 18:37 ` [PATCH v3 3/6] ARM: dts: Device tree for AXM55xx Anders Berg
@ 2014-05-14 18:37 ` Anders Berg
2014-05-14 18:38 ` [PATCH v3 5/6] power: reset: Add Axxia system reset driver Anders Berg
` (2 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Anders Berg @ 2014-05-14 18:37 UTC (permalink / raw)
To: Arnd Bergmann, Olof Johansson
Cc: Linus Walleij, Russell King, devicetree, linux-arm-kernel,
linux-kernel, Anders Berg
From: Anders Berg <anders.berg@lsi.com>
Add a defconfig file for the LSI Axxia family of devices (CONFIG_ARCH_AXXIA).
Signed-off-by: Anders Berg <anders.berg@lsi.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/configs/axm55xx_defconfig | 248 +++++++++++++++++++++++++++++++++++++
1 file changed, 248 insertions(+)
create mode 100644 arch/arm/configs/axm55xx_defconfig
diff --git a/arch/arm/configs/axm55xx_defconfig b/arch/arm/configs/axm55xx_defconfig
new file mode 100644
index 0000000..d3260d7
--- /dev/null
+++ b/arch/arm/configs/axm55xx_defconfig
@@ -0,0 +1,248 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
+CONFIG_AUDIT=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_AXXIA=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_ERRATA_798181=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_AXXIA=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=16
+CONFIG_HOTPLUG_CPU=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_HIGHMEM=y
+CONFIG_KSM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_MISC=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETWORK_PHY_TIMESTAMPING=y
+CONFIG_BRIDGE=y
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_AFS_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_VETH=y
+CONFIG_VIRTIO_NET=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_BROADCOM_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_AXXIA=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_DP83640_PHY=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PL061=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_AXXIA=y
+CONFIG_SENSORS_ADT7475=y
+CONFIG_SENSORS_JC42=y
+CONFIG_SENSORS_LM75=y
+CONFIG_PMBUS=y
+CONFIG_SENSORS_LTC2978=y
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DRAGONRISE=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_KYE=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_TWINHAN=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_ORTEK=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
+CONFIG_HID_SMARTJOYPLUS=y
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
+CONFIG_HID_ZEROPLUS=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_HCD_AXXIA=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_DMADEVICES=y
+CONFIG_PL330_DMA=y
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_MAILBOX=y
+CONFIG_PL320_MBOX=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_FSCACHE=y
+CONFIG_FSCACHE_STATS=y
+CONFIG_FSCACHE_HISTOGRAM=y
+CONFIG_FSCACHE_DEBUG=y
+CONFIG_FSCACHE_OBJECT_LIST=y
+CONFIG_CACHEFILES=y
+CONFIG_CACHEFILES_HISTOGRAM=y
+CONFIG_ISO9660_FS=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFS_FSCACHE=y
+CONFIG_SUNRPC_DEBUG=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
--
1.8.3.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 5/6] power: reset: Add Axxia system reset driver
2014-05-14 18:37 [PATCH v3 0/6] Add platform support for LSI AXM55xx Anders Berg
` (3 preceding siblings ...)
2014-05-14 18:37 ` [PATCH v3 4/6] ARM: axxia: Adding defconfig " Anders Berg
@ 2014-05-14 18:38 ` Anders Berg
2014-05-14 18:38 ` [PATCH v3 6/6] ARM: dts: axxia: Add reset controller Anders Berg
2014-05-14 18:56 ` [PATCH v3 0/6] Add platform support for LSI AXM55xx Arnd Bergmann
6 siblings, 0 replies; 15+ messages in thread
From: Anders Berg @ 2014-05-14 18:38 UTC (permalink / raw)
To: Arnd Bergmann, Olof Johansson
Cc: Linus Walleij, Russell King, devicetree, linux-arm-kernel,
linux-kernel, Anders Berg, Dmitry Eremin-Solenikov,
David Woodhouse
From: Anders Berg <anders.berg@lsi.com>
Add Axxia (AXM55xx) SoC system reset driver. This driver handles only system
reboot (and not power-off).
Signed-off-by: Anders Berg <anders.berg@lsi.com>
Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
.../bindings/power_supply/axxia-reset.txt | 20 +++++
drivers/power/reset/Kconfig | 8 ++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/axxia-reset.c | 97 ++++++++++++++++++++++
4 files changed, 126 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power_supply/axxia-reset.txt
create mode 100644 drivers/power/reset/axxia-reset.c
diff --git a/Documentation/devicetree/bindings/power_supply/axxia-reset.txt b/Documentation/devicetree/bindings/power_supply/axxia-reset.txt
new file mode 100644
index 0000000..47e720d
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/axxia-reset.txt
@@ -0,0 +1,20 @@
+Axxia Restart Driver
+
+This driver can do reset of the Axxia SoC. It uses the registers in the syscon
+block to initiate a chip reset.
+
+Required Properties:
+ -compatible: "lsi,axm55xx-reset"
+ -syscon: phandle to the syscon node.
+
+Example:
+
+ syscon: syscon@2010030000 {
+ compatible = "lsi,axxia-syscon", "syscon";
+ reg = <0x20 0x10030000 0 0x2000>;
+ };
+
+ reset: reset@2010031000 {
+ compatible = "lsi,axm55xx-reset";
+ syscon = <&syscon>;
+ };
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index fa0e4e0..49b46e6 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -12,6 +12,14 @@ config POWER_RESET_AS3722
help
This driver supports turning off board via a ams AS3722 power-off.
+config POWER_RESET_AXXIA
+ bool "LSI Axxia reset driver"
+ depends on POWER_RESET && ARCH_AXXIA
+ help
+ This driver supports restart for Axxia SoC.
+
+ Say Y if you have an Axxia family SoC.
+
config POWER_RESET_GPIO
bool "GPIO power-off driver"
depends on OF_GPIO && POWER_RESET
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index a5b4a77..16c0516 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_POWER_RESET_AS3722) += as3722-poweroff.o
+obj-$(CONFIG_POWER_RESET_AXXIA) += axxia-reset.o
obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
diff --git a/drivers/power/reset/axxia-reset.c b/drivers/power/reset/axxia-reset.c
new file mode 100644
index 0000000..a16eb50
--- /dev/null
+++ b/drivers/power/reset/axxia-reset.c
@@ -0,0 +1,97 @@
+/*
+ * Reset driver for Axxia devices
+ *
+ * Copyright (C) 2014 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+
+#include <asm/system_misc.h>
+
+
+#define SC_CRIT_WRITE_KEY 0x1000
+#define SC_LATCH_ON_RESET 0x1004
+#define SC_RESET_CONTROL 0x1008
+#define RSTCTL_RST_ZERO (1<<3)
+#define RSTCTL_RST_FAB (1<<2)
+#define RSTCTL_RST_CHIP (1<<1)
+#define RSTCTL_RST_SYS (1<<0)
+#define SC_EFUSE_INT_STATUS 0x180c
+#define EFUSE_READ_DONE (1<<31)
+
+static struct regmap *syscon;
+
+static void do_axxia_restart(enum reboot_mode reboot_mode, const char *cmd)
+{
+ /* Access Key (0xab) */
+ regmap_write(syscon, SC_CRIT_WRITE_KEY, 0xab);
+ /* Select internal boot from 0xffff0000 */
+ regmap_write(syscon, SC_LATCH_ON_RESET, 0x00000040);
+ /* Assert ResetReadDone (to avoid hanging in boot ROM) */
+ regmap_write(syscon, SC_EFUSE_INT_STATUS, EFUSE_READ_DONE);
+ /* Assert chip reset */
+ regmap_update_bits(syscon, SC_RESET_CONTROL,
+ RSTCTL_RST_CHIP, RSTCTL_RST_CHIP);
+}
+
+static int axxia_reset_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *dev_np = dev->of_node;
+ struct device_node *syscon_np;
+
+ syscon_np = of_parse_phandle(dev_np, "syscon", 0);
+ if (!syscon_np) {
+ pr_err("%s: no handle to syscon node\n", dev_np->name);
+ return -ENODEV;
+ }
+
+ syscon = syscon_node_to_regmap(syscon_np);
+ if (IS_ERR(syscon)) {
+ pr_err("%s: could not locate syscon regmap\n", dev_np->name);
+ return PTR_ERR(syscon);
+ }
+
+ arm_pm_restart = do_axxia_restart;
+
+ return 0;
+}
+
+static const struct of_device_id of_axxia_reset_match[] = {
+ { .compatible = "lsi,axm55xx-reset", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, of_axxia_reset_match);
+
+static struct platform_driver axxia_reset_driver = {
+ .probe = axxia_reset_probe,
+ .driver = {
+ .name = "axxia-reset",
+ .of_match_table = of_match_ptr(of_axxia_reset_match),
+ },
+};
+
+static int __init axxia_reset_init(void)
+{
+ return platform_driver_register(&axxia_reset_driver);
+}
+device_initcall(axxia_reset_init);
--
1.8.3.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 6/6] ARM: dts: axxia: Add reset controller
2014-05-14 18:37 [PATCH v3 0/6] Add platform support for LSI AXM55xx Anders Berg
` (4 preceding siblings ...)
2014-05-14 18:38 ` [PATCH v3 5/6] power: reset: Add Axxia system reset driver Anders Berg
@ 2014-05-14 18:38 ` Anders Berg
2014-05-14 18:56 ` [PATCH v3 0/6] Add platform support for LSI AXM55xx Arnd Bergmann
6 siblings, 0 replies; 15+ messages in thread
From: Anders Berg @ 2014-05-14 18:38 UTC (permalink / raw)
To: Arnd Bergmann, Olof Johansson
Cc: Linus Walleij, Russell King, devicetree, linux-arm-kernel,
linux-kernel, Anders Berg
From: Anders Berg <anders.berg@lsi.com>
Add the reset controller to the AXM5xx device tree.
Signed-off-by: Anders Berg <anders.berg@lsi.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/axm55xx.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
index 5d63887..bd1e07d 100644
--- a/arch/arm/boot/dts/axm55xx.dtsi
+++ b/arch/arm/boot/dts/axm55xx.dtsi
@@ -208,6 +208,11 @@
reg = <0x20 0x10030000 0 0x2000>;
};
+ reset: reset@2010031000 {
+ compatible = "lsi,axm55xx-reset";
+ syscon = <&syscon>;
+ };
+
amba {
compatible = "arm,amba-bus";
#address-cells = <2>;
--
1.8.3.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 0/6] Add platform support for LSI AXM55xx
2014-05-14 18:37 [PATCH v3 0/6] Add platform support for LSI AXM55xx Anders Berg
` (5 preceding siblings ...)
2014-05-14 18:38 ` [PATCH v3 6/6] ARM: dts: axxia: Add reset controller Anders Berg
@ 2014-05-14 18:56 ` Arnd Bergmann
2014-05-14 19:21 ` Anders Berg
2014-05-15 12:37 ` Anders Berg
6 siblings, 2 replies; 15+ messages in thread
From: Arnd Bergmann @ 2014-05-14 18:56 UTC (permalink / raw)
To: Anders Berg
Cc: Olof Johansson, Linus Walleij, Russell King, devicetree,
linux-arm-kernel, linux-kernel
On Wednesday 14 May 2014 20:37:55 Anders Berg wrote:
>
> This is version 3 of this series to introduces basic platform support for the LSI
> AXM5516 SoC.
>
> No major changes since v2. Ready to be applied to the arm-soc tree?
I think it's good, but I'm not sure if we should put them all into arm-soc.
There are no dependencies between the drivers that I can see, so why not
merge the clock and reset drivers through the individual subsystem maintainers?
We can take patches 1/3/4/6, and the others if there is a good reason
not to have the regular maintainers pick them up.
The hip04 platform series is also adding a multi_v7_lpae_defconfig file.
it would be good to add axxia to that config and also to the regular
multi_v7_defconfig, but that can be an add-on patch once we have merged
hip04.
Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v3 0/6] Add platform support for LSI AXM55xx
2014-05-14 18:56 ` [PATCH v3 0/6] Add platform support for LSI AXM55xx Arnd Bergmann
@ 2014-05-14 19:21 ` Anders Berg
2014-05-15 12:37 ` Anders Berg
1 sibling, 0 replies; 15+ messages in thread
From: Anders Berg @ 2014-05-14 19:21 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Olof Johansson, Linus Walleij, Russell King, devicetree,
linux-arm-kernel, linux-kernel
On Wed, May 14, 2014 at 8:56 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Wednesday 14 May 2014 20:37:55 Anders Berg wrote:
>>
>> This is version 3 of this series to introduces basic platform support for the LSI
>> AXM5516 SoC.
>>
>> No major changes since v2. Ready to be applied to the arm-soc tree?
>
> I think it's good, but I'm not sure if we should put them all into arm-soc.
> There are no dependencies between the drivers that I can see, so why not
> merge the clock and reset drivers through the individual subsystem maintainers?
>
> We can take patches 1/3/4/6, and the others if there is a good reason
> not to have the regular maintainers pick them up.
Sure, that'll work to take 1,3,4,6.
>
> The hip04 platform series is also adding a multi_v7_lpae_defconfig file.
> it would be good to add axxia to that config and also to the regular
> multi_v7_defconfig, but that can be an add-on patch once we have merged
> hip04.
Ok.
Thanks,
Anders
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 0/6] Add platform support for LSI AXM55xx
2014-05-14 18:56 ` [PATCH v3 0/6] Add platform support for LSI AXM55xx Arnd Bergmann
2014-05-14 19:21 ` Anders Berg
@ 2014-05-15 12:37 ` Anders Berg
[not found] ` <CAE0=X_15Yk3VhHTwG-piA_eYL1mKW9wu_Szp-yL0YyfL8m0ecA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
1 sibling, 1 reply; 15+ messages in thread
From: Anders Berg @ 2014-05-15 12:37 UTC (permalink / raw)
To: Arnd Bergmann, Mike Turquette
Cc: Olof Johansson, Linus Walleij, Russell King, devicetree,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On Wed, May 14, 2014 at 8:56 PM, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
> On Wednesday 14 May 2014 20:37:55 Anders Berg wrote:
>>
>> This is version 3 of this series to introduces basic platform support for the LSI
>> AXM5516 SoC.
>>
>> No major changes since v2. Ready to be applied to the arm-soc tree?
>
> I think it's good, but I'm not sure if we should put them all into arm-soc.
> There are no dependencies between the drivers that I can see, so why not
> merge the clock and reset drivers through the individual subsystem maintainers?
>
After suggestions from Mike on the clk driver (and it's dts binding)
I've done an updated clock driver patch - and a dependency surfaced...
The file <dt-bindings/clock/lsi,axm5516-clks.h>. Which way should this
take, arm-soc or Mikes clk tree? Perhaps this is a reason to take it
all through arm-soc?
/Anders
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^ permalink raw reply [flat|nested] 15+ messages in thread