Re: [PATCHv3 1/3] ARM: mm: allow sub-architectures to override PCI I/O memory type

[Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>]

On Thu, May 15, 2014 at 02:51:30PM +0100, Thomas Petazzoni wrote:
> On Thu, 15 May 2014 15:21:25 +0200, Arnd Bergmann wrote:
> > On Thursday 15 May 2014 11:18:37 Thomas Petazzoni wrote:
> > > @@ -445,7 +452,7 @@ int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr)
> > >         return ioremap_page_range(PCI_IO_VIRT_BASE + offset,
> > >                                   PCI_IO_VIRT_BASE + offset + SZ_64K,
> > >                                   phys_addr,
> > > -                                 __pgprot(get_mem_type(MT_DEVICE)->prot_pte));
> > > +                                 __pgprot(get_mem_type(pci_ioremap_mem_type)->prot_pte));
> > >  }
> > >  EXPORT_SYMBOL_GPL(pci_ioremap_io);
> > > 
> > 
> > As discussed on IRC, I think we'd be better off making this a strong-ordered
> > mapping for all platforms unconditionally. The PCI I/O space semantics
> > require non-posted writes, which is the main difference between device
> > and SO mappings, so the same fix is required both for mvebu as a workaround
> > for the deadlock as well as for everyone else as a fix for an incorrect
> > PCI behavior.
> 
> Ok, I'll take that into account when posting a v4.

Actually, I don't think this reasoning is correct. The memory type here
applies to accesses mastered by the CPU onto AXI -- it is the job of the
AXI/PCI bridge (i.e. the host controller) to ensure that writes are not
posted, so this is irrelevant.

Of course, the erratum in question requires SO memory, but that's an
entirely different problem. The default should remain as device memory.

Will
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