From mboxrd@z Thu Jan 1 00:00:00 1970 From: Catalin Marinas Subject: Re: [PATCHv5 2/4] ARM: mm: add support for HW coherent systems in PL310 Date: Mon, 19 May 2014 10:37:28 +0100 Message-ID: <20140519093728.GC5113@arm.com> References: <1400487234-4501-1-git-send-email-thomas.petazzoni@free-electrons.com> <1400487234-4501-3-git-send-email-thomas.petazzoni@free-electrons.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1400487234-4501-3-git-send-email-thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thomas Petazzoni Cc: Russell King , Will Deacon , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Grant Likely , Rob Herring , Arnd Bergmann , Albin Tonnerre , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Tawfik Bayouk , Nadav Haklai , Lior Amsalem , Ezequiel Garcia List-Id: devicetree@vger.kernel.org On Mon, May 19, 2014 at 09:13:52AM +0100, Thomas Petazzoni wrote: > When a PL310 cache is used on a system that provides hardware > coherency, the outer cache sync operation is useless, and can be > skipped. Moreover, on some systems, it is harmful as it causes > deadlocks between the Marvell coherency mechanism, the Marvell PCIe > controller and the Cortex-A9. > > To avoid this, this commit introduces a new Device Tree property > 'arm,io-coherent' for the L2 cache controller node, valid only for the > PL310 cache. It identifies the usage of the PL310 cache in an I/O > coherent configuration. Internally, it makes the driver disable the > outer cache sync operation. > > Note that technically speaking, a fully coherent system wouldn't > require any of the other .outer_cache operations. However, in > practice, when booting secondary CPUs, these are not yet coherent, and > therefore a set of cache maintenance operations are necessary at this > point. This explains why we keep the other .outer_cache operations and > only ->sync is disabled. > > While in theory any write to a PL310 register could cause the > deadlock, in practice, disabling ->sync is sufficient to workaround > the deadlock, since the other cache maintenance operations are only > used in very specific situations. > > Signed-off-by: Thomas Petazzoni Acked-by: Catalin Marinas -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html