From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jisheng Zhang Subject: Re: [PATCH 1/5] ARM: berlin: add SMP support Date: Tue, 3 Jun 2014 15:18:26 +0800 Message-ID: <20140603151826.100a7fd5@xhacker> References: <1401700866-24804-1-git-send-email-antoine.tenart@free-electrons.com> <1401700866-24804-2-git-send-email-antoine.tenart@free-electrons.com> <20140603143113.0b2aeb74@xhacker> <20140603071017.GA15966@kwain> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <20140603071017.GA15966@kwain> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Antoine =?UTF-8?B?VMOpbmFydA==?= Cc: "sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" , "alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org" , "thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org" , Jimmy Xu , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: devicetree@vger.kernel.org On Tue, 3 Jun 2014 00:10:17 -0700 Antoine T=C3=A9nart wrote: > Hi Jisheng, >=20 > On Tue, Jun 03, 2014 at 02:31:13PM +0800, Jisheng Zhang wrote: > > On Mon, 2 Jun 2014 02:21:02 -0700 > > Antoine T=C3=A9nart wrote: > > > + > > > +extern void berlin_secondary_startup(void); > > > +extern u32 boot_inst; > > > + > > > +static void __iomem *cpu_ctrl; > > > + > > > +static inline void berlin_reset_cpu(unsigned int cpu) > > > +{ > > > + u32 val; > > > + > > > + val =3D readl(cpu_ctrl + CPU_RESET); > > > + val |=3D BIT(cpu_logical_map(cpu)); > > > + writel(val, cpu_ctrl + CPU_RESET); > >=20 > > "writel(BIT(cpu_logical_map(cpu)), cpu_ctrl + CPU_RESET)" is enough= =2E > > we don't need to read and modify, because we writing 0 has no any e= ffect. >=20 > The reset bit is automatically cleared but I dumped the register valu= e > and it wasn't 0x0, that's why I preferred to read first and only set = the > reset bit. >=20 > > > + > > > + /* > > > + * Write the first instruction the CPU will execute after being > > > reseted > > > + * in the reset exception register. > > > + */ > > > + writel(boot_inst, vectors_base + RESET_VECT); > >=20 > > Is it better to let bootloader/firmware handle this writing. Then, = we can > > also remove the tricky boot_inst in headsmp.S. >=20 > We thought about it, and since it can be difficult to update the > bootloader for some boards, like BG2 based ones, we preferred to incl= ude > this here. >=20 > Thanks! >=20 > Antoine >=20 Got your points. Thanks very much -- To unsubscribe from this list: send the line "unsubscribe devicetree" i= n the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html