From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: Jisheng Zhang <jszhang@marvell.com>
Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
sebastian.hesselbarth@gmail.com,
alexandre.belloni@free-electrons.com,
antoine.tenart@free-electrons.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
Date: Thu, 12 Jun 2014 10:44:23 +0100 [thread overview]
Message-ID: <20140612094423.GC23430@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <1402565920-5636-1-git-send-email-jszhang@marvell.com>
On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> For all BG2Q SoCs, 2 cycles is the best/correct value
It would be a good idea to set all these parameters if you need to set
them at all - in other words, setting arm,dirty-latency as well, as
that's all part of the timing specification.
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
next prev parent reply other threads:[~2014-06-12 9:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-12 9:38 [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles Jisheng Zhang
2014-06-12 9:44 ` Russell King - ARM Linux [this message]
[not found] ` <20140612094423.GC23430-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2014-06-12 10:15 ` Jisheng Zhang
2014-06-12 10:19 ` Jisheng Zhang
2014-06-16 11:24 ` Sebastian Hesselbarth
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