[PATCH v3] crypto: Add Allwinner Security System crypto accelerator

[PATCH v3] crypto: Add Allwinner Security System crypto accelerator

[LABBE Corentin]

Hello

This is the driver for the Security System included in Allwinner SoC A20.
The Security System (SS for short) is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on others Allwinner SoC: 
- A10s and A31 diagram speak about it with precisions (AES/DES/3DES/Md5/SHA1/PRNG)
- A10 and A13 manual give the same datasheet for SS than A20
- A23 speak about a security system but without precisions
But I do not have access on any of those hardware, tests are welcome.

This driver currently supports:
- MD5 and SHA1 hash algorithms
- AES block cipher in CBC mode with 128/196/256bits keys.
- DES and 3DES block cipher in CBC mode
- PRNG
The driver exposes all those algorithms through the kernel cryptographic API.

The driver support only CPU driven (aka poll mode) transfer mode since the DMA engine of the A20 does not have a driver yet.

Changes since v2:
- Fix Makefile and Kconfig for static kernel.

Changes since v1:
- annotate ss->base as __iomem
- regroup all mutex in the ss_ctx structure
- splited driver in 7 modules (core md5 sha1 aes des 3des prng) in sunxi-ss directory
- use dev_exit_p() for .remove
- added missing CRYPTO_BLKCIPHER dep in Kconfig
- use ahash instead of shash
- use ablkcipher instead of blkcipher
- use crypto_rng_ctx instead of crypto_tfm_ctx
- set seed as an u32
- drop useless comment decoration
- drop useless debug
- ss_ctx is now a static pointer and whole structure being allocated
- fix the platform_get_resource/devm_ioremap_resource pattern
- invert getting die id and configuring clock
- set clock value as a const unsigned long
- add MODULE_ALIAS
- use define names more consistency (SS_xxx)
- fix PRNG errors
- respell SS to Security System in DT documentation

[PATCH v3 1/4] crypto: Add Allwinner Security System crypto accelerator

[LABBE Corentin]

Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG algorithms.

Signed-off-by: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/crypto/sunxi-ss/Makefile               |  19 ++
 drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c | 118 ++++++++
 drivers/crypto/sunxi-ss/sunxi-ss-cipher-aes.c  | 130 +++++++++
 drivers/crypto/sunxi-ss/sunxi-ss-cipher-des.c  | 118 ++++++++
 drivers/crypto/sunxi-ss/sunxi-ss-cipher.c      | 368 +++++++++++++++++++++++++
 drivers/crypto/sunxi-ss/sunxi-ss-cipher.h      |   8 +
 drivers/crypto/sunxi-ss/sunxi-ss-hash-md5.c    |  69 +++++
 drivers/crypto/sunxi-ss/sunxi-ss-hash-sha1.c   |  69 +++++
 drivers/crypto/sunxi-ss/sunxi-ss-hash.c        | 234 ++++++++++++++++
 drivers/crypto/sunxi-ss/sunxi-ss-hash.h        |   9 +
 drivers/crypto/sunxi-ss/sunxi-ss-rng.c         | 115 ++++++++
 drivers/crypto/sunxi-ss/sunxi-ss.c             | 190 +++++++++++++
 drivers/crypto/sunxi-ss/sunxi-ss.h             | 161 +++++++++++
 13 files changed, 1608 insertions(+)
 create mode 100644 drivers/crypto/sunxi-ss/Makefile
 create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c
 create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-cipher-aes.c
 create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-cipher-des.c
 create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-cipher.c
 create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-cipher.h
 create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-hash-md5.c
 create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-hash-sha1.c
 create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-hash.c
 create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-hash.h
 create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-rng.c
 create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss.c
 create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss.h

diff --git a/drivers/crypto/sunxi-ss/Makefile b/drivers/crypto/sunxi-ss/Makefile
new file mode 100644
index 0000000..21e0c3c
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/Makefile
@@ -0,0 +1,19 @@
+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS) += sunxi-ss.o
+
+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS_PRNG) += sunxi-ss-rng.o
+
+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS_CIPHER) += sunxi-ss-cipher.o
+
+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS_DES) += sunxi-ss-des.o
+sunxi-ss-des-y += sunxi-ss-cipher-des.o
+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS_3DES) += sunxi-ss-3des.o
+sunxi-ss-3des-y += sunxi-ss-cipher-3des.o
+
+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS_AES) += sunxi-ss-aes.o
+sunxi-ss-aes-y += sunxi-ss-cipher-aes.o
+
+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS_HASH) += sunxi-ss-hash.o
+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS_MD5) += sunxi-ss-md5.o
+sunxi-ss-md5-y += sunxi-ss-hash-md5.o
+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS_SHA1) += sunxi-ss-sha1.o
+sunxi-ss-sha1-y += sunxi-ss-hash-sha1.o
diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c b/drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c
new file mode 100644
index 0000000..fcdc8a4
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c
@@ -0,0 +1,118 @@
+/*
+ * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
+ *
+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * Support AES cipher with 128,192,256 bits keysize.
+ * Support MD5 and SHA1 hash algorithms.
+ * Support DES and 3DES
+ * Support PRNG
+ *
+ * You could find the datasheet at
+ * http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation version 2 of the License
+ */
+#include "sunxi-ss-cipher.h"
+
+/* check and set the 3DES key, prepare the mode to be used */
+static int sunxi_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
+		unsigned int keylen)
+{
+	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
+	if (keylen != 3 * DES_KEY_SIZE) {
+		dev_err(ss->dev, "Invalid keylen %u\n", keylen);
+		crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
+		return -EINVAL;
+	}
+	op->keylen = keylen;
+	memcpy(op->key, key, keylen);
+	return 0;
+}
+
+static int sunxi_des3_cbc_encrypt(struct ablkcipher_request *areq)
+{
+	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
+	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
+
+	if (areq->info == NULL) {
+		dev_info(ss->dev, "Empty IV\n");
+		return -EINVAL;
+	}
+
+	op->mode |= SS_ENCRYPTION;
+	op->mode |= SS_OP_3DES;
+	op->mode |= SS_CBC;
+
+	return sunxi_des_poll(areq);
+}
+
+static int sunxi_des3_cbc_decrypt(struct ablkcipher_request *areq)
+{
+	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
+	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
+
+	if (areq->info == NULL) {
+		dev_info(ss->dev, "Empty IV\n");
+		return -EINVAL;
+	}
+
+	op->mode |= SS_DECRYPTION;
+	op->mode |= SS_OP_3DES;
+	op->mode |= SS_CBC;
+
+	return sunxi_des_poll(areq);
+}
+
+static struct crypto_alg sunxi_des3_alg = {
+	.cra_name = "cbc(des3_ede)",
+	.cra_driver_name = "cbc-des3-sunxi-ss",
+	.cra_priority = 300,
+	.cra_blocksize = DES3_EDE_BLOCK_SIZE,
+	.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
+	.cra_ctxsize = sizeof(struct sunxi_req_ctx),
+	.cra_module = THIS_MODULE,
+	.cra_type = &crypto_ablkcipher_type,
+	.cra_init = sunxi_cipher_init,
+	.cra_exit = sunxi_cipher_exit,
+	.cra_alignmask = 3,
+	.cra_u.ablkcipher = {
+		.min_keysize    = DES3_EDE_KEY_SIZE,
+		.max_keysize    = DES3_EDE_KEY_SIZE,
+		.ivsize         = DES3_EDE_BLOCK_SIZE,
+		.setkey         = sunxi_des3_setkey,
+		.encrypt        = sunxi_des3_cbc_encrypt,
+		.decrypt        = sunxi_des3_cbc_decrypt,
+	}
+};
+
+static int sunxi_ss_3des_init(void)
+{
+	int err = 0;
+	if (ss == NULL) {
+		pr_err("Cannot get Security System structure\n");
+		return -ENODEV;
+	}
+	err = crypto_register_alg(&sunxi_des3_alg);
+	if (err)
+		dev_err(ss->dev, "crypto_register_alg error for DES3\n");
+	else
+		dev_dbg(ss->dev, "Registred DES3\n");
+	return err;
+}
+
+static void __exit sunxi_ss_3des_exit(void)
+{
+	crypto_unregister_alg(&sunxi_des3_alg);
+}
+
+module_init(sunxi_ss_3des_init);
+module_exit(sunxi_ss_3des_exit);
+
+MODULE_DESCRIPTION("Allwinner Security System crypto accelerator DES3 module");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
+MODULE_ALIAS("3des");
diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-cipher-aes.c b/drivers/crypto/sunxi-ss/sunxi-ss-cipher-aes.c
new file mode 100644
index 0000000..eb52209
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sunxi-ss-cipher-aes.c
@@ -0,0 +1,130 @@
+/*
+ * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
+ *
+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * Support AES cipher with 128,192,256 bits keysize.
+ * Support MD5 and SHA1 hash algorithms.
+ * Support DES and 3DES
+ * Support PRNG
+ *
+ * You could find the datasheet at
+ * http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation version 2 of the License
+ */
+#include "sunxi-ss-cipher.h"
+
+static int sunxi_aes_cbc_encrypt(struct ablkcipher_request *areq)
+{
+	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
+	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
+
+	if (areq->info == NULL) {
+		dev_err(ss->dev, "Empty IV\n");
+		return -EINVAL;
+	}
+
+	op->mode |= SS_ENCRYPTION;
+	op->mode |= SS_OP_AES;
+	op->mode |= SS_CBC;
+
+	return sunxi_aes_poll(areq);
+}
+
+static int sunxi_aes_cbc_decrypt(struct ablkcipher_request *areq)
+{
+	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
+	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
+
+	if (areq->info == NULL) {
+		dev_err(ss->dev, "Empty IV\n");
+		return -EINVAL;
+	}
+
+	op->mode |= SS_DECRYPTION;
+	op->mode |= SS_OP_AES;
+	op->mode |= SS_CBC;
+
+	return sunxi_aes_poll(areq);
+}
+
+/* check and set the AES key, prepare the mode to be used */
+static int sunxi_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
+		unsigned int keylen)
+{
+	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
+	switch (keylen) {
+	case 128 / 8:
+		op->mode = SS_AES_128BITS;
+		break;
+	case 192 / 8:
+		op->mode = SS_AES_192BITS;
+		break;
+	case 256 / 8:
+		op->mode = SS_AES_256BITS;
+		break;
+	default:
+		dev_err(ss->dev, "Invalid keylen %u\n", keylen);
+		crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
+		return -EINVAL;
+	}
+	op->keylen = keylen;
+	memcpy(op->key, key, keylen);
+	return 0;
+}
+
+static struct crypto_alg sunxi_aes_alg = {
+	.cra_name = "cbc(aes)",
+	.cra_driver_name = "cbc-aes-sunxi-ss",
+	.cra_priority = 300,
+	.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+	.cra_blocksize   = AES_BLOCK_SIZE,
+	.cra_ctxsize = sizeof(struct sunxi_req_ctx),
+	.cra_module = THIS_MODULE,
+	.cra_alignmask = 3,
+	.cra_type = &crypto_ablkcipher_type,
+	.cra_init = sunxi_cipher_init,
+	.cra_exit = sunxi_cipher_exit,
+	.cra_u = {
+		.ablkcipher = {
+			.min_keysize    = AES_MIN_KEY_SIZE,
+			.max_keysize    = AES_MAX_KEY_SIZE,
+			.ivsize         = AES_BLOCK_SIZE,
+			.setkey         = sunxi_aes_setkey,
+			.encrypt        = sunxi_aes_cbc_encrypt,
+			.decrypt        = sunxi_aes_cbc_decrypt,
+		}
+	}
+};
+
+int sunxi_ss_aes_init(void)
+{
+	int err = 0;
+	if (ss == NULL) {
+		pr_err("Cannot get Security System structure\n");
+		return -ENODEV;
+	}
+	err = crypto_register_alg(&sunxi_aes_alg);
+	if (err)
+		dev_err(ss->dev, "crypto_register_alg error for AES\n");
+	else
+		dev_dbg(ss->dev, "Registred AES\n");
+	return err;
+}
+
+static void __exit sunxi_ss_aes_exit(void)
+{
+	crypto_unregister_alg(&sunxi_aes_alg);
+}
+
+module_init(sunxi_ss_aes_init);
+module_exit(sunxi_ss_aes_exit);
+
+MODULE_DESCRIPTION("Allwinner Security System crypto accelerator AES module");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
+MODULE_ALIAS("aes");
diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-cipher-des.c b/drivers/crypto/sunxi-ss/sunxi-ss-cipher-des.c
new file mode 100644
index 0000000..be4cd4b
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sunxi-ss-cipher-des.c
@@ -0,0 +1,118 @@
+/*
+ * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
+ *
+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * Support AES cipher with 128,192,256 bits keysize.
+ * Support MD5 and SHA1 hash algorithms.
+ * Support DES and 3DES
+ * Support PRNG
+ *
+ * You could find the datasheet at
+ * http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation version 2 of the License
+ */
+#include "sunxi-ss-cipher.h"
+
+/* check and set the DES key, prepare the mode to be used */
+static int sunxi_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
+		unsigned int keylen)
+{
+	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
+	if (keylen != DES_KEY_SIZE) {
+		dev_err(ss->dev, "Invalid keylen %u\n", keylen);
+		crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
+		return -EINVAL;
+	}
+	op->keylen = keylen;
+	memcpy(op->key, key, keylen);
+	return 0;
+}
+
+static int sunxi_des_cbc_encrypt(struct ablkcipher_request *areq)
+{
+	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
+	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
+
+	if (areq->info == NULL) {
+		dev_info(ss->dev, "Empty IV\n");
+		return -EINVAL;
+	}
+
+	op->mode |= SS_ENCRYPTION;
+	op->mode |= SS_OP_DES;
+	op->mode |= SS_CBC;
+
+	return sunxi_des_poll(areq);
+}
+
+static int sunxi_des_cbc_decrypt(struct ablkcipher_request *areq)
+{
+	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
+	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
+
+	if (areq->info == NULL) {
+		dev_info(ss->dev, "Empty IV\n");
+		return -EINVAL;
+	}
+
+	op->mode |= SS_DECRYPTION;
+	op->mode |= SS_OP_DES;
+	op->mode |= SS_CBC;
+
+	return sunxi_des_poll(areq);
+}
+
+static struct crypto_alg sunxi_des_alg = {
+	.cra_name = "cbc(des)",
+	.cra_driver_name = "cbc-des-sunxi-ss",
+	.cra_priority = 300,
+	.cra_blocksize = DES_BLOCK_SIZE,
+	.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
+	.cra_ctxsize = sizeof(struct sunxi_req_ctx),
+	.cra_module = THIS_MODULE,
+	.cra_type = &crypto_ablkcipher_type,
+	.cra_init = sunxi_cipher_init,
+	.cra_exit = sunxi_cipher_exit,
+	.cra_alignmask = 3,
+	.cra_u.ablkcipher = {
+		.min_keysize    = DES_KEY_SIZE,
+		.max_keysize    = DES_KEY_SIZE,
+		.ivsize         = DES_BLOCK_SIZE,
+		.setkey         = sunxi_des_setkey,
+		.encrypt        = sunxi_des_cbc_encrypt,
+		.decrypt        = sunxi_des_cbc_decrypt,
+	}
+};
+
+static int sunxi_ss_des_init(void)
+{
+	int err = 0;
+	if (ss == NULL) {
+		pr_err("Cannot get Security System structure\n");
+		return -ENODEV;
+	}
+	err = crypto_register_alg(&sunxi_des_alg);
+	if (err)
+		dev_err(ss->dev, "crypto_register_alg error for DES\n");
+	else
+		dev_dbg(ss->dev, "Registred DES\n");
+	return err;
+}
+
+static void __exit sunxi_ss_des_exit(void)
+{
+	crypto_unregister_alg(&sunxi_des_alg);
+}
+
+module_init(sunxi_ss_des_init);
+module_exit(sunxi_ss_des_exit);
+
+MODULE_DESCRIPTION("Allwinner Security System crypto accelerator DES module");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
+MODULE_ALIAS("des");
diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c
new file mode 100644
index 0000000..a27de49
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c
@@ -0,0 +1,368 @@
+/*
+ * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
+ *
+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * Support AES cipher with 128,192,256 bits keysize.
+ * Support MD5 and SHA1 hash algorithms.
+ * Support DES and 3DES
+ * Support PRNG
+ *
+ * You could find the datasheet at
+ * http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation version 2 of the License
+ */
+#include "sunxi-ss-cipher.h"
+
+int sunxi_cipher_init(struct crypto_tfm *tfm)
+{
+	struct sunxi_req_ctx *op = crypto_tfm_ctx(tfm);
+	memset(op, 0, sizeof(struct sunxi_req_ctx));
+	return 0;
+}
+EXPORT_SYMBOL_GPL(sunxi_cipher_init);
+
+void sunxi_cipher_exit(struct crypto_tfm *tfm)
+{
+}
+EXPORT_SYMBOL_GPL(sunxi_cipher_exit);
+
+int sunxi_aes_poll(struct ablkcipher_request *areq)
+{
+	u32 tmp;
+	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
+	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
+	unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
+	/* when activating SS, the default FIFO space is 32 */
+	u32 rx_cnt = 32;
+	u32 tx_cnt = 0;
+	u32 v;
+	int i;
+	struct scatterlist *in_sg;
+	struct scatterlist *out_sg;
+	void *src_addr;
+	void *dst_addr;
+	unsigned int ileft = areq->nbytes;
+	unsigned int oleft = areq->nbytes;
+	unsigned int sgileft = areq->src->length;
+	unsigned int sgoleft = areq->dst->length;
+	unsigned int todo;
+	u32 *src32;
+	u32 *dst32;
+
+	tmp = op->mode;
+	tmp |= SS_ENABLED;
+
+	in_sg = areq->src;
+	out_sg = areq->dst;
+	if (areq->src == NULL || areq->dst == NULL) {
+		dev_err(ss->dev, "ERROR: Some SGs are NULL %u\n", areq->nbytes);
+		return -1;
+	}
+	mutex_lock(&ss->lock);
+	if (areq->info != NULL) {
+		for (i = 0; i < op->keylen; i += 4) {
+			v = *(u32 *)(op->key + i);
+			writel(v, ss->base + SS_KEY0 + i);
+		}
+		for (i = 0; i < 4 && i < ivsize / 4; i++) {
+			v = *(u32 *)(areq->info + i * 4);
+			writel(v, ss->base + SS_IV0 + i * 4);
+		}
+	}
+	writel(tmp, ss->base + SS_CTL);
+
+	/* If we have only one SG, we can use kmap_atomic */
+	if (sg_next(in_sg) == NULL && sg_next(out_sg) == NULL) {
+		src_addr = kmap_atomic(sg_page(in_sg)) + in_sg->offset;
+		if (src_addr == NULL) {
+			dev_err(ss->dev, "kmap_atomic error for src SG\n");
+			writel(0, ss->base + SS_CTL);
+			mutex_unlock(&ss->lock);
+			return -1;
+		}
+		dst_addr = kmap_atomic(sg_page(out_sg)) + out_sg->offset;
+		if (dst_addr == NULL) {
+			dev_err(ss->dev, "kmap_atomic error for dst SG\n");
+			writel(0, ss->base + SS_CTL);
+			mutex_unlock(&ss->lock);
+			kunmap_atomic(src_addr);
+			return -1;
+		}
+		src32 = (u32 *)src_addr;
+		dst32 = (u32 *)dst_addr;
+		ileft = areq->nbytes / 4;
+		oleft = areq->nbytes / 4;
+		do {
+			if (ileft > 0 && rx_cnt > 0) {
+				todo = min(rx_cnt, ileft);
+				ileft -= todo;
+				do {
+					writel_relaxed(*src32++,
+						       ss->base +
+						       SS_RXFIFO);
+					todo--;
+				} while (todo > 0);
+			}
+			if (tx_cnt > 0) {
+				todo = min(tx_cnt, oleft);
+				oleft -= todo;
+				do {
+					*dst32++ = readl_relaxed(ss->base +
+								SS_TXFIFO);
+					todo--;
+				} while (todo > 0);
+			}
+			tmp = readl_relaxed(ss->base + SS_FCSR);
+			rx_cnt = SS_RXFIFO_SPACES(tmp);
+			tx_cnt = SS_TXFIFO_SPACES(tmp);
+		} while (oleft > 0);
+		writel(0, ss->base + SS_CTL);
+		mutex_unlock(&ss->lock);
+		kunmap_atomic(src_addr);
+		kunmap_atomic(dst_addr);
+		return 0;
+	}
+
+	/* If we have more than one SG, we cannot use kmap_atomic since
+	 * we hold the mapping too long*/
+	src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
+	if (src_addr == NULL) {
+		dev_err(ss->dev, "KMAP error for src SG\n");
+		return -1;
+	}
+	dst_addr = kmap(sg_page(out_sg)) + out_sg->offset;
+	if (dst_addr == NULL) {
+		kunmap(sg_page(in_sg));
+		dev_err(ss->dev, "KMAP error for dst SG\n");
+		return -1;
+	}
+	src32 = (u32 *)src_addr;
+	dst32 = (u32 *)dst_addr;
+	ileft = areq->nbytes / 4;
+	oleft = areq->nbytes / 4;
+	sgileft = in_sg->length / 4;
+	sgoleft = out_sg->length / 4;
+	do {
+		tmp = readl_relaxed(ss->base + SS_FCSR);
+		rx_cnt = SS_RXFIFO_SPACES(tmp);
+		tx_cnt = SS_TXFIFO_SPACES(tmp);
+		todo = min3(rx_cnt, ileft, sgileft);
+		if (todo > 0) {
+			ileft -= todo;
+			sgileft -= todo;
+		}
+		while (todo > 0) {
+			writel_relaxed(*src32++, ss->base + SS_RXFIFO);
+			todo--;
+		}
+		if (in_sg != NULL && sgileft == 0 && ileft > 0) {
+			kunmap(sg_page(in_sg));
+			in_sg = sg_next(in_sg);
+			if (in_sg != NULL && in_sg->length == 0)
+				in_sg = sg_next(in_sg);
+			if (in_sg != NULL && in_sg->length == 0)
+				in_sg = sg_next(in_sg);
+			if (in_sg != NULL && ileft > 0) {
+				src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
+				if (src_addr == NULL) {
+					dev_err(ss->dev, "KMAP error for src SG\n");
+					return -1;
+				}
+				src32 = src_addr;
+				sgileft = in_sg->length / 4;
+			}
+		}
+		/* do not test oleft since when oleft == 0 we have finished */
+		todo = min3(tx_cnt, oleft, sgoleft);
+		if (todo > 0) {
+			oleft -= todo;
+			sgoleft -= todo;
+		}
+		while (todo > 0) {
+			*dst32++ = readl_relaxed(ss->base + SS_TXFIFO);
+			todo--;
+		}
+		if (out_sg != NULL && sgoleft == 0 && oleft >= 0) {
+			kunmap(sg_page(out_sg));
+			out_sg = sg_next(out_sg);
+			if (out_sg != NULL && out_sg->length == 0)
+				out_sg = sg_next(out_sg);
+			if (out_sg != NULL && oleft > 0) {
+				dst_addr = kmap(sg_page(out_sg)) +
+					out_sg->offset;
+				if (dst_addr == NULL) {
+					dev_err(ss->dev, "KMAP error\n");
+					return -1;
+				}
+				dst32 = dst_addr;
+				sgoleft = out_sg->length / 4;
+			}
+		}
+	} while (oleft > 0);
+
+	writel(0, ss->base + SS_CTL);
+	mutex_unlock(&ss->lock);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(sunxi_aes_poll);
+
+/* Pure CPU way of doing DES/3DES with SS
+ * Since DES and 3DES SGs could be smaller than 4 bytes, I use sg_copy_to_buffer
+ * for "linearize" them.
+ * The problem with that is that I alloc (2 x areq->nbytes) for buf_in/buf_out
+ * TODO: change this system
+ * SGsrc -> buf_in -> SS -> buf_out -> SGdst */
+int sunxi_des_poll(struct ablkcipher_request *areq)
+{
+	u32 tmp, value;
+	size_t nb_in_sg_tx, nb_in_sg_rx;
+	size_t ir, it;
+	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
+	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
+	unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
+	u32 tx_cnt = 0;
+	u32 rx_cnt = 0;
+	u32 v;
+	int i;
+	int no_chunk = 1;
+
+	/* if we have only SGs with size multiple of 4,
+	 * we can use the SS AES function */
+	struct scatterlist *in_sg;
+	struct scatterlist *out_sg;
+	in_sg = areq->src;
+	out_sg = areq->dst;
+
+	while (in_sg != NULL && no_chunk == 1) {
+		if ((in_sg->length % 4) != 0)
+			no_chunk = 0;
+		in_sg = sg_next(in_sg);
+	}
+	while (out_sg != NULL && no_chunk == 1) {
+		if ((out_sg->length % 4) != 0)
+			no_chunk = 0;
+		out_sg = sg_next(out_sg);
+	}
+
+	if (no_chunk == 1)
+		return sunxi_aes_poll(areq);
+	in_sg = areq->src;
+	out_sg = areq->dst;
+
+	tmp = op->mode;
+	tmp |= SS_ENABLED;
+
+	nb_in_sg_rx = sg_nents(in_sg);
+	nb_in_sg_tx = sg_nents(out_sg);
+
+	mutex_lock(&ss->bufin_lock);
+	if (ss->buf_in == NULL) {
+		ss->buf_in = kmalloc(areq->nbytes, GFP_KERNEL);
+		ss->buf_in_size = areq->nbytes;
+	} else {
+		if (areq->nbytes > ss->buf_in_size) {
+			kfree(ss->buf_in);
+			ss->buf_in = kmalloc(areq->nbytes, GFP_KERNEL);
+			ss->buf_in_size = areq->nbytes;
+		}
+	}
+	if (ss->buf_in == NULL) {
+		ss->buf_in_size = 0;
+		mutex_unlock(&ss->bufin_lock);
+		dev_err(ss->dev, "Unable to allocate pages.\n");
+		return -ENOMEM;
+	}
+	if (ss->buf_out == NULL) {
+		mutex_lock(&ss->bufout_lock);
+		ss->buf_out = kmalloc(areq->nbytes, GFP_KERNEL);
+		if (ss->buf_out == NULL) {
+			ss->buf_out_size = 0;
+			mutex_unlock(&ss->bufout_lock);
+			dev_err(ss->dev, "Unable to allocate pages.\n");
+			return -ENOMEM;
+		}
+		ss->buf_out_size = areq->nbytes;
+		mutex_unlock(&ss->bufout_lock);
+	} else {
+		if (areq->nbytes > ss->buf_out_size) {
+			mutex_lock(&ss->bufout_lock);
+			kfree(ss->buf_out);
+			ss->buf_out = kmalloc(areq->nbytes, GFP_KERNEL);
+			if (ss->buf_out == NULL) {
+				ss->buf_out_size = 0;
+				mutex_unlock(&ss->bufout_lock);
+				dev_err(ss->dev, "Unable to allocate pages.\n");
+				return -ENOMEM;
+			}
+			ss->buf_out_size = areq->nbytes;
+			mutex_unlock(&ss->bufout_lock);
+		}
+	}
+
+	sg_copy_to_buffer(areq->src, nb_in_sg_rx, ss->buf_in, areq->nbytes);
+
+	ir = 0;
+	it = 0;
+	mutex_lock(&ss->lock);
+	if (areq->info != NULL) {
+		for (i = 0; i < op->keylen; i += 4) {
+			v = *(u32 *)(op->key + i);
+			writel(v, ss->base + SS_KEY0 + i);
+		}
+		for (i = 0; i < 4 && i < ivsize / 4; i++) {
+			v = *(u32 *)(areq->info + i * 4);
+			writel(v, ss->base + SS_IV0 + i * 4);
+		}
+	}
+	writel(tmp, ss->base + SS_CTL);
+
+	do {
+		if (rx_cnt == 0 || tx_cnt == 0) {
+			tmp = readl(ss->base + SS_FCSR);
+			rx_cnt = SS_RXFIFO_SPACES(tmp);
+			tx_cnt = SS_TXFIFO_SPACES(tmp);
+		}
+		if (rx_cnt > 0 && ir < areq->nbytes) {
+			do {
+				value = *(u32 *)(ss->buf_in + ir);
+				writel(value, ss->base + SS_RXFIFO);
+				ir += 4;
+				rx_cnt--;
+			} while (rx_cnt > 0 && ir < areq->nbytes);
+		}
+		if (tx_cnt > 0 && it < areq->nbytes) {
+			do {
+				if (ir <= it)
+					dev_warn(ss->dev, "ANORMAL %u %u\n",
+							ir, it);
+				value = readl(ss->base + SS_TXFIFO);
+				*(u32 *)(ss->buf_out + it) = value;
+				it += 4;
+				tx_cnt--;
+			} while (tx_cnt > 0 && it < areq->nbytes);
+		}
+		if (ir == areq->nbytes) {
+			mutex_unlock(&ss->bufin_lock);
+			ir++;
+		}
+	} while (it < areq->nbytes);
+
+	writel(0, ss->base + SS_CTL);
+	mutex_unlock(&ss->lock);
+
+	/* a simple optimization, since we dont need the hardware for this copy
+	 * we release the lock and do the copy. With that we gain 5/10% perf */
+	mutex_lock(&ss->bufout_lock);
+	sg_copy_from_buffer(areq->dst, nb_in_sg_tx, ss->buf_out, areq->nbytes);
+
+	mutex_unlock(&ss->bufout_lock);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(sunxi_des_poll);
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-cipher.h b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.h
new file mode 100644
index 0000000..ecfbf9c
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.h
@@ -0,0 +1,8 @@
+#include "sunxi-ss.h"
+
+extern struct sunxi_ss_ctx *ss;
+
+int sunxi_aes_poll(struct ablkcipher_request *areq);
+int sunxi_des_poll(struct ablkcipher_request *areq);
+int sunxi_cipher_init(struct crypto_tfm *tfm);
+void sunxi_cipher_exit(struct crypto_tfm *tfm);
diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-hash-md5.c b/drivers/crypto/sunxi-ss/sunxi-ss-hash-md5.c
new file mode 100644
index 0000000..1cadd44
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sunxi-ss-hash-md5.c
@@ -0,0 +1,69 @@
+/*
+ * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
+ *
+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * Support AES cipher with 128,192,256 bits keysize.
+ * Support MD5 and SHA1 hash algorithms.
+ * Support DES and 3DES
+ * Support PRNG
+ *
+ * You could find the datasheet at
+ * http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation version 2 of the License
+ */
+#include "sunxi-ss-hash.h"
+
+static struct ahash_alg sunxi_md5_alg = {
+	.init = sunxi_hash_init,
+	.update = sunxi_hash_update,
+	.final = sunxi_hash_final,
+	.finup = sunxi_hash_finup,
+	.digest = sunxi_hash_digest,
+	.halg = {
+		.digestsize = MD5_DIGEST_SIZE,
+		.base = {
+			.cra_name = "md5",
+			.cra_driver_name = "md5-sunxi-ss",
+			.cra_priority = 300,
+			.cra_alignmask = 3,
+			.cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+			.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
+			.cra_ctxsize = sizeof(struct sunxi_req_ctx),
+			.cra_module = THIS_MODULE,
+			.cra_type = &crypto_ahash_type
+		}
+	}
+};
+
+static int sunxi_ss_md5_init(void)
+{
+	int err = 0;
+	if (ss == NULL) {
+		pr_err("Cannot get Security System structure\n");
+		return -ENODEV;
+	}
+	err = crypto_register_ahash(&sunxi_md5_alg);
+	if (err)
+		dev_err(ss->dev, "crypto_register_alg error for MD5\n");
+	else
+		dev_dbg(ss->dev, "Registred MD5\n");
+	return err;
+}
+
+static void __exit sunxi_ss_md5_exit(void)
+{
+	crypto_unregister_ahash(&sunxi_md5_alg);
+}
+
+module_init(sunxi_ss_md5_init);
+module_exit(sunxi_ss_md5_exit);
+
+MODULE_DESCRIPTION("Allwinner Security System crypto accelerator MD5 module");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
+MODULE_ALIAS("md5");
diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-hash-sha1.c b/drivers/crypto/sunxi-ss/sunxi-ss-hash-sha1.c
new file mode 100644
index 0000000..c509436
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sunxi-ss-hash-sha1.c
@@ -0,0 +1,69 @@
+/*
+ * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
+ *
+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * Support AES cipher with 128,192,256 bits keysize.
+ * Support MD5 and SHA1 hash algorithms.
+ * Support DES and 3DES
+ * Support PRNG
+ *
+ * You could find the datasheet at
+ * http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation version 2 of the License
+ */
+#include "sunxi-ss-hash.h"
+
+static struct ahash_alg sunxi_sha1_alg = {
+	.init = sunxi_hash_init,
+	.update = sunxi_hash_update,
+	.final = sunxi_hash_final,
+	.finup = sunxi_hash_finup,
+	.digest = sunxi_hash_digest,
+	.halg = {
+		.digestsize = SHA1_DIGEST_SIZE,
+		.base = {
+			.cra_name = "sha1",
+			.cra_driver_name = "sha1-sunxi-ss",
+			.cra_priority = 300,
+			.cra_alignmask = 3,
+			.cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+			.cra_blocksize = SHA1_BLOCK_SIZE,
+			.cra_ctxsize = sizeof(struct sunxi_req_ctx),
+			.cra_module = THIS_MODULE,
+			.cra_type = &crypto_ahash_type
+		}
+	}
+};
+
+static int sunxi_ss_sha1_init(void)
+{
+	int err = 0;
+	if (ss == NULL) {
+		pr_err("Cannot get Security System structure\n");
+		return -ENODEV;
+	}
+	err = crypto_register_ahash(&sunxi_sha1_alg);
+	if (err)
+		dev_err(ss->dev, "crypto_register_alg error for SHA1\n");
+	else
+		dev_dbg(ss->dev, "Registred SHA1\n");
+	return err;
+}
+
+static void __exit sunxi_ss_sha1_exit(void)
+{
+	crypto_unregister_ahash(&sunxi_sha1_alg);
+}
+
+module_init(sunxi_ss_sha1_init);
+module_exit(sunxi_ss_sha1_exit);
+
+MODULE_DESCRIPTION("Allwinner Security System crypto accelerator SHA1 module");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
+MODULE_ALIAS("sha1");
diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-hash.c b/drivers/crypto/sunxi-ss/sunxi-ss-hash.c
new file mode 100644
index 0000000..c566e03
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sunxi-ss-hash.c
@@ -0,0 +1,234 @@
+#include "sunxi-ss-hash.h"
+
+/* sunxi_hash_init: initialize request context
+ * Activate the SS, and configure it for MD5 or SHA1
+ */
+int sunxi_hash_init(struct ahash_request *areq)
+{
+	const char *hash_type;
+	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+	struct sunxi_req_ctx *op = crypto_ahash_ctx(tfm);
+	u32 tmp = SS_ENABLED;
+
+	mutex_lock(&ss->lock);
+
+	hash_type = crypto_tfm_alg_name(areq->base.tfm);
+
+	op->byte_count = 0;
+	op->nbwait = 0;
+	op->waitbuf = 0;
+
+	/* Enable and configure SS for MD5 or SHA1 */
+	if (strcmp(hash_type, "sha1") == 0) {
+		tmp |= SS_OP_SHA1;
+		op->mode = SS_OP_SHA1;
+	} else {
+		tmp |= SS_OP_MD5;
+		op->mode = SS_OP_MD5;
+	}
+
+	writel(tmp, ss->base + SS_CTL);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(sunxi_hash_init);
+
+/*
+ * sunxi_hash_update: update hash engine
+ *
+ * Could be used for both SHA1 and MD5
+ * Write data by step of 32bits and put then in the SS.
+ * The remaining data is stored (nbwait bytes) in op->waitbuf
+ * As an optimisation, we do not check RXFIFO_SPACES, since SS handle
+ * the FIFO faster than our writes
+ */
+int sunxi_hash_update(struct ahash_request *areq)
+{
+	u32 v;
+	unsigned int i = 0;/* bytes read, to be compared to areq->nbytes */
+	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+	struct sunxi_req_ctx *op = crypto_ahash_ctx(tfm);
+	struct scatterlist *in_sg;
+	unsigned int in_i = 0;/* advancement in the current SG */
+	void *src_addr;
+
+	u8 *waitbuf = (u8 *)(&op->waitbuf);
+
+	if (areq->nbytes == 0)
+		return 0;
+
+	in_sg = areq->src;
+	do {
+		src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
+		/* step 1, if some bytes remains from last SG,
+		 * try to complete them to 4 and sent its */
+		if (op->nbwait > 0) {
+			while (op->nbwait < 4 && i < areq->nbytes &&
+					in_i < in_sg->length) {
+				waitbuf[op->nbwait] = *(u8 *)(src_addr + in_i);
+				i++;
+				in_i++;
+				op->nbwait++;
+			}
+			if (op->nbwait == 4) {
+				writel(op->waitbuf, ss->base + SS_RXFIFO);
+				op->byte_count += 4;
+				op->nbwait = 0;
+				op->waitbuf = 0;
+			}
+		}
+		/* step 2, main loop, read data 4bytes at a time */
+		while (i < areq->nbytes && areq->nbytes - i >= 4 &&
+				in_i < in_sg->length &&
+				in_sg->length - in_i >= 4) {
+			v = *(u32 *)(src_addr + in_i);
+			writel_relaxed(v, ss->base + SS_RXFIFO);
+			i += 4;
+			op->byte_count += 4;
+			in_i += 4;
+		}
+		/* step 3, if we have less than 4 bytes, copy them in waitbuf
+		 * no need to check for op->nbwait < 4 since we cannot have
+		 * more than 4 bytes remaining */
+		if (in_i < in_sg->length && in_sg->length - in_i < 4 &&
+				i < areq->nbytes) {
+			do {
+				waitbuf[op->nbwait] = *(u8 *)(src_addr + in_i);
+				op->nbwait++;
+				in_i++;
+				i++;
+			} while (in_i < in_sg->length && i < areq->nbytes);
+		}
+		/* we have finished the current SG, try next one */
+		kunmap(sg_page(in_sg));
+		in_sg = sg_next(in_sg);
+		in_i = 0;
+	} while (in_sg != NULL && i < areq->nbytes);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(sunxi_hash_update);
+
+/*
+ * sunxi_hash_final: finalize hashing operation
+ *
+ * If we have some remaining bytes, send it.
+ * Then ask the SS for finalizing the hash
+ */
+int sunxi_hash_final(struct ahash_request *areq)
+{
+	u32 v;
+	unsigned int i;
+	int zeros;
+	unsigned int index, padlen;
+	__be64 bits;
+	struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+	struct sunxi_req_ctx *op = crypto_ahash_ctx(tfm);
+
+	if (op->nbwait > 0) {
+		op->waitbuf |= ((1 << 7) << (op->nbwait * 8));
+		writel(op->waitbuf, ss->base + SS_RXFIFO);
+	} else {
+		writel((1 << 7), ss->base + SS_RXFIFO);
+	}
+
+	/* number of space to pad to obtain 64o minus 8(size) minus 4 (final 1)
+	 * example len=0
+	 * example len=56
+	 * */
+
+	/* we have already send 4 more byte of which nbwait data */
+	if (op->mode == SS_OP_MD5) {
+		index = (op->byte_count + 4) & 0x3f;
+		op->byte_count += op->nbwait;
+		if (index > 56)
+			zeros = (120 - index) / 4;
+		else
+			zeros = (56 - index) / 4;
+	} else {
+		op->byte_count += op->nbwait;
+		index = op->byte_count & 0x3f;
+		padlen = (index < 56) ? (56 - index) : ((64+56) - index);
+		zeros = (padlen - 1) / 4;
+	}
+	for (i = 0; i < zeros; i++)
+		writel(0, ss->base + SS_RXFIFO);
+
+	/* write the lenght */
+	if (op->mode == SS_OP_SHA1) {
+		bits = cpu_to_be64(op->byte_count << 3);
+		writel(bits & 0xffffffff, ss->base + SS_RXFIFO);
+		writel((bits >> 32) & 0xffffffff, ss->base + SS_RXFIFO);
+	} else {
+		writel((op->byte_count << 3) & 0xffffffff,
+				ss->base + SS_RXFIFO);
+		writel((op->byte_count >> 29) & 0xffffffff,
+				ss->base + SS_RXFIFO);
+	}
+
+	/* stop the hashing */
+	v = readl(ss->base + SS_CTL);
+	v |= SS_DATA_END;
+	writel(v, ss->base + SS_CTL);
+
+	/* check the end */
+	/* The timeout could happend only in case of bad overcloking */
+#define SS_TIMEOUT 100
+	i = 0;
+	do {
+		v = readl(ss->base + SS_CTL);
+		i++;
+	} while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
+	if (i >= SS_TIMEOUT) {
+		dev_err(ss->dev, "ERROR: hash end timeout %d>%d\n",
+				i, SS_TIMEOUT);
+		writel(0, ss->base + SS_CTL);
+		mutex_unlock(&ss->lock);
+		return -1;
+	}
+
+	if (op->mode == SS_OP_SHA1) {
+		for (i = 0; i < 5; i++) {
+			v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4));
+			memcpy(areq->result + i * 4, &v, 4);
+		}
+	} else {
+		for (i = 0; i < 4; i++) {
+			v = readl(ss->base + SS_MD0 + i * 4);
+			memcpy(areq->result + i * 4, &v, 4);
+		}
+	}
+	writel(0, ss->base + SS_CTL);
+	mutex_unlock(&ss->lock);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(sunxi_hash_final);
+
+/* sunxi_hash_finup: finalize hashing operation after an update */
+int sunxi_hash_finup(struct ahash_request *areq)
+{
+	int err;
+
+	err = sunxi_hash_update(areq);
+	if (err != 0)
+		return err;
+
+	return sunxi_hash_final(areq);
+}
+EXPORT_SYMBOL_GPL(sunxi_hash_finup);
+
+/* combo of init/update/final functions */
+int sunxi_hash_digest(struct ahash_request *areq)
+{
+	int err;
+
+	err = sunxi_hash_init(areq);
+	if (err != 0)
+		return err;
+
+	err = sunxi_hash_update(areq);
+	if (err != 0)
+		return err;
+
+	return sunxi_hash_final(areq);
+}
+EXPORT_SYMBOL_GPL(sunxi_hash_digest);
+MODULE_LICENSE("GPL");
diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-hash.h b/drivers/crypto/sunxi-ss/sunxi-ss-hash.h
new file mode 100644
index 0000000..7fae093
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sunxi-ss-hash.h
@@ -0,0 +1,9 @@
+#include "sunxi-ss.h"
+
+extern struct sunxi_ss_ctx *ss;
+
+int sunxi_hash_init(struct ahash_request *areq);
+int sunxi_hash_update(struct ahash_request *areq);
+int sunxi_hash_final(struct ahash_request *areq);
+int sunxi_hash_finup(struct ahash_request *areq);
+int sunxi_hash_digest(struct ahash_request *areq);
diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-rng.c b/drivers/crypto/sunxi-ss/sunxi-ss-rng.c
new file mode 100644
index 0000000..0af20ab
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sunxi-ss-rng.c
@@ -0,0 +1,115 @@
+#include "sunxi-ss.h"
+#include <crypto/internal/rng.h>
+
+#define SS_SEED_LEN (192/8)
+#define SS_DATA_LEN (160/8)
+
+struct prng_context {
+	u32 seed[SS_SEED_LEN/4];
+	unsigned int slen;
+};
+
+extern struct sunxi_ss_ctx *ss;
+
+static int sunxi_ss_rng_get_random(struct crypto_rng *tfm, u8 *rdata,
+		unsigned int dlen)
+{
+	struct prng_context *ctx = crypto_rng_ctx(tfm);
+	int i;
+	u32 mode = 0;
+	u32 v;
+
+	if (rdata == NULL)
+		return -EINVAL;
+
+	mode |= SS_OP_PRNG | SS_PRNG_ONESHOT | SS_ENABLED;
+
+	mutex_lock(&ss->lock);
+	writel(mode, ss->base + SS_CTL);
+
+	for (i = 0; i < ctx->slen && i < SS_SEED_LEN; i += 4) {
+		v = *(u32 *)(ctx->seed + i);
+		writel(v, ss->base + SS_KEY0 + i);
+	}
+
+	writel(mode | SS_PRNG_START, ss->base + SS_CTL);
+	i = 0;
+	do {
+		v = readl(ss->base + SS_CTL);
+		i++;
+	} while (v != mode && i < 10);
+	for (i = 0; i < dlen && i < SS_DATA_LEN; i += 4) {
+		v = readl(ss->base + SS_MD0 + i);
+		*(u32 *)(rdata + i) = v;
+	}
+
+	writel(0, ss->base + SS_CTL);
+	mutex_unlock(&ss->lock);
+	return dlen;
+}
+
+static int sunxi_ss_rng_reset(struct crypto_rng *tfm, u8 *seed,
+		unsigned int slen)
+{
+	struct prng_context *ctx = crypto_rng_ctx(tfm);
+	unsigned int i;
+
+	if (slen == 0) {
+		ctx->slen = 0;
+		return 0;
+	}
+	if (slen > SS_SEED_LEN) {
+		dev_err(ss->dev, "Requested seedlen %u exceed %u\n",
+				slen, SS_SEED_LEN);
+		return -EINVAL;
+	}
+	for (i = 0; i < SS_SEED_LEN && i < slen; i++)
+		ctx->seed[i] = seed[i];
+	ctx->slen = slen;
+	return 0;
+}
+
+static struct crypto_alg sunxi_ss_prng = {
+	.cra_name = "stdrng",
+	.cra_driver_name = "rng-sunxi-ss",
+	.cra_priority = 300,
+	.cra_flags = CRYPTO_ALG_TYPE_RNG,
+	.cra_ctxsize = sizeof(struct prng_context),
+	.cra_module = THIS_MODULE,
+	.cra_type = &crypto_rng_type,
+	.cra_u.rng = {
+		.rng_make_random = sunxi_ss_rng_get_random,
+		.rng_reset = sunxi_ss_rng_reset,
+		.seedsize = SS_SEED_LEN
+	}
+};
+
+
+static int sunxi_ss_rng_init(void)
+{
+	int err = 0;
+	if (ss == NULL) {
+		pr_err("Cannot get SUNXI SS\n");
+		return 0;
+	}
+
+	err = crypto_register_alg(&sunxi_ss_prng);
+	if (err)
+		dev_err(ss->dev, "crypto_register_alg error\n");
+	else
+		dev_info(ss->dev, "Registred PRNG\n");
+	return err;
+}
+
+static void __exit sunxi_ss_rng_exit(void)
+{
+	crypto_unregister_alg(&sunxi_ss_prng);
+}
+
+
+module_init(sunxi_ss_rng_init);
+module_exit(sunxi_ss_rng_exit);
+
+MODULE_DESCRIPTION("Allwinner Security System crypto accelerator RNG module");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
diff --git a/drivers/crypto/sunxi-ss/sunxi-ss.c b/drivers/crypto/sunxi-ss/sunxi-ss.c
new file mode 100644
index 0000000..9287af2
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sunxi-ss.c
@@ -0,0 +1,190 @@
+/*
+ * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
+ *
+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * Support AES cipher with 128,192,256 bits keysize.
+ * Support MD5 and SHA1 hash algorithms.
+ * Support DES and 3DES
+ * Support PRNG
+ *
+ * You could find the datasheet at
+ * http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation version 2 of the License
+ */
+#include "sunxi-ss.h"
+
+#include <linux/clk.h>
+#include <linux/crypto.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <crypto/scatterwalk.h>
+#include <linux/scatterlist.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+
+/* General notes:
+ * I cannot use a key/IV cache because each time one of these change ALL stuff
+ * need to be re-writed (rewrite SS_KEYX ans SS_IVX).
+ * And for example, with dm-crypt IV changes on each request.
+ *
+ * After each request the device must be disabled with a write of 0 in SS_CTL
+ *
+ * For performance reason, we use writel_relaxed/read_relaxed for all
+ * operations on RX and TX FIFO and also SS_FCSR.
+ * For all other registers, we use writel/readl.
+ * See http://permalink.gmane.org/gmane.linux.ports.arm.kernel/117644
+ * and http://permalink.gmane.org/gmane.linux.ports.arm.kernel/117640
+ * */
+
+static int ss_is_init;
+struct sunxi_ss_ctx *ss;
+EXPORT_SYMBOL_GPL(ss);
+
+static int sunxi_ss_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	u32 v;
+	int err;
+	unsigned long cr;
+	const unsigned long cr_ahb = 24 * 1000 * 1000;
+	const unsigned long cr_mod = 150 * 1000 * 1000;
+
+	if (!pdev->dev.of_node)
+		return -ENODEV;
+
+	if (ss_is_init == 1) {
+		dev_err(&pdev->dev, "Device already initialized\n");
+		return -ENODEV;
+	}
+
+	ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
+	if (ss == NULL)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ss->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(ss->base)) {
+		dev_err(&pdev->dev, "Cannot request MMIO\n");
+		return PTR_ERR(ss->base);
+	}
+
+	ss->ssclk = devm_clk_get(&pdev->dev, "mod");
+	if (IS_ERR(ss->ssclk)) {
+		err = PTR_ERR(ss->ssclk);
+		dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
+		return err;
+	}
+	dev_dbg(&pdev->dev, "clock ss acquired\n");
+
+	ss->busclk = devm_clk_get(&pdev->dev, "ahb");
+	if (IS_ERR(ss->busclk)) {
+		err = PTR_ERR(ss->busclk);
+		dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
+		return err;
+	}
+	dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
+
+	/* Enable the clocks */
+	err = clk_prepare_enable(ss->busclk);
+	if (err != 0) {
+		dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
+		return err;
+	}
+	err = clk_prepare_enable(ss->ssclk);
+	if (err != 0) {
+		dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n");
+		clk_disable_unprepare(ss->busclk);
+		return err;
+	}
+
+	/* Check that clock have the correct rates gived in the datasheet */
+	/* Try to set the clock to the maximum allowed */
+	err = clk_set_rate(ss->ssclk, cr_mod);
+	if (err != 0) {
+		dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
+		clk_disable_unprepare(ss->ssclk);
+		clk_disable_unprepare(ss->busclk);
+		return err;
+	}
+	cr = clk_get_rate(ss->busclk);
+	if (cr >= cr_ahb)
+		dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
+				cr, cr / 1000000, cr_ahb);
+	else
+		dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
+				cr, cr / 1000000, cr_ahb);
+	cr = clk_get_rate(ss->ssclk);
+	if (cr == cr_mod)
+		dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
+				cr, cr / 1000000, cr_mod);
+	else {
+		dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
+				cr, cr / 1000000, cr_mod);
+	}
+
+	/* TODO Does this information could be usefull ? */
+	writel(SS_ENABLED, ss->base + SS_CTL);
+	v = readl(ss->base + SS_CTL);
+	v >>= 16;
+	v &= 0x07;
+	dev_info(&pdev->dev, "Die ID %d\n", v);
+	writel(0, ss->base + SS_CTL);
+
+	ss->dev = &pdev->dev;
+
+	mutex_init(&ss->lock);
+	mutex_init(&ss->bufin_lock);
+	mutex_init(&ss->bufout_lock);
+	ss_is_init = 1;
+	return 0;
+}
+
+/* No need to check is some sub module is loaded,
+ * since they need the ss structure symbol */
+static int __exit sunxi_ss_remove(struct platform_device *pdev)
+{
+	if (!pdev->dev.of_node)
+		return 0;
+
+	if (ss->buf_in != NULL)
+		kfree(ss->buf_in);
+	if (ss->buf_out != NULL)
+		kfree(ss->buf_out);
+
+	writel(0, ss->base + SS_CTL);
+	clk_disable_unprepare(ss->busclk);
+	clk_disable_unprepare(ss->ssclk);
+	ss_is_init = 0;
+	return 0;
+}
+
+/*============================================================================*/
+/*============================================================================*/
+static const struct of_device_id a20ss_crypto_of_match_table[] = {
+	{ .compatible = "allwinner,sun7i-a20-crypto" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);
+
+static struct platform_driver sunxi_ss_driver = {
+	.probe          = sunxi_ss_probe,
+	.remove         = __exit_p(sunxi_ss_remove),
+	.driver         = {
+		.owner          = THIS_MODULE,
+		.name           = "sunxi-ss",
+		.of_match_table	= a20ss_crypto_of_match_table,
+	},
+};
+
+module_platform_driver(sunxi_ss_driver);
+
+MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
diff --git a/drivers/crypto/sunxi-ss/sunxi-ss.h b/drivers/crypto/sunxi-ss/sunxi-ss.h
new file mode 100644
index 0000000..cac6560
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sunxi-ss.h
@@ -0,0 +1,161 @@
+/*
+ * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
+ *
+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * Support AES cipher with 128,192,256 bits keysize.
+ * Support MD5 and SHA1 hash algorithms.
+ * Support DES and 3DES
+ * Support PRNG
+ *
+ * You could find the datasheet at
+ * http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation version 2 of the License
+ */
+
+#include <linux/clk.h>
+#include <linux/crypto.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <crypto/scatterwalk.h>
+#include <linux/scatterlist.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <crypto/md5.h>
+#include <crypto/sha.h>
+#include <crypto/hash.h>
+#include <crypto/internal/hash.h>
+#include <crypto/aes.h>
+#include <crypto/des.h>
+
+#define SS_CTL            0x00
+#define SS_KEY0           0x04
+#define SS_KEY1           0x08
+#define SS_KEY2           0x0C
+#define SS_KEY3           0x10
+#define SS_KEY4           0x14
+#define SS_KEY5           0x18
+#define SS_KEY6           0x1C
+#define SS_KEY7           0x20
+
+#define SS_IV0            0x24
+#define SS_IV1            0x28
+#define SS_IV2            0x2C
+#define SS_IV3            0x30
+
+#define SS_CNT0           0x34
+#define SS_CNT1           0x38
+#define SS_CNT2           0x3C
+#define SS_CNT3           0x40
+
+#define SS_FCSR           0x44
+#define SS_ICSR           0x48
+
+#define SS_MD0            0x4C
+#define SS_MD1            0x50
+#define SS_MD2            0x54
+#define SS_MD3            0x58
+#define SS_MD4            0x5C
+
+#define SS_RXFIFO         0x200
+#define SS_TXFIFO         0x204
+
+/* SS_CTL configuration values */
+
+/* PRNG generator mode - bit 15 */
+#define SS_PRNG_ONESHOT		(0 << 15)
+#define SS_PRNG_CONTINUE	(1 << 15)
+
+/* SS operation mode - bits 12-13 */
+#define SS_ECB			(0 << 12)
+#define SS_CBC			(1 << 12)
+#define SS_CNT			(2 << 12)
+
+/* Counter width for CNT mode - bits 10-11 */
+#define SS_CNT_16BITS		(0 << 10)
+#define SS_CNT_32BITS		(1 << 10)
+#define SS_CNT_64BITS		(2 << 10)
+
+/* Key size for AES - bits 8-9 */
+#define SS_AES_128BITS		(0 << 8)
+#define SS_AES_192BITS		(1 << 8)
+#define SS_AES_256BITS		(2 << 8)
+
+/* Operation direction - bit 7 */
+#define SS_ENCRYPTION		(0 << 7)
+#define SS_DECRYPTION		(1 << 7)
+
+/* SS Method - bits 4-6 */
+#define SS_OP_AES		(0 << 4)
+#define SS_OP_DES		(1 << 4)
+#define SS_OP_3DES		(2 << 4)
+#define SS_OP_SHA1		(3 << 4)
+#define SS_OP_MD5		(4 << 4)
+#define SS_OP_PRNG		(5 << 4)
+
+/* Data end bit - bit 2 */
+#define SS_DATA_END		(1 << 2)
+
+/* PRNG start bit - bit 1 */
+#define SS_PRNG_START		(1 << 1)
+
+/* SS Enable bit - bit 0 */
+#define SS_DISABLED		(0 << 0)
+#define SS_ENABLED		(1 << 0)
+
+/* SS_FCSR configuration values */
+/* RX FIFO status - bit 30 */
+#define SS_RXFIFO_FREE		(1 << 30)
+
+/* RX FIFO empty spaces - bits 24-29 */
+#define SS_RXFIFO_SPACES(val)	(((val) >> 24) & 0x3f)
+
+/* TX FIFO status - bit 22 */
+#define SS_TXFIFO_AVAILABLE	(1 << 22)
+
+/* TX FIFO available spaces - bits 16-21 */
+#define SS_TXFIFO_SPACES(val)	(((val) >> 16) & 0x3f)
+
+#define SS_RXFIFO_EMP_INT_PENDING	(1 << 10)
+#define SS_TXFIFO_AVA_INT_PENDING	(1 << 8)
+#define SS_RXFIFO_EMP_INT_ENABLE	(1 << 2)
+#define SS_TXFIFO_AVA_INT_ENABLE	(1 << 0)
+
+/* SS_ICSR configuration values */
+#define SS_ICS_DRQ_ENABLE		(1 << 4)
+
+struct sunxi_ss_ctx {
+	void __iomem *base;
+	int irq;
+	struct clk *busclk;
+	struct clk *ssclk;
+	struct device *dev;
+	struct resource *res;
+	void *buf_in; /* pointer to data to be uploaded to the device */
+	size_t buf_in_size; /* size of buf_in */
+	void *buf_out;
+	size_t buf_out_size;
+	struct mutex lock; /* control the use of the device */
+	struct mutex bufout_lock; /* control the use of buf_out*/
+	struct mutex bufin_lock; /* control the sue of buf_in*/
+};
+
+struct sunxi_req_ctx {
+	u8 key[AES_MAX_KEY_SIZE * 8];
+	u32 keylen;
+	u32 mode;
+	u64 byte_count; /* number of bytes "uploaded" to the device */
+	u32 waitbuf; /* a partial word waiting to be completed and
+			uploaded to the device */
+	/* number of bytes to be uploaded in the waitbuf word */
+	unsigned int nbwait;
+};
+
+int sunxi_ss_aes_init(void);
+
-- 
1.8.5.5

Re: [PATCH v3 1/4] crypto: Add Allwinner Security System crypto accelerator

[Marek Vasut]

On Tuesday, June 10, 2014 at 02:43:14 PM, LABBE Corentin wrote:
> Add support for the Security System included in Allwinner SoC A20.
> The Security System is a hardware cryptographic accelerator that support
> AES/MD5/SHA1/DES/3DES/PRNG algorithms.
> 
> Signed-off-by: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

[...]

> diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c
> b/drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c new file mode 100644
> index 0000000..fcdc8a4
> --- /dev/null
> +++ b/drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c
> @@ -0,0 +1,118 @@
> +/*
> + * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
> + *
> + * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * Support AES cipher with 128,192,256 bits keysize.
> + * Support MD5 and SHA1 hash algorithms.
> + * Support DES and 3DES
> + * Support PRNG
> + *
> + * You could find the datasheet at
> + * http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
> + *
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation version 2 of the License

The license text seems incomplete.
[...]

> +static int sunxi_des3_cbc_encrypt(struct ablkcipher_request *areq)
> +{
> +	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
> +	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
> +
> +	if (areq->info == NULL) {
> +		dev_info(ss->dev, "Empty IV\n");

dev_err() here.

> +		return -EINVAL;
> +	}
> +
> +	op->mode |= SS_ENCRYPTION;
> +	op->mode |= SS_OP_3DES;
> +	op->mode |= SS_CBC;

You can just op |= (foo | bar | baz) here .

> +	return sunxi_des_poll(areq);
> +}
> +
> +static int sunxi_des3_cbc_decrypt(struct ablkcipher_request *areq)
> +{
> +	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
> +	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
> +
> +	if (areq->info == NULL) {
> +		dev_info(ss->dev, "Empty IV\n");

DTTO.

> +		return -EINVAL;
> +	}
> +
> +	op->mode |= SS_DECRYPTION;
> +	op->mode |= SS_OP_3DES;
> +	op->mode |= SS_CBC;

DTTO.

[...]
> +static int sunxi_ss_3des_init(void)
> +{
> +	int err = 0;
> +	if (ss == NULL) {
> +		pr_err("Cannot get Security System structure\n");
> +		return -ENODEV;
> +	}
> +	err = crypto_register_alg(&sunxi_des3_alg);
> +	if (err)
> +		dev_err(ss->dev, "crypto_register_alg error for DES3\n");
> +	else
> +		dev_dbg(ss->dev, "Registred DES3\n");
> +	return err;
> +}
> +
> +static void __exit sunxi_ss_3des_exit(void)
> +{
> +	crypto_unregister_alg(&sunxi_des3_alg);
> +}
> +
> +module_init(sunxi_ss_3des_init);
> +module_exit(sunxi_ss_3des_exit);

I really dislike how you have multiple modules accessing the same hardware. That 
just seems broken.

[...]

> +static int sunxi_aes_cbc_encrypt(struct ablkcipher_request *areq)
> +{
> +	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
> +	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
> +
> +	if (areq->info == NULL) {
> +		dev_err(ss->dev, "Empty IV\n");
> +		return -EINVAL;
> +	}
> +
> +	op->mode |= SS_ENCRYPTION;
> +	op->mode |= SS_OP_AES;
> +	op->mode |= SS_CBC;

This looks just like the 3DES implementation. Please make this into a common 
code if possible. I think you'd just need to have some switch statement based on 
the type of cipher to fill op->mode, that's all.

> +	return sunxi_aes_poll(areq);
> +}

[...]

> +static int sunxi_des_cbc_encrypt(struct ablkcipher_request *areq)
> +{
> +	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
> +	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
> +
> +	if (areq->info == NULL) {
> +		dev_info(ss->dev, "Empty IV\n");
> +		return -EINVAL;
> +	}
> +
> +	op->mode |= SS_ENCRYPTION;
> +	op->mode |= SS_OP_DES;
> +	op->mode |= SS_CBC;

Looks similar to 3DES and AES again.

> +	return sunxi_des_poll(areq);
> +}

[...]

> diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c
> b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c new file mode 100644
> index 0000000..a27de49
[...]
> +int sunxi_cipher_init(struct crypto_tfm *tfm)
> +{
> +	struct sunxi_req_ctx *op = crypto_tfm_ctx(tfm);
> +	memset(op, 0, sizeof(struct sunxi_req_ctx));
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(sunxi_cipher_init);

This is wrong, you don't want to export this symbol.

> +void sunxi_cipher_exit(struct crypto_tfm *tfm)
> +{
> +}
> +EXPORT_SYMBOL_GPL(sunxi_cipher_exit);

Why do you even need an empty function ?

> +int sunxi_aes_poll(struct ablkcipher_request *areq)
> +{
> +	u32 tmp;
> +	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
> +	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
> +	unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
> +	/* when activating SS, the default FIFO space is 32 */
> +	u32 rx_cnt = 32;
> +	u32 tx_cnt = 0;
> +	u32 v;
> +	int i;
> +	struct scatterlist *in_sg;
> +	struct scatterlist *out_sg;
> +	void *src_addr;
> +	void *dst_addr;
> +	unsigned int ileft = areq->nbytes;
> +	unsigned int oleft = areq->nbytes;
> +	unsigned int sgileft = areq->src->length;
> +	unsigned int sgoleft = areq->dst->length;
> +	unsigned int todo;
> +	u32 *src32;
> +	u32 *dst32;
> +
> +	tmp = op->mode;
> +	tmp |= SS_ENABLED;

tmp is not a good name for a variable .

> +	in_sg = areq->src;
> +	out_sg = areq->dst;
> +	if (areq->src == NULL || areq->dst == NULL) {

You do a NULL pointer test here, yet you access areq->src->length in sgileft 
above . DTTO for areq->dst->length . That would crash much earlier than here.

> +		dev_err(ss->dev, "ERROR: Some SGs are NULL %u\n", areq->nbytes);
> +		return -1;
> +	}
> +	mutex_lock(&ss->lock);
> +	if (areq->info != NULL) {
> +		for (i = 0; i < op->keylen; i += 4) {
> +			v = *(u32 *)(op->key + i);

Consider that op->key would be magically unaligned ... then you'd trigger 
alignment fault here. Make the "op->key" an u32[] and drop those crap casts 
here.

> +			writel(v, ss->base + SS_KEY0 + i);
> +		}
> +		for (i = 0; i < 4 && i < ivsize / 4; i++) {
> +			v = *(u32 *)(areq->info + i * 4);
> +			writel(v, ss->base + SS_IV0 + i * 4);
> +		}
> +	}
> +	writel(tmp, ss->base + SS_CTL);
> +
> +	/* If we have only one SG, we can use kmap_atomic */
> +	if (sg_next(in_sg) == NULL && sg_next(out_sg) == NULL) {
> +		src_addr = kmap_atomic(sg_page(in_sg)) + in_sg->offset;
> +		if (src_addr == NULL) {
> +			dev_err(ss->dev, "kmap_atomic error for src SG\n");
> +			writel(0, ss->base + SS_CTL);
> +			mutex_unlock(&ss->lock);
> +			return -1;

-EINVAL ?

> +		}
> +		dst_addr = kmap_atomic(sg_page(out_sg)) + out_sg->offset;
> +		if (dst_addr == NULL) {
> +			dev_err(ss->dev, "kmap_atomic error for dst SG\n");
> +			writel(0, ss->base + SS_CTL);
> +			mutex_unlock(&ss->lock);
> +			kunmap_atomic(src_addr);
> +			return -1;

-EINVAL ?

> +		}
> +		src32 = (u32 *)src_addr;
> +		dst32 = (u32 *)dst_addr;
> +		ileft = areq->nbytes / 4;
> +		oleft = areq->nbytes / 4;
> +		do {
> +			if (ileft > 0 && rx_cnt > 0) {
> +				todo = min(rx_cnt, ileft);
> +				ileft -= todo;
> +				do {
> +					writel_relaxed(*src32++,
> +						       ss->base +
> +						       SS_RXFIFO);
> +					todo--;
> +				} while (todo > 0);
> +			}
> +			if (tx_cnt > 0) {
> +				todo = min(tx_cnt, oleft);
> +				oleft -= todo;
> +				do {
> +					*dst32++ = readl_relaxed(ss->base +
> +								SS_TXFIFO);
> +					todo--;
> +				} while (todo > 0);
> +			}
> +			tmp = readl_relaxed(ss->base + SS_FCSR);
> +			rx_cnt = SS_RXFIFO_SPACES(tmp);
> +			tx_cnt = SS_TXFIFO_SPACES(tmp);
> +		} while (oleft > 0);
> +		writel(0, ss->base + SS_CTL);
> +		mutex_unlock(&ss->lock);
> +		kunmap_atomic(src_addr);
> +		kunmap_atomic(dst_addr);
> +		return 0;
> +	}
> +
> +	/* If we have more than one SG, we cannot use kmap_atomic since
> +	 * we hold the mapping too long*/

Wrong comment style.

btw. can't you use generic scatterwalk here ?

> +	src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
> +	if (src_addr == NULL) {
> +		dev_err(ss->dev, "KMAP error for src SG\n");
> +		return -1;
> +	}

Why can't you just use dma_map_sg() or somesuch ?

[...]
> +EXPORT_SYMBOL_GPL(sunxi_aes_poll);

Again, don't export the symbol please.

[...]
> diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-cipher.h
> b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.h new file mode 100644
> index 0000000..ecfbf9c
> --- /dev/null
> +++ b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.h
> @@ -0,0 +1,8 @@
> +#include "sunxi-ss.h"
> +
> +extern struct sunxi_ss_ctx *ss;

Right. Please make it into one module and you won't need all this horror.
[...]

Re: [PATCH v3 1/4] crypto: Add Allwinner Security System crypto accelerator

[Corentin LABBE]

Le 14/06/2014 21:01, Marek Vasut a écrit :
> On Tuesday, June 10, 2014 at 02:43:14 PM, LABBE Corentin wrote:
>> Add support for the Security System included in Allwinner SoC A20.
>> The Security System is a hardware cryptographic accelerator that support
>> AES/MD5/SHA1/DES/3DES/PRNG algorithms.
>>
>> Signed-off-by: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> 
> [...]
> 
>> diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c
>> b/drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c new file mode 100644
>> index 0000000..fcdc8a4
>> --- /dev/null
>> +++ b/drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c
>> @@ -0,0 +1,118 @@
>> +/*
>> + * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
>> + *
>> + * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> + *
>> + * Support AES cipher with 128,192,256 bits keysize.
>> + * Support MD5 and SHA1 hash algorithms.
>> + * Support DES and 3DES
>> + * Support PRNG
>> + *
>> + * You could find the datasheet at
>> + * http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
>> + *
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation version 2 of the License
> 
> The license text seems incomplete.
> [...]

I will replace it with a simplier line "Licensed under the GPL-2."

> 
>> +static int sunxi_des3_cbc_encrypt(struct ablkcipher_request *areq)
>> +{
>> +	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
>> +	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
>> +
>> +	if (areq->info == NULL) {
>> +		dev_info(ss->dev, "Empty IV\n");
> 
> dev_err() here.
> 
>> +		return -EINVAL;
>> +	}
>> +
>> +	op->mode |= SS_ENCRYPTION;
>> +	op->mode |= SS_OP_3DES;
>> +	op->mode |= SS_CBC;
> 
> You can just op |= (foo | bar | baz) here .
> 
>> +	return sunxi_des_poll(areq);
>> +}
>> +
>> +static int sunxi_des3_cbc_decrypt(struct ablkcipher_request *areq)
>> +{
>> +	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
>> +	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
>> +
>> +	if (areq->info == NULL) {
>> +		dev_info(ss->dev, "Empty IV\n");
> 
> DTTO.
> 
>> +		return -EINVAL;
>> +	}
>> +
>> +	op->mode |= SS_DECRYPTION;
>> +	op->mode |= SS_OP_3DES;
>> +	op->mode |= SS_CBC;
> 
> DTTO.
> 
> [...]
>> +static int sunxi_ss_3des_init(void)
>> +{
>> +	int err = 0;
>> +	if (ss == NULL) {
>> +		pr_err("Cannot get Security System structure\n");
>> +		return -ENODEV;
>> +	}
>> +	err = crypto_register_alg(&sunxi_des3_alg);
>> +	if (err)
>> +		dev_err(ss->dev, "crypto_register_alg error for DES3\n");
>> +	else
>> +		dev_dbg(ss->dev, "Registred DES3\n");
>> +	return err;
>> +}
>> +
>> +static void __exit sunxi_ss_3des_exit(void)
>> +{
>> +	crypto_unregister_alg(&sunxi_des3_alg);
>> +}
>> +
>> +module_init(sunxi_ss_3des_init);
>> +module_exit(sunxi_ss_3des_exit);
> 
> I really dislike how you have multiple modules accessing the same hardware. That 
> just seems broken.

OK I abort my tries to make things optionnal.

> 
> [...]
> 
>> +static int sunxi_aes_cbc_encrypt(struct ablkcipher_request *areq)
>> +{
>> +	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
>> +	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
>> +
>> +	if (areq->info == NULL) {
>> +		dev_err(ss->dev, "Empty IV\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	op->mode |= SS_ENCRYPTION;
>> +	op->mode |= SS_OP_AES;
>> +	op->mode |= SS_CBC;
> 
> This looks just like the 3DES implementation. Please make this into a common 
> code if possible. I think you'd just need to have some switch statement based on 
> the type of cipher to fill op->mode, that's all.

I agree, I will simplify that.

> 
>> +	return sunxi_aes_poll(areq);
>> +}
> 
> [...]
> 
>> +static int sunxi_des_cbc_encrypt(struct ablkcipher_request *areq)
>> +{
>> +	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
>> +	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
>> +
>> +	if (areq->info == NULL) {
>> +		dev_info(ss->dev, "Empty IV\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	op->mode |= SS_ENCRYPTION;
>> +	op->mode |= SS_OP_DES;
>> +	op->mode |= SS_CBC;
> 
> Looks similar to 3DES and AES again.
> 
>> +	return sunxi_des_poll(areq);
>> +}
> 
> [...]
> 
>> diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c
>> b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c new file mode 100644
>> index 0000000..a27de49
> [...]
>> +int sunxi_cipher_init(struct crypto_tfm *tfm)
>> +{
>> +	struct sunxi_req_ctx *op = crypto_tfm_ctx(tfm);
>> +	memset(op, 0, sizeof(struct sunxi_req_ctx));
>> +	return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(sunxi_cipher_init);
> 
> This is wrong, you don't want to export this symbol.
> 
>> +void sunxi_cipher_exit(struct crypto_tfm *tfm)
>> +{
>> +}
>> +EXPORT_SYMBOL_GPL(sunxi_cipher_exit);
> 
> Why do you even need an empty function ?

Ok, I will clean that

> 
>> +int sunxi_aes_poll(struct ablkcipher_request *areq)
>> +{
>> +	u32 tmp;
>> +	struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
>> +	struct sunxi_req_ctx *op = crypto_ablkcipher_ctx(tfm);
>> +	unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
>> +	/* when activating SS, the default FIFO space is 32 */
>> +	u32 rx_cnt = 32;
>> +	u32 tx_cnt = 0;
>> +	u32 v;
>> +	int i;
>> +	struct scatterlist *in_sg;
>> +	struct scatterlist *out_sg;
>> +	void *src_addr;
>> +	void *dst_addr;
>> +	unsigned int ileft = areq->nbytes;
>> +	unsigned int oleft = areq->nbytes;
>> +	unsigned int sgileft = areq->src->length;
>> +	unsigned int sgoleft = areq->dst->length;
>> +	unsigned int todo;
>> +	u32 *src32;
>> +	u32 *dst32;
>> +
>> +	tmp = op->mode;
>> +	tmp |= SS_ENABLED;
> 
> tmp is not a good name for a variable .

renamed to mode

> 
>> +	in_sg = areq->src;
>> +	out_sg = areq->dst;
>> +	if (areq->src == NULL || areq->dst == NULL) {
> 
> You do a NULL pointer test here, yet you access areq->src->length in sgileft 
> above . DTTO for areq->dst->length . That would crash much earlier than here.
> 
>> +		dev_err(ss->dev, "ERROR: Some SGs are NULL %u\n", areq->nbytes);
>> +		return -1;
>> +	}
>> +	mutex_lock(&ss->lock);
>> +	if (areq->info != NULL) {
>> +		for (i = 0; i < op->keylen; i += 4) {
>> +			v = *(u32 *)(op->key + i);
> 
> Consider that op->key would be magically unaligned ... then you'd trigger 
> alignment fault here. Make the "op->key" an u32[] and drop those crap casts 
> here.

I Agree

> 
>> +			writel(v, ss->base + SS_KEY0 + i);
>> +		}
>> +		for (i = 0; i < 4 && i < ivsize / 4; i++) {
>> +			v = *(u32 *)(areq->info + i * 4);
>> +			writel(v, ss->base + SS_IV0 + i * 4);
>> +		}
>> +	}
>> +	writel(tmp, ss->base + SS_CTL);
>> +
>> +	/* If we have only one SG, we can use kmap_atomic */
>> +	if (sg_next(in_sg) == NULL && sg_next(out_sg) == NULL) {
>> +		src_addr = kmap_atomic(sg_page(in_sg)) + in_sg->offset;
>> +		if (src_addr == NULL) {
>> +			dev_err(ss->dev, "kmap_atomic error for src SG\n");
>> +			writel(0, ss->base + SS_CTL);
>> +			mutex_unlock(&ss->lock);
>> +			return -1;
> 
> -EINVAL ?
> 
>> +		}
>> +		dst_addr = kmap_atomic(sg_page(out_sg)) + out_sg->offset;
>> +		if (dst_addr == NULL) {
>> +			dev_err(ss->dev, "kmap_atomic error for dst SG\n");
>> +			writel(0, ss->base + SS_CTL);
>> +			mutex_unlock(&ss->lock);
>> +			kunmap_atomic(src_addr);
>> +			return -1;
> 
> -EINVAL ?
> 
>> +		}
>> +		src32 = (u32 *)src_addr;
>> +		dst32 = (u32 *)dst_addr;
>> +		ileft = areq->nbytes / 4;
>> +		oleft = areq->nbytes / 4;
>> +		do {
>> +			if (ileft > 0 && rx_cnt > 0) {
>> +				todo = min(rx_cnt, ileft);
>> +				ileft -= todo;
>> +				do {
>> +					writel_relaxed(*src32++,
>> +						       ss->base +
>> +						       SS_RXFIFO);
>> +					todo--;
>> +				} while (todo > 0);
>> +			}
>> +			if (tx_cnt > 0) {
>> +				todo = min(tx_cnt, oleft);
>> +				oleft -= todo;
>> +				do {
>> +					*dst32++ = readl_relaxed(ss->base +
>> +								SS_TXFIFO);
>> +					todo--;
>> +				} while (todo > 0);
>> +			}
>> +			tmp = readl_relaxed(ss->base + SS_FCSR);
>> +			rx_cnt = SS_RXFIFO_SPACES(tmp);
>> +			tx_cnt = SS_TXFIFO_SPACES(tmp);
>> +		} while (oleft > 0);
>> +		writel(0, ss->base + SS_CTL);
>> +		mutex_unlock(&ss->lock);
>> +		kunmap_atomic(src_addr);
>> +		kunmap_atomic(dst_addr);
>> +		return 0;
>> +	}
>> +
>> +	/* If we have more than one SG, we cannot use kmap_atomic since
>> +	 * we hold the mapping too long*/
> 
> Wrong comment style.
> 
> btw. can't you use generic scatterwalk here ?

I will check if it simplify the code.

> 
>> +	src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
>> +	if (src_addr == NULL) {
>> +		dev_err(ss->dev, "KMAP error for src SG\n");
>> +		return -1;
>> +	}
> 
> Why can't you just use dma_map_sg() or somesuch ?

I do not see why I will use a DMA function in a driver without DMA support.
Perhaps I do not know some tricks.
Can I use writel/readl on address gived by DMA API ?


> 
> [...]
>> +EXPORT_SYMBOL_GPL(sunxi_aes_poll);
> 
> Again, don't export the symbol please.
> 
> [...]
>> diff --git a/drivers/crypto/sunxi-ss/sunxi-ss-cipher.h
>> b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.h new file mode 100644
>> index 0000000..ecfbf9c
>> --- /dev/null
>> +++ b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.h
>> @@ -0,0 +1,8 @@
>> +#include "sunxi-ss.h"
>> +
>> +extern struct sunxi_ss_ctx *ss;
> 
> Right. Please make it into one module and you won't need all this horror.
> [...]
> 

Thanks for your review

Regards

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Re: [PATCH v3 1/4] crypto: Add Allwinner Security System crypto accelerator

[Marek Vasut]

On Sunday, June 22, 2014 at 01:58:08 PM, Corentin LABBE wrote:
[...]
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License as published by
> >> + * the Free Software Foundation version 2 of the License
> > 
> > The license text seems incomplete.
> > [...]
> 
> I will replace it with a simplier line "Licensed under the GPL-2."

I'd suggest you to use the SPDX license identifiers then, but that's not 
something the kernel crowd agreed upon yet IIRC.Therefore , just make the text 
complete please.

[...]

> >> +	src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
> >> +	if (src_addr == NULL) {
> >> +		dev_err(ss->dev, "KMAP error for src SG\n");
> >> +		return -1;
> >> +	}
> > 
> > Why can't you just use dma_map_sg() or somesuch ?
> 
> I do not see why I will use a DMA function in a driver without DMA support.
> Perhaps I do not know some tricks.
> Can I use writel/readl on address gived by DMA API ?

Oh, ok, good question -- dear list, shall one use sg_page()+kmap or sg_virt()?

btw. I just noticed you're just feeding the hardware FIFO in a loop with data in 
the scatterlists, do I understand it correctly ? The driver will consume quite a 
lot of CPU time to do that, can you not implement DMA here ?

[...]

Best regards,
Marek Vasut

Re: [PATCH v3 1/4] crypto: Add Allwinner Security System crypto accelerator

[Russell King - ARM Linux]

On Sun, Jun 22, 2014 at 02:23:15PM +0200, Marek Vasut wrote:
> On Sunday, June 22, 2014 at 01:58:08 PM, Corentin LABBE wrote:
> [...]
> > >> + * This program is free software; you can redistribute it and/or modify
> > >> + * it under the terms of the GNU General Public License as published by
> > >> + * the Free Software Foundation version 2 of the License
> > > 
> > > The license text seems incomplete.
> > > [...]
> > 
> > I will replace it with a simplier line "Licensed under the GPL-2."
> 
> I'd suggest you to use the SPDX license identifiers then, but that's not 
> something the kernel crowd agreed upon yet IIRC.Therefore , just make the text 
> complete please.

Marek,

The full text of the first paragraph (in COPYING) is:

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

which is deemed to be entirely sufficient; quoting the full text is
discouraged, especially when it includes the FSF address.  It is also
acceptable to restrict it to version 2 only, in which case something
like this can be used:

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License version 2 as
   published by the Free Software Foundation.

Of course, it's up to the author to make up their own mind at the end
of the day.

> Oh, ok, good question -- dear list, shall one use sg_page()+kmap or sg_virt()?

sg_page() + kmap() is preferred, because sg_virt() fails with highmem.
Using sg_virt() means you restrict the driver to non-highmem memory,
and if the kernel wants to place the data into a highmem page, it will
have to use bounce buffers (so it's inefficient).

What's even better is to use the scatterlist iterator, which will handle
this for you.  See the sg_miter_*() functions.

-- 
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Re: [PATCH v3 1/4] crypto: Add Allwinner Security System crypto accelerator

[Marek Vasut]

On Sunday, June 22, 2014 at 02:33:35 PM, Russell King - ARM Linux wrote:
> On Sun, Jun 22, 2014 at 02:23:15PM +0200, Marek Vasut wrote:
> > On Sunday, June 22, 2014 at 01:58:08 PM, Corentin LABBE wrote:
> > [...]
> > 
> > > >> + * This program is free software; you can redistribute it and/or
> > > >> modify + * it under the terms of the GNU General Public License as
> > > >> published by + * the Free Software Foundation version 2 of the
> > > >> License
> > > > 
> > > > The license text seems incomplete.
> > > > [...]
> > > 
> > > I will replace it with a simplier line "Licensed under the GPL-2."
> > 
> > I'd suggest you to use the SPDX license identifiers then, but that's not
> > something the kernel crowd agreed upon yet IIRC.Therefore , just make the
> > text complete please.
> 
> Marek,
> 
> The full text of the first paragraph (in COPYING) is:
> 
>     This program is free software; you can redistribute it and/or modify
>     it under the terms of the GNU General Public License as published by
>     the Free Software Foundation; either version 2 of the License, or
>     (at your option) any later version.
> 
> which is deemed to be entirely sufficient; quoting the full text is
> discouraged, especially when it includes the FSF address.  It is also
> acceptable to restrict it to version 2 only, in which case something
> like this can be used:
> 
>    This program is free software; you can redistribute it and/or modify
>    it under the terms of the GNU General Public License version 2 as
>    published by the Free Software Foundation.
> 
> Of course, it's up to the author to make up their own mind at the end
> of the day.

Ah, I fully agree. Thank you for clarifying this.

> > Oh, ok, good question -- dear list, shall one use sg_page()+kmap or
> > sg_virt()?
> 
> sg_page() + kmap() is preferred, because sg_virt() fails with highmem.
> Using sg_virt() means you restrict the driver to non-highmem memory,
> and if the kernel wants to place the data into a highmem page, it will
> have to use bounce buffers (so it's inefficient).

Ah, thanks for explaining this!

> What's even better is to use the scatterlist iterator, which will handle
> this for you.  See the sg_miter_*() functions.

The scatterwalk ( include/crypto/scatterwalk.h ) should work pretty much the 
same then, right ? But with the added benefit that it's crypto-friendly such 
that it handles both the input and output scatterlists of the crypto 
transformation etc.

Please correct me if I'm mistaken.

Best regards,
Marek Vasut

Re: [PATCH v3 1/4] crypto: Add Allwinner Security System crypto accelerator

[Russell King - ARM Linux]

On Tue, Jun 10, 2014 at 02:43:14PM +0200, LABBE Corentin wrote:
> +int sunxi_aes_poll(struct ablkcipher_request *areq)
> +{
...
> +	if (areq->src == NULL || areq->dst == NULL) {
> +		dev_err(ss->dev, "ERROR: Some SGs are NULL %u\n", areq->nbytes);
> +		return -1;

You return -1 from here quite frequently.  Have you verified that there
is no way for this return value to get to userspace?

Even if it can't get to userspace now, what if someone modifies the code
so it can be returned?

I detest crap that's written with "return -1" in it because it looks like
there is no care with the established error handling semantics for the
kernel (small negative numbers are errno codes.)

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[PATCH v3 2/4] crypto: Update makefile and Kconfig for Security System

[LABBE Corentin]

Add necessary changes for configuring and compiling the Security System driver.

Signed-off-by: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/crypto/Kconfig  | 91 +++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/crypto/Makefile |  1 +
 2 files changed, 92 insertions(+)

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 03ccdb0..ed1c918 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -418,4 +418,95 @@ config CRYPTO_DEV_MXS_DCP
 	  To compile this driver as a module, choose M here: the module
 	  will be called mxs-dcp.
 
+config CRYPTO_DEV_SUNXI_SS
+	tristate "Support for Allwinner Security System cryptographic accelerator"
+	depends on ARCH_SUNXI
+	help
+	  Some Allwinner SoC have a crypto accelerator named
+	  Security System. Select this if you want to use it.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called sunxi-ss.
+
+if CRYPTO_DEV_SUNXI_SS
+config CRYPTO_DEV_SUNXI_SS_PRNG
+	tristate "Security System PRNG"
+	select CRYPTO_RNG2
+	help
+	  If you enable this option, the SS will provide a pseudo random
+	  number generator.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called sunxi-ss-prng.
+
+config CRYPTO_DEV_SUNXI_SS_HASH
+	tristate "Security System hash common"
+	help
+	  Common parts of Security System shared by hash algorithms.
+
+config CRYPTO_DEV_SUNXI_SS_CIPHER
+	tristate "Security System cipher common"
+	help
+	  Common parts of Security System shared by cipher algorithms.
+
+config CRYPTO_DEV_SUNXI_SS_MD5
+	tristate "Security System MD5"
+	select CRYPTO_MD5
+	select CRYPTO_DEV_SUNXI_SS_HASH
+	help
+	  If you enable this option, the SS will provide MD5 hardware
+	  acceleration.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called sunxi-ss-md5.
+
+config CRYPTO_DEV_SUNXI_SS_SHA1
+	tristate "Security System SHA1"
+	select CRYPTO_SHA1
+	select CRYPTO_DEV_SUNXI_SS_HASH
+	help
+	  If you enable this option, the SS will provide SHA1 hardware
+	  acceleration.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called sunxi-ss-sha1.
+
+config CRYPTO_DEV_SUNXI_SS_AES
+	tristate "Security System AES"
+	select CRYPTO_AES
+	select CRYPTO_BLKCIPHER
+	select CRYPTO_DEV_SUNXI_SS_CIPHER
+	help
+	  If you enable this option, the SS will provide AES hardware
+	  acceleration.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called sunxi-ss-aes.
+
+config CRYPTO_DEV_SUNXI_SS_DES
+	tristate "Security System DES"
+	select CRYPTO_DES
+	select CRYPTO_BLKCIPHER
+	select CRYPTO_DEV_SUNXI_SS_CIPHER
+	help
+	  If you enable this option, the SS will provide DES hardware
+	  acceleration.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called sunxi-ss-des.
+
+config CRYPTO_DEV_SUNXI_SS_3DES
+	tristate "Security System 3DES"
+	select CRYPTO_DES
+	select CRYPTO_BLKCIPHER
+	select CRYPTO_DEV_SUNXI_SS_CIPHER
+	help
+	  If you enable this option, the SS will provide 3DES hardware
+	  acceleration.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called sunxi-ss-3des.
+
+endif #CRYPTO_DEV_SUNXI_SS
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 482f090..855292a 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
 obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
 obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
 obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS) += sunxi-ss/
-- 
1.8.5.5

Re: [PATCH v3 2/4] crypto: Update makefile and Kconfig for Security System

[Marek Vasut]

On Tuesday, June 10, 2014 at 02:43:15 PM, LABBE Corentin wrote:
> Add necessary changes for configuring and compiling the Security System
> driver.
> 
> Signed-off-by: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  drivers/crypto/Kconfig  | 91
> +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/crypto/Makefile
> |  1 +
>  2 files changed, 92 insertions(+)

This should be part of 1/4, otherwise 1/4 just adds dead code.

Best regards,
Marek Vasut

Re: [PATCH v3 2/4] crypto: Update makefile and Kconfig for Security System

[Corentin LABBE]

Le 14/06/2014 21:01, Marek Vasut a écrit :
> On Tuesday, June 10, 2014 at 02:43:15 PM, LABBE Corentin wrote:
>> Add necessary changes for configuring and compiling the Security System
>> driver.
>>
>> Signed-off-by: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>>  drivers/crypto/Kconfig  | 91
>> +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/crypto/Makefile
>> |  1 +
>>  2 files changed, 92 insertions(+)
> 
> This should be part of 1/4, otherwise 1/4 just adds dead code.
> 

If I do that 1/4 add to the makefile a path that do not exists.

But as you like I will change that.

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Re: [PATCH v3 2/4] crypto: Update makefile and Kconfig for Security System

[Marek Vasut]

On Sunday, June 22, 2014 at 01:58:38 PM, Corentin LABBE wrote:
> Le 14/06/2014 21:01, Marek Vasut a écrit :
> > On Tuesday, June 10, 2014 at 02:43:15 PM, LABBE Corentin wrote:
> >> Add necessary changes for configuring and compiling the Security System
> >> driver.
> >> 
> >> Signed-off-by: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> >> ---
> >> 
> >>  drivers/crypto/Kconfig  | 91
> >> 
> >> +++++++++++++++++++++++++++++++++++++++++++++++++
> >> drivers/crypto/Makefile
> >> 
> >> |  1 +
> >>  
> >>  2 files changed, 92 insertions(+)
> > 
> > This should be part of 1/4, otherwise 1/4 just adds dead code.
> 
> If I do that 1/4 add to the makefile a path that do not exists.
> 
> But as you like I will change that.

Well, the point is to add stuff which is logically coupled together (code, 
Makefile entry, Kconfig entry) in a single patch if possible.

Best regards,
Marek Vasut

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[PATCH v3 3/4] ARM: sun7i: dt: Add Security System to A20 SoC DTS

[LABBE Corentin]

The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on many Allwinner SoC.

This patch enable the Security System on the Allwinner A20 SoC Device-tree.

Signed-off-by: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 6acdbdf..19b1ced 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -529,6 +529,14 @@
 			status = "disabled";
 		};
 
+		crypto: crypto-engine@01c15000 {
+			compatible = "allwinner,sun7i-a20-crypto";
+			reg = <0x01c15000 0x1000>;
+			interrupts = <0 86 4>;
+			clocks = <&ahb_gates 5>, <&ss_clk>;
+			clock-names = "ahb", "mod";
+		};
+
 		spi2: spi@01c17000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c17000 0x1000>;
-- 
1.8.5.5

[PATCH v3 4/4] ARM: sunxi: dt: Add DT bindings documentation for SUNXI Security System

[LABBE Corentin]

This patch adds documentation for Device-Tree bindings for the Security
System cryptographic accelerator driver.

Signed-off-by: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 Documentation/devicetree/bindings/crypto/sunxi-ss.txt | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/sunxi-ss.txt

diff --git a/Documentation/devicetree/bindings/crypto/sunxi-ss.txt b/Documentation/devicetree/bindings/crypto/sunxi-ss.txt
new file mode 100644
index 0000000..a566803
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/sunxi-ss.txt
@@ -0,0 +1,9 @@
+* Allwinner Security System found on A20 SoC
+
+Required properties:
+- compatible : Should be "allwinner,sun7i-a20-crypto".
+- reg: Should contain the Security System register location and length.
+- interrupts: Should contain the IRQ line for the Security System.
+- clocks : A phandle to the functional clock node of the Security System module
+- clock-names : Name of the functional clock, should be "ahb" and "mod".
+
-- 
1.8.5.5