From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pratyush Anand Subject: Re: [PATCH v2 1/8] PCI: designware: add rd[wr]_other_conf API Date: Wed, 18 Jun 2014 12:07:07 +0530 Message-ID: <20140618063706.GA6098@pratyush-vbox> References: <1402426287-31157-1-git-send-email-m-karicheri2@ti.com> <1402426287-31157-2-git-send-email-m-karicheri2@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Return-path: Content-Disposition: inline In-Reply-To: <1402426287-31157-2-git-send-email-m-karicheri2@ti.com> Sender: linux-doc-owner@vger.kernel.org To: Murali Karicheri Cc: "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-doc@vger.kernel.org" , Santosh Shilimkar , Russell King , Grant Likely , Rob Herring , Mohit KUMAR DCG , Jingoo Han , Bjorn Helgaas , Richard Zhu , Kishon Vijay Abraham I , Marek Vasut , Arnd Bergmann , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Randy List-Id: devicetree@vger.kernel.org On Wed, Jun 11, 2014 at 02:51:20AM +0800, Murali Karicheri wrote: > v3.65 version of the designware h/w, requires application space > registers to be configured to access the remote EP config space. > To support this, add rd[wr]_other_conf API in the pcie_host_opts > > Signed-off-by: Murali Karicheri > > CC: Santosh Shilimkar > CC: Russell King > CC: Grant Likely > CC: Rob Herring > CC: Mohit Kumar > CC: Jingoo Han > CC: Bjorn Helgaas > CC: Pratyush Anand > CC: Richard Zhu > CC: Kishon Vijay Abraham I > CC: Marek Vasut > CC: Arnd Bergmann > CC: Pawel Moll > CC: Mark Rutland > CC: Ian Campbell > CC: Kumar Gala > CC: Randy Dunlap > CC: Grant Likely > > --- > drivers/pci/host/pcie-designware.c | 12 ++++++++++-- > drivers/pci/host/pcie-designware.h | 4 ++++ > 2 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c > index c4e3732..e8f5d8d 100644 > --- a/drivers/pci/host/pcie-designware.c > +++ b/drivers/pci/host/pcie-designware.c > @@ -654,7 +654,11 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, > > spin_lock_irqsave(&pp->conf_lock, flags); > if (bus->number != pp->root_bus_nr) > - ret = dw_pcie_rd_other_conf(pp, bus, devfn, > + if (pp->ops->rd_other_conf) > + ret = pp->ops->rd_other_conf(pp, bus, devfn, > + where, size, val); > + else > + ret = dw_pcie_rd_other_conf(pp, bus, devfn, > where, size, val); > else > ret = dw_pcie_rd_own_conf(pp, where, size, val); > @@ -680,7 +684,11 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, > > spin_lock_irqsave(&pp->conf_lock, flags); > if (bus->number != pp->root_bus_nr) > - ret = dw_pcie_wr_other_conf(pp, bus, devfn, > + if (pp->ops->wr_other_conf) > + ret = pp->ops->wr_other_conf(pp, bus, devfn, > + where, size, val); > + else > + ret = dw_pcie_wr_other_conf(pp, bus, devfn, > where, size, val); > else > ret = dw_pcie_wr_own_conf(pp, where, size, val); > diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h > index 3063b35..2d6dd66 100644 > --- a/drivers/pci/host/pcie-designware.h > +++ b/drivers/pci/host/pcie-designware.h > @@ -62,6 +62,10 @@ struct pcie_host_ops { > u32 val, void __iomem *dbi_base); > int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); > int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); > + int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus, > + unsigned int devfn, int where, int size, u32 *val); > + int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus, > + unsigned int devfn, int where, int size, u32 val); > int (*link_up)(struct pcie_port *pp); > void (*host_init)(struct pcie_port *pp); > }; Reviewed-by: Pratyush Anand > -- > 1.7.9.5