From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
Cc: "Rob Herring" <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
"Pawel Moll" <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
"Mark Rutland" <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
"Ian Campbell"
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
"Kumar Gala" <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
"Russell King" <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
"Ben Dooks" <ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org>,
"Kukjin Kim" <kgene.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
"Benoît Cousson"
<bcousson-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
"Tony Lindgren" <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>,
"Stephen Warren"
<swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
"Thierry Reding"
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
"Catalin Marinas" <catalin.marinas-5wv7dgnIgG8@public.gmane.org>,
"Will Deacon" <will.deacon-5wv7dgnIgG8@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH] arm/arm64: DT: Fix GICv2 CPU interface size
Date: Wed, 25 Jun 2014 15:31:34 +0200 [thread overview]
Message-ID: <20140625133134.GQ19730@lukather> (raw)
In-Reply-To: <1403692675-26503-1-git-send-email-marc.zyngier-5wv7dgnIgG8@public.gmane.org>
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On Wed, Jun 25, 2014 at 11:37:54AM +0100, Marc Zyngier wrote:
> All the Cortex-{A7,A15} implementations are using a GICv2. Same for
> the current arm64 platforms.
>
> Turns out that most of these platforms have described their GIC CPU
> interface size as being 4kB. while it is actually 8kB (the GICC_DIR
> register lives at offset 0x1000).
>
> This was found when converting the GIC driver to use EOImode==1 on
> GICv2-based systems. It uses the GICC_DIR register, and the result
> is a very early firework...
>
> Signed-off-by: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
Just tested this on an Allwinner A31.
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Tested-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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prev parent reply other threads:[~2014-06-25 13:31 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-25 10:37 [PATCH] arm/arm64: DT: Fix GICv2 CPU interface size Marc Zyngier
2014-06-25 12:21 ` Rob Herring
[not found] ` <CAL_Jsq+rS3FE8_F-4qdUUTaJ6X9XNFP2d2h7CdU9hDRG0KG9uA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-06-25 12:32 ` Marc Zyngier
[not found] ` <1403692675-26503-1-git-send-email-marc.zyngier-5wv7dgnIgG8@public.gmane.org>
2014-06-25 11:11 ` Thierry Reding
2014-06-25 13:31 ` Maxime Ripard [this message]
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