From: Tejun Heo <tj@kernel.org>
To: "Antoine Ténart" <antoine.tenart@free-electrons.com>
Cc: sebastian.hesselbarth@gmail.com, kishon@ti.com,
alexandre.belloni@free-electrons.com,
thomas.petazzoni@free-electrons.com, zmxu@marvell.com,
jszhang@marvell.com, linux-arm-kernel@lists.infradead.org,
linux-ide@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Hans de Goede <hdegoede@redhat.com>
Subject: Re: [PATCH v9 3/7] ata: libahci: allow to use multiple PHYs
Date: Tue, 8 Jul 2014 09:40:00 -0400 [thread overview]
Message-ID: <20140708134000.GC4979@htj.dyndns.org> (raw)
In-Reply-To: <1404728173-20263-4-git-send-email-antoine.tenart@free-electrons.com>
(Cc'ing Hans.)
On Mon, Jul 07, 2014 at 12:16:09PM +0200, Antoine Ténart wrote:
> @@ -482,6 +482,13 @@ void ahci_save_initial_config(struct device *dev,
> port_map &= mask_port_map;
> }
>
> + /*
> + * If port_map was filled automatically when finding port sub-nodes,
> + * make sure we get the right set here.
> + */
> + if (hpriv->port_map)
> + port_map &= hpriv->port_map;
> +
So, hpriv->port is both input and output? This is messy and can lead
to confusing failures and there now are multiple ways to modify
port_map. If carrying this information through ahci_host_priv is
necessary, let's remove the direct params and introduce new input
fields to the struct.
> /**
> + * ahci_platform_enable_phys - Enable PHYs
> + * @hpriv: host private area to store config values
> + *
> + * This function enables all the PHYs found in hpriv->phys, if any.
> + * If a PHY fails to be enabled, it disables all the PHYs already
> + * enabled in reverse order and returns an error.
> + *
> + * RETURNS:
> + * 0 on success otherwise a negative error code
> + */
> +int ahci_platform_enable_phys(struct ahci_host_priv *hpriv)
> +{
> + int i, rc = 0;
> +
> + for (i = 0; i < hpriv->nphys; i++) {
> + rc = phy_init(hpriv->phys[i]);
> + if (rc)
> + goto disable_phys;
> +
> + rc = phy_power_on(hpriv->phys[i]);
> + if (rc) {
> + phy_exit(hpriv->phys[i]);
> + goto disable_phys;
> + }
> + }
> +
> + return 0;
> +
> +disable_phys:
> + while (--i >= 0) {
> + phy_power_off(hpriv->phys[i]);
> + phy_exit(hpriv->phys[i]);
> + }
> + return rc;
> +}
> +EXPORT_SYMBOL_GPL(ahci_platform_enable_phys);
Do we need to make hpriv->phys[] dynamically allocated? We already
have hpriv->clks[AHCI_MAX_CLKS] and it's unlikely that we're gonna
need more than several phys per host. Let's go with a simpler fixed
array.
Thanks.
--
tejun
next prev parent reply other threads:[~2014-07-08 13:40 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-07 10:16 [PATCH v9 0/7] ARM: berlin: add AHCI support Antoine Ténart
2014-07-07 10:16 ` [PATCH v9 1/7] phy: add a driver for the Berlin SATA PHY Antoine Ténart
[not found] ` <1404728173-20263-2-git-send-email-antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-07-08 12:29 ` Kishon Vijay Abraham I
2014-07-08 12:36 ` Antoine Ténart
2014-07-08 13:00 ` Sebastian Hesselbarth
2014-07-08 13:13 ` Kishon Vijay Abraham I
2014-07-07 10:16 ` [PATCH v9 2/7] Documentation: bindings: add " Antoine Ténart
2014-07-07 10:16 ` [PATCH v9 3/7] ata: libahci: allow to use multiple PHYs Antoine Ténart
2014-07-08 13:40 ` Tejun Heo [this message]
[not found] ` <20140708134000.GC4979-Gd/HAXX7CRxy/B6EtB590w@public.gmane.org>
2014-07-08 17:03 ` Antoine Ténart
2014-07-08 17:18 ` Tejun Heo
2014-07-08 17:49 ` Antoine Ténart
2014-07-08 21:40 ` Tejun Heo
2014-07-09 8:23 ` Antoine Ténart
2014-07-09 13:59 ` Tejun Heo
2014-07-09 14:02 ` Hans de Goede
2014-07-09 15:24 ` Alexandre Belloni
2014-07-09 15:42 ` Tejun Heo
2014-07-09 7:22 ` Hans de Goede
2014-07-08 13:42 ` Tejun Heo
2014-07-08 17:05 ` Antoine Ténart
2014-07-07 10:16 ` [PATCH v9 4/7] ata: ahci_platform: add a generic AHCI compatible Antoine Ténart
2014-07-07 10:16 ` [PATCH v9 5/7] Documentation: bindings: document the sub-nodes AHCI bindings Antoine Ténart
2014-07-07 10:16 ` [PATCH v9 6/7] ARM: berlin: add the AHCI node for the BG2Q Antoine Ténart
2014-07-07 10:16 ` [PATCH v9 7/7] ARM: berlin: enable the eSATA interface on the BG2Q DMP Antoine Ténart
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