[PATCH 1/3] arm: dra7xx: Add hwmod data for MDIO and CPSW

[PATCH 1/3] arm: dra7xx: Add hwmod data for MDIO and CPSW

[Sebastian Andrzej Siewior]

Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Praveen Rao <prao@ti.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 96 +++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 20b4398..0fa2c66 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1845,6 +1845,85 @@ static struct omap_hwmod dra7xx_vcp2_hwmod = {
 };
 
 /*
+ * 'gmac' class
+ * cpsw/gmac sub system
+ */
+static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
+	.rev_offs	= 0x0,
+	.sysc_offs	= 0x8,
+	.syss_offs	= 0x4,
+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+			SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+			MSTANDBY_NO),
+	.sysc_fields	= &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
+	.name	= "gmac",
+	.sysc	= &dra7xx_gmac_sysc,
+};
+
+static struct omap_hwmod_irq_info dra7xx_gmac_irqs[] = {
+	{ .name = "c0_rx_thresh_pend", .irq = 50 + DRA7XX_IRQ_GIC_START, },
+	{ .name = "c0_rx_pend", .irq = 51 + DRA7XX_IRQ_GIC_START, },
+	{ .name = "c0_tx_pend", .irq = 52 + DRA7XX_IRQ_GIC_START, },
+	{ .name = "c0_misc_pend", .irq = 53 + DRA7XX_IRQ_GIC_START, },
+	{ .irq = -1 },
+};
+static struct omap_hwmod_addr_space dra7xx_gmac_addr_space[] = {
+	/* cpsw ss */
+	{
+		.pa_start	= 0x48484000,
+		.pa_end	= 0x48484000 + SZ_2K - 1,
+	},
+	/* cpsw wr */
+	{
+		.pa_start	= 0x48485200,
+		.pa_end	= 0x48485200 + SZ_256 - 1,
+		.flags	= ADDR_TYPE_RT,
+	},
+	{ }
+};
+
+static struct omap_hwmod dra7xx_gmac_hwmod = {
+	.name		= "gmac",
+	.class		= &dra7xx_gmac_hwmod_class,
+	.clkdm_name	= "gmac_clkdm",
+	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+	.mpu_irqs	= dra7xx_gmac_irqs,
+	.main_clk	= "dpll_gmac_ck",
+	.prcm	= {
+		.omap4	= {
+			.clkctrl_offs	= DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
+			.context_offs	= DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
+ * 'mdio' class
+ */
+static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
+	.name	= "davinci_mdio",
+};
+
+static struct omap_hwmod_addr_space dra7xx_mdio_addr_space[] = {
+	{
+		.pa_start	= 0x48485000,
+		.pa_end		= 0x48485000 + SZ_256 - 1,
+	},
+	{ }
+};
+static struct omap_hwmod dra7xx_mdio_hwmod = {
+	.name		= "davinci_mdio",
+	.class		= &dra7xx_mdio_hwmod_class,
+	.clkdm_name	= "gmac_clkdm",
+	.main_clk	= "dpll_gmac_ck",
+};
+
+/*
  * 'wd_timer' class
  *
  */
@@ -2015,6 +2094,21 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__gmac = {
+	.master         = &dra7xx_l4_per2_hwmod,
+	.slave          = &dra7xx_gmac_hwmod,
+	.clk            = "dpll_gmac_ck",
+	.addr           = dra7xx_gmac_addr_space,
+	.user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
+	.master         = &dra7xx_gmac_hwmod,
+	.slave          = &dra7xx_mdio_hwmod,
+	.addr           = dra7xx_mdio_addr_space,
+	.user           = OCP_USER_MPU,
+};
+
 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
 	{
 		.pa_start	= 0x4a056000,
@@ -2642,6 +2736,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l4_wkup__ctrl_module_wkup,
 	&dra7xx_l4_wkup__dcan1,
 	&dra7xx_l4_per2__dcan2,
+	&dra7xx_l4_per2__gmac,
+	&dra7xx_gmac__mdio,
 	&dra7xx_l4_cfg__dma_system,
 	&dra7xx_l3_main_1__dss,
 	&dra7xx_l3_main_1__dispc,
-- 
2.0.1

[PATCH 2/3] arm: dts: dra7: Enable CPSW and MDIO for dra7xx EVM

[Sebastian Andrzej Siewior]

From: Mugunthan V N <mugunthanvnm@ti.com>

Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active
and sleep states and enable them in board evm dts file.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Resolved merge conflict and rebased on 3.8 kernel.
Update the pinmux configuration for CPSW and MDIO by removing the
macro definitons to match the 3.8 implementation.]
Signed-off-by: Praveen Rao <prao@ti.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
 arch/arm/boot/dts/dra7-evm.dts | 61 ++++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra7.dtsi    | 48 +++++++++++++++++++++++++++++++++
 2 files changed, 109 insertions(+)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 4adc280..956a7bd 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -94,6 +94,46 @@
 		>;
 	};
 
+	cpsw_default_pins: pinmux_cpsw_default_pins {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			0x250	0x0 /* rgmii1_tclk PIN_OUTPUT | MUX_MODE0 */
+			0x254	0x0 /* rgmii1_tctl PIN_OUTPUT | MUX_MODE0 */
+			0x258	0x0 /* rgmii1_td3 PIN_OUTPUT | MUX_MODE0 */
+			0x25c	0x0 /* rgmii1_td2 PIN_OUTPUT | MUX_MODE0 */
+			0x260	0x0 /* rgmii1_td1 PIN_OUTPUT | MUX_MODE0 */
+			0x264	0x0 /* rgmii1_td0 PIN_OUTPUT | MUX_MODE0 */
+			0x268	0x00040000 /* rgmii1_rclk PIN_INPUT | MUX_MODE0 */
+			0x26c	0x00040000 /* rgmii1_rctl PIN_INPUT | MUX_MODE0 */
+			0x270	0x00040000 /* rgmii1_rd3 PIN_INPUT | MUX_MODE0 */
+			0x274	0x00040000 /* rgmii1_rd2 PIN_INPUT | MUX_MODE0 */
+			0x278	0x00040000 /* rgmii1_rd1 PIN_INPUT | MUX_MODE0 */
+			0x27c	0x00040000 /* rgmii1_rd0 PIN_INPUT | MUX_MODE0 */
+
+			/* Slave 2 */
+			0x198	0x4 /* rgmii2_tclk PIN_OUTPUT | MUX_MODE4 */
+			0x19c	0x4 /* rgmii2_tctl PIN_OUTPUT | MUX_MODE4 */
+			0x1a0	0x4 /* rgmii2_td3 PIN_OUTPUT | MUX_MODE4 */
+			0x1a4	0x4 /* rgmii2_td2 PIN_OUTPUT | MUX_MODE4 */
+			0x1a8	0x4 /* rgmii2_td1 PIN_OUTPUT | MUX_MODE4 */
+			0x1ac	0x4 /* rgmii2_td0 PIN_OUTPUT | MUX_MODE4 */
+			0x1b0	0x00040004 /* rgmii2_rclk PIN_INPUT | MUX_MODE4 */
+			0x1b4	0x00040004 /* rgmii2_rctl PIN_INPUT | MUX_MODE4 */
+			0x1b8	0x00040004 /* rgmii2_rd3 PIN_INPUT | MUX_MODE4 */
+			0x1bc	0x00040004 /* rgmii2_rd2 PIN_INPUT | MUX_MODE4 */
+			0x1c0	0x00040004 /* rgmii2_rd1 PIN_INPUT | MUX_MODE4 */
+			0x1c4	0x00040004 /* rgmii2_rd0 PIN_INPUT | MUX_MODE4 */
+		>;
+	};
+
+	davinci_mdio_default_pins: pinmux_davinci_mdio_default_pins {
+		pinctrl-single,pins = <
+			/* MDIO */
+			0x23c	0x30000 /* mdio_data PIN_OUTPUT_PULLUP | MUX_MODE0 */
+			0x240	0x70000 /* mdio_clk PIN_INPUT_PULLUP | MUX_MODE0 */
+			>;
+		};
+
 	qspi1_pins: pinmux_qspi1_pins {
 		pinctrl-single,pins = <
 			0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
@@ -332,6 +372,27 @@
 	cpu0-supply = <&smps123_reg>;
 };
 
+&gmac {
+	status="okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpsw_default_pins>;
+};
+
+&davinci_mdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&davinci_mdio_default_pins>;
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <2>;
+	phy-mode = "rgmii-txid";
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <3>;
+	phy-mode = "rgmii-txid";
+};
+
 &qspi {
 	status = "okay";
 	pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c29945e..daf7d36 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -763,6 +763,54 @@
 			status = "disabled";
 		};
 
+		gmac: ethernet@48484000 {
+			compatible = "ti,cpsw";
+			ti,hwmods = "gmac";
+			cpdma_channels = <8>;
+			ale_entries = <1024>;
+			bd_ram_size = <0x2000>;
+			no_bd_ram = <0>;
+			rx_descs = <64>;
+			mac_control = <0x20>;
+			slaves = <2>;
+			active_slave = <0>;
+			cpts_clock_mult = <0x80000000>;
+			cpts_clock_shift = <29>;
+			reg = <0x48484000 0x800
+				0x48485200 0x100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/*
+			 * rx_thresh_pend
+			 * rx_pend
+			 * tx_pend
+			 * misc_pend
+			 */
+			interrupts = <0 50 0x4>,
+					<0 51 0x4>,
+					<0 52 0x4>,
+					<0 53 0x4>;
+			ranges;
+			status = "disabled";
+
+			davinci_mdio: mdio@48485000 {
+				compatible = "ti,davinci_mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				ti,hwmods = "davinci_mdio";
+				bus_freq = <1000000>;
+				reg = <0x48485000 0x100>;
+			};
+
+			cpsw_emac0: slave@48484200 {
+				mac-address = [ 00 00 00 00 00 00 ];
+			};
+
+			cpsw_emac1: slave@48484300 {
+				mac-address = [ 00 00 00 00 00 00 ];
+			};
+		};
+
 		qspi: qspi@4b300000 {
 			compatible = "ti,dra7xxx-qspi";
 			reg = <0x4b300000 0x100>;
-- 
2.0.1

[PATCH 3/3] arm: dts: dra7: fixup qspi entry

[Sebastian Andrzej Siewior]

The core complains that the number 343 is too large. The older code has
here 124. This avoids the warning, the driver hasn't been tested.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
 arch/arm/boot/dts/dra7.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index daf7d36..1529bca 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -821,7 +821,7 @@
 			clocks = <&qspi_gfclk_div>;
 			clock-names = "fck";
 			num-cs = <4>;
-			interrupts = <0 343 0x4>;
+			interrupts = <0 124 0x4>;
 			status = "disabled";
 		};
 
-- 
2.0.1

Re: [PATCH 1/3] arm: dra7xx: Add hwmod data for MDIO and CPSW

[Tony Lindgren]

Hi,

Can you please check the comments below so we don't have to
add duplicate data just to remove it later on.

* Sebastian Andrzej Siewior <bigeasy@linutronix.de> [140708 11:43]:
> +
> +static struct omap_hwmod_irq_info dra7xx_gmac_irqs[] = {
> +	{ .name = "c0_rx_thresh_pend", .irq = 50 + DRA7XX_IRQ_GIC_START, },
> +	{ .name = "c0_rx_pend", .irq = 51 + DRA7XX_IRQ_GIC_START, },
> +	{ .name = "c0_tx_pend", .irq = 52 + DRA7XX_IRQ_GIC_START, },
> +	{ .name = "c0_misc_pend", .irq = 53 + DRA7XX_IRQ_GIC_START, },
> +	{ .irq = -1 },
> +};

Why do we need the interrupts here? They should be coming
from the .dts files? Is this numbering with or without
the crossbar?

> +static struct omap_hwmod_addr_space dra7xx_gmac_addr_space[] = {
> +	/* cpsw ss */
> +	{
> +		.pa_start	= 0x48484000,
> +		.pa_end	= 0x48484000 + SZ_2K - 1,
> +	},
> +	/* cpsw wr */
> +	{
> +		.pa_start	= 0x48485200,
> +		.pa_end	= 0x48485200 + SZ_256 - 1,
> +		.flags	= ADDR_TYPE_RT,
> +	},
> +	{ }
> +};

Also for the IO range, this should be coming from the .dts
files now?

> +static struct omap_hwmod_addr_space dra7xx_mdio_addr_space[] = {
> +	{
> +		.pa_start	= 0x48485000,
> +		.pa_end		= 0x48485000 + SZ_256 - 1,
> +	},
> +	{ }
> +};

Here too?

Regards,

Tony

Re: [PATCH 1/3] arm: dra7xx: Add hwmod data for MDIO and CPSW

[Mugunthan V N]

On Wednesday 09 July 2014 12:10 AM, Sebastian Andrzej Siewior wrote:
> Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Signed-off-by: Praveen Rao <prao@ti.com>
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> ---
>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 96 +++++++++++++++++++++++++++++++
>  1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 20b4398..0fa2c66 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1845,6 +1845,85 @@ static struct omap_hwmod dra7xx_vcp2_hwmod = {
>  };
>  
>  /*
> + * 'gmac' class
> + * cpsw/gmac sub system
> + */
> +static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
> +	.rev_offs	= 0x0,
> +	.sysc_offs	= 0x8,
> +	.syss_offs	= 0x4,
> +	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
> +			SYSS_HAS_RESET_STATUS),
> +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
> +			MSTANDBY_NO),
> +	.sysc_fields	= &omap_hwmod_sysc_type3,
> +};
> +
> +static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
> +	.name	= "gmac",
> +	.sysc	= &dra7xx_gmac_sysc,
> +};
> +
> +static struct omap_hwmod_irq_info dra7xx_gmac_irqs[] = {
> +	{ .name = "c0_rx_thresh_pend", .irq = 50 + DRA7XX_IRQ_GIC_START, },
> +	{ .name = "c0_rx_pend", .irq = 51 + DRA7XX_IRQ_GIC_START, },
> +	{ .name = "c0_tx_pend", .irq = 52 + DRA7XX_IRQ_GIC_START, },
> +	{ .name = "c0_misc_pend", .irq = 53 + DRA7XX_IRQ_GIC_START, },
> +	{ .irq = -1 },
> +};

This is not proper, NAK

Hwmod is already posted
http://www.spinics.net/lists/linux-omap/msg99039.html
and waiting for Acks and tested-by

Regards
Mugunthan V N

Re: [PATCH 2/3] arm: dts: dra7: Enable CPSW and MDIO for dra7xx EVM

[Mugunthan V N]

On Wednesday 09 July 2014 12:10 AM, Sebastian Andrzej Siewior wrote:
> From: Mugunthan V N <mugunthanvnm@ti.com>
>
> Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active
> and sleep states and enable them in board evm dts file.
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> [Resolved merge conflict and rebased on 3.8 kernel.
> Update the pinmux configuration for CPSW and MDIO by removing the
> macro definitons to match the 3.8 implementation.]
> Signed-off-by: Praveen Rao <prao@ti.com>
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> ---
>  arch/arm/boot/dts/dra7-evm.dts | 61 ++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/dra7.dtsi    | 48 +++++++++++++++++++++++++++++++++
>  2 files changed, 109 insertions(+)
>
> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
> index 4adc280..956a7bd 100644
> --- a/arch/arm/boot/dts/dra7-evm.dts
> +++ b/arch/arm/boot/dts/dra7-evm.dts
> @@ -94,6 +94,46 @@
>  		>;
>  	};
>  
> +	cpsw_default_pins: pinmux_cpsw_default_pins {
> +		pinctrl-single,pins = <
> +			/* Slave 1 */
> +			0x250	0x0 /* rgmii1_tclk PIN_OUTPUT | MUX_MODE0 */
> +			0x254	0x0 /* rgmii1_tctl PIN_OUTPUT | MUX_MODE0 */
> +			0x258	0x0 /* rgmii1_td3 PIN_OUTPUT | MUX_MODE0 */
> +			0x25c	0x0 /* rgmii1_td2 PIN_OUTPUT | MUX_MODE0 */
> +			0x260	0x0 /* rgmii1_td1 PIN_OUTPUT | MUX_MODE0 */
> +			0x264	0x0 /* rgmii1_td0 PIN_OUTPUT | MUX_MODE0 */
> +			0x268	0x00040000 /* rgmii1_rclk PIN_INPUT | MUX_MODE0 */
> +			0x26c	0x00040000 /* rgmii1_rctl PIN_INPUT | MUX_MODE0 */
> +			0x270	0x00040000 /* rgmii1_rd3 PIN_INPUT | MUX_MODE0 */
> +			0x274	0x00040000 /* rgmii1_rd2 PIN_INPUT | MUX_MODE0 */
> +			0x278	0x00040000 /* rgmii1_rd1 PIN_INPUT | MUX_MODE0 */
> +			0x27c	0x00040000 /* rgmii1_rd0 PIN_INPUT | MUX_MODE0 */
> +
> +			/* Slave 2 */
> +			0x198	0x4 /* rgmii2_tclk PIN_OUTPUT | MUX_MODE4 */
> +			0x19c	0x4 /* rgmii2_tctl PIN_OUTPUT | MUX_MODE4 */
> +			0x1a0	0x4 /* rgmii2_td3 PIN_OUTPUT | MUX_MODE4 */
> +			0x1a4	0x4 /* rgmii2_td2 PIN_OUTPUT | MUX_MODE4 */
> +			0x1a8	0x4 /* rgmii2_td1 PIN_OUTPUT | MUX_MODE4 */
> +			0x1ac	0x4 /* rgmii2_td0 PIN_OUTPUT | MUX_MODE4 */
> +			0x1b0	0x00040004 /* rgmii2_rclk PIN_INPUT | MUX_MODE4 */
> +			0x1b4	0x00040004 /* rgmii2_rctl PIN_INPUT | MUX_MODE4 */
> +			0x1b8	0x00040004 /* rgmii2_rd3 PIN_INPUT | MUX_MODE4 */
> +			0x1bc	0x00040004 /* rgmii2_rd2 PIN_INPUT | MUX_MODE4 */
> +			0x1c0	0x00040004 /* rgmii2_rd1 PIN_INPUT | MUX_MODE4 */
> +			0x1c4	0x00040004 /* rgmii2_rd0 PIN_INPUT | MUX_MODE4 */
> +		>;
> +	};
> +
> +	davinci_mdio_default_pins: pinmux_davinci_mdio_default_pins {
> +		pinctrl-single,pins = <
> +			/* MDIO */
> +			0x23c	0x30000 /* mdio_data PIN_OUTPUT_PULLUP | MUX_MODE0 */
> +			0x240	0x70000 /* mdio_clk PIN_INPUT_PULLUP | MUX_MODE0 */
> +			>;
> +		};
> +
>  	qspi1_pins: pinmux_qspi1_pins {
>  		pinctrl-single,pins = <
>  			0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
> @@ -332,6 +372,27 @@
>  	cpu0-supply = <&smps123_reg>;
>  };
>  
> +&gmac {
> +	status="okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cpsw_default_pins>;
> +};
> +
> +&davinci_mdio {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&davinci_mdio_default_pins>;
> +};
> +
> +&cpsw_emac0 {
> +	phy_id = <&davinci_mdio>, <2>;
> +	phy-mode = "rgmii-txid";
> +};
> +
> +&cpsw_emac1 {
> +	phy_id = <&davinci_mdio>, <3>;
> +	phy-mode = "rgmii-txid";
> +};
> +
>  &qspi {
>  	status = "okay";
>  	pinctrl-names = "default";
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index c29945e..daf7d36 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -763,6 +763,54 @@
>  			status = "disabled";
>  		};
>  
> +		gmac: ethernet@48484000 {
> +			compatible = "ti,cpsw";
> +			ti,hwmods = "gmac";
> +			cpdma_channels = <8>;
> +			ale_entries = <1024>;
> +			bd_ram_size = <0x2000>;
> +			no_bd_ram = <0>;
> +			rx_descs = <64>;
> +			mac_control = <0x20>;
> +			slaves = <2>;
> +			active_slave = <0>;
> +			cpts_clock_mult = <0x80000000>;
> +			cpts_clock_shift = <29>;
> +			reg = <0x48484000 0x800
> +				0x48485200 0x100>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			/*
> +			 * rx_thresh_pend
> +			 * rx_pend
> +			 * tx_pend
> +			 * misc_pend
> +			 */
> +			interrupts = <0 50 0x4>,
> +					<0 51 0x4>,
> +					<0 52 0x4>,
> +					<0 53 0x4>;

These interrupts are not correct, I have already posted and are waiting
for crossbar to be merged.
Hence NAK

Regards
Mugunthan V N

> +			ranges;
> +			status = "disabled";
> +
> +			davinci_mdio: mdio@48485000 {
> +				compatible = "ti,davinci_mdio";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				ti,hwmods = "davinci_mdio";
> +				bus_freq = <1000000>;
> +				reg = <0x48485000 0x100>;
> +			};
> +
> +			cpsw_emac0: slave@48484200 {
> +				mac-address = [ 00 00 00 00 00 00 ];
> +			};
> +
> +			cpsw_emac1: slave@48484300 {
> +				mac-address = [ 00 00 00 00 00 00 ];
> +			};
> +		};
> +
>  		qspi: qspi@4b300000 {
>  			compatible = "ti,dra7xxx-qspi";
>  			reg = <0x4b300000 0x100>;

Re: [PATCH 3/3] arm: dts: dra7: fixup qspi entry

[sourav]

Hi,

On Wednesday 09 July 2014 12:10 AM, Sebastian Andrzej Siewior wrote:
> The core complains that the number 343 is too large. The older code has
> here 124. This avoids the warning, the driver hasn't been tested.
>
> Signed-off-by: Sebastian Andrzej Siewior<bigeasy@linutronix.de>
> ---
>   arch/arm/boot/dts/dra7.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index daf7d36..1529bca 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -821,7 +821,7 @@
>   			clocks =<&qspi_gfclk_div>;
>   			clock-names = "fck";
>   			num-cs =<4>;
> -			interrupts =<0 343 0x4>;
> +			interrupts =<0 124 0x4>;
>   			status = "disabled";
>   		};
>

The number is correct and is complaining just because the crossbar stuff 
is not
put in. I had already posted a patch[1] to remove interrupt binding as 
of now.

Hence, NAK for this patch.

[1]: https://patchwork.kernel.org/patch/4364341/

Re: [PATCH 3/3] arm: dts: dra7: fixup qspi entry

[Sebastian Andrzej Siewior]

On 07/09/2014 12:07 PM, sourav wrote:
> Hi,

Hello, Sourav,

> The number is correct and is complaining just because the crossbar stuff
> is not
> put in. I had already posted a patch[1] to remove interrupt binding as
> of now.
> 
> Hence, NAK for this patch.

Thank you for explanation. What is the status on the crossbar stuff? Is
this comming any time soon? It seems that it is also stalling the
networking pieces.

> 
> [1]: https://patchwork.kernel.org/patch/4364341/

Sebastian

Re: [PATCH 3/3] arm: dts: dra7: fixup qspi entry

[Tony Lindgren]

* Sebastian Andrzej Siewior <bigeasy@linutronix.de> [140709 03:20]:
> On 07/09/2014 12:07 PM, sourav wrote:
> > Hi,
> 
> Hello, Sourav,
> 
> > The number is correct and is complaining just because the crossbar stuff
> > is not
> > put in. I had already posted a patch[1] to remove interrupt binding as
> > of now.
> > 
> > Hence, NAK for this patch.
> 
> Thank you for explanation. What is the status on the crossbar stuff? Is
> this comming any time soon? It seems that it is also stalling the
> networking pieces.

The drivers/irqchip related fixes are queued into linux next,
and I'm planning to queue the dts related changes for v3.17.

I might have the crossbar stuff in omap-for-v3.17/dt at some
point today.

Regards,

Tony

> > [1]: https://patchwork.kernel.org/patch/4364341/