From: Thierry Reding <thierry.reding@gmail.com>
To: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Viresh Kumar <viresh.kumar@linaro.org>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
Stephen Warren <swarren@wwwdotorg.org>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH 12/13] cpufreq: Add cpufreq driver for Tegra124
Date: Fri, 11 Jul 2014 17:15:02 +0200 [thread overview]
Message-ID: <20140711151501.GA25810@ulmo> (raw)
In-Reply-To: <53BFFEAD.7000405@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 742 bytes --]
On Fri, Jul 11, 2014 at 06:11:41PM +0300, Tuomas Tynkkynen wrote:
> On 11/07/14 17:57, Thierry Reding wrote:
>
> >>I don't think that's going to work? The voltage scaling is handled in hw.
> >
> >Do we have to handle it in hardware or can we opt to do it in software,
> >too?
> >
>
> With the PLLX, voltage scaling is done entirely in SW. With the DFLL,
> it's possible to stay in open-loop mode and do it in SW, but there's
> not much point in that.
It's kind of ugly how we need to pass the address of the PMU and the
offset of the voltage control register to the DFLL which will then
initiate I2C transactions itself. I'm wondering if that plays well with
the I2C traffic originating from within the kernel.
Thierry
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next prev parent reply other threads:[~2014-07-11 15:15 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-10 21:42 [PATCH 00/13] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 01/13] clk: tegra: Add binding for the Tegra124 DFLL clocksource Tuomas Tynkkynen
2014-07-11 16:28 ` Andrew Bresticker
[not found] ` <CAL1qeaFF0ZpUFovxTuLXrBPRg2Lbf-754Z=ztD5HFZPbfnDsAw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-07-11 16:48 ` Tuomas Tynkkynen
2014-07-11 17:08 ` Andrew Bresticker
[not found] ` <CAL1qeaHETQ7kSGNjPiwi_9WNMtr9qZp0KwjZCCxY29+_N4AcuA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-07-11 17:21 ` Tuomas Tynkkynen
2014-07-14 8:38 ` Thierry Reding
2014-07-14 9:12 ` Mark Brown
[not found] ` <20140714091233.GC6800-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2014-07-14 9:24 ` Thierry Reding
2014-07-14 10:22 ` Mark Brown
2014-07-15 20:23 ` Tuomas Tynkkynen
[not found] ` <53C58DCB.90502-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-07-15 22:52 ` Mark Brown
2014-07-16 8:01 ` Thierry Reding
2014-07-16 11:00 ` Mark Brown
2014-07-10 21:42 ` [PATCH 02/13] clk: tegra: Add library for the DFLL clock source (open-loop mode) Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 03/13] clk: tegra: Add closed loop support for the DFLL Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 04/13] clk: tegra: Add functions for parsing CVB tables Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 05/13] clk: tegra: Add DFLL DVCO reset control for Tegra124 Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 06/13] clk: tegra: Add Tegra124 DFLL clocksource platform driver Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 07/13] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 08/13] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 09/13] ARM: tegra: Add the DFLL to Tegra124 device tree Tuomas Tynkkynen
[not found] ` <1405028569-14253-1-git-send-email-ttynkkynen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-07-10 21:42 ` [PATCH 10/13] ARM: tegra: Enable the DFLL on the Jetson TK1 Tuomas Tynkkynen
2014-07-11 7:14 ` Mikko Perttunen
2014-07-10 21:42 ` [PATCH 12/13] cpufreq: Add cpufreq driver for Tegra124 Tuomas Tynkkynen
[not found] ` <1405028569-14253-13-git-send-email-ttynkkynen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-07-11 4:35 ` Viresh Kumar
[not found] ` <CAKohpom9ORXFiUU4=V+CxgN0ZOFLMEhEjHiU8HsYUYDybNXgHQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-07-11 9:12 ` Peter De Schrijver
2014-07-11 9:14 ` Viresh Kumar
[not found] ` <20140711091207.GY23218-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2014-07-11 14:57 ` Thierry Reding
2014-07-11 15:11 ` Tuomas Tynkkynen
2014-07-11 15:15 ` Thierry Reding [this message]
2014-07-11 15:29 ` Tuomas Tynkkynen
[not found] ` <53C002BE.90805-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-07-11 16:33 ` Andrew Bresticker
2014-07-11 14:14 ` Tuomas Tynkkynen
[not found] ` <53BFF132.3020700-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-07-11 14:37 ` Viresh Kumar
2014-07-11 15:32 ` [PATCH 00/13] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq Mike Turquette
2014-07-10 21:42 ` [PATCH 11/13] cpufreq: tegra124: Add device tree bindings Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 13/13] ARM: tegra: Add entries for cpufreq on Tegra124 Tuomas Tynkkynen
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