[PATCH v4 0/6] ARM: sun8i: Support A23 PRCM clock and reset controllers

[PATCH v4 0/6] ARM: sun8i: Support A23 PRCM clock and reset controllers

[Chen-Yu Tsai]

Hi everyone,

This is PRCM subset v4 of the sun8i A23 bring-up series. This subset
includes clock and reset controller support for the PRCM (power,
reset and clock module) on the A23 SoC. It is based on my previous
series for basic sun8i A23 clocks [1].

Patch 1 modifies tha sun6i-a31-apb0-gates driver to use a bitmap
to denote valid gate indices, instead of just counting "clock-names"
from the DT possibly with "clock-indicies". This makes the driver
consistent with the other sunxi clock gate drivers.

Patch 2 adds the A23 variant of apb0-gates, with A23 specific
compatible and bitmap.

Patch 3 adds support for A23's PRCM to the sun6i-prcm driver.
The difference between the A23 and the A31 regarding the PRCM block
is 2 clock muxes were removed, a divider clock has slightly difference
dividers, and some clock gates are gone. The resources used are
unchanged. Drivers for the 2 clock muxes are replaced with fixed-factor
clocks in the DT. So the A23 variant is supported with the sun6i-prcm
driver with a slightly different sub-device list.

Patch 4 adds optional reset control support to the 8250_dw, which
is used by sun6i and sun8i platforms. Till now, this wasn't needed
from a working standpoint, as the bootloader de-asserts the reset
control on the console UART for us. However, during the development
of the sun8i patches, I noticed other UARTs wouldn't work. Also the
new sun6i A31 Hummingbird has multiple UARTs available, which would
require this patch.

Patch 5 adds deferred probing to 8250_dw. In my case, even though
the clocks and reset controller "devices" were registered before
the UART, the 8250_dw driver binded with the UART devices before
the clocks and resets were available. This resulted in the 8250_dw
driver failing. I only tested the R_UART device.

Strictly speaking it won't be needed once pinctrl support is added,
as the driver core handles deferred probing for pinctrl phandles,
and the pinctrl device for the R_UART is probed after it. However
it may be required for the A31 Hummingbird development board.

Patch 6 adds the PRCM nodes, and the associated clock/reset phandles,
to the sun8i DTSI.

These patches can go through their separate trees. There are no
compile time dependencies between them.

Related changes since v3:

  - Dropped patches already merged by Maxime
  - Used bitmaps to denote possible gate indicies in sun6i-a31-apb0-gates,
    and added A23 variant
  - Added Maxime's Acked-by for
    'mfd: sun6i-prcm: Add support for Allwinner A23 PRCM'

Related changes since v2:

  - Add separate driver for sun8i-a23-apb0-clk
  - Use sun6i-a31-clock-reset for ahb1_rst

Related changes since v1:

  - Add sun8i-a23-apb0-gates-clk compatible to sun6i-a31-apb0-gates-clk


Cheers
ChenYu


  [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/266990.html

Chen-Yu Tsai (6):
  clk: sunxi: sun6i-apb0-gates: use bitmaps for valid gate indicies
  clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 support
  mfd: sun6i-prcm: Add support for Allwinner A23 PRCM
  serial: 8250_dw: Add optional reset control support
  serial: 8250_dw: Add support for deferred probing
  ARM: sun8i: Add PRCM clock and reset controller nodes to the DTSI

 Documentation/devicetree/bindings/clock/sunxi.txt  |  1 +
 .../devicetree/bindings/mfd/sun6i-prcm.txt         |  2 +-
 .../bindings/serial/snps-dw-apb-uart.txt           |  1 +
 arch/arm/boot/dts/sun8i-a23.dtsi                   | 47 ++++++++++++-
 drivers/clk/sunxi/clk-sun6i-apb0-gates.c           | 80 ++++++++++++----------
 drivers/mfd/sun6i-prcm.c                           | 30 ++++++++
 drivers/tty/serial/8250/8250_dw.c                  | 13 ++++
 7 files changed, 136 insertions(+), 38 deletions(-)

-- 
2.0.1

[PATCH v4 1/6] clk: sunxi: sun6i-apb0-gates: use bitmaps for valid gate indicies

[Chen-Yu Tsai]

sun6i-apb0-gates uses the "clock-indices" DT property to indicate
valid gate bits or holes in between. However, the rest of sunxi
clock drivers use bitmaps for this purpose.

This patch modifies sun6i-apb0-gates to use bitmaps as well, to be
consistent with the sunxi platform. Also add the missing call to
clk_register_clkdev, so system clock lookups will work.

Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
 drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 75 +++++++++++++++++---------------
 1 file changed, 39 insertions(+), 36 deletions(-)

diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
index b342f2a..3bd8357 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
@@ -9,24 +9,48 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/clkdev.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 
 #define SUN6I_APB0_GATES_MAX_SIZE	32
 
+struct gates_data {
+	DECLARE_BITMAP(mask, SUN6I_APB0_GATES_MAX_SIZE);
+};
+
+static const struct gates_data sun6i_a31_apb0_gates __initconst = {
+	.mask = {0x7F},
+};
+
+const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
+	{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
+	{ /* sentinel */ }
+};
+
 static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
 	struct clk_onecell_data *clk_data;
+	const struct of_device_id *device;
+	const struct gates_data *data;
 	const char *clk_parent;
 	const char *clk_name;
 	struct resource *r;
 	void __iomem *reg;
-	int gate_id;
 	int ngates;
-	int gate_max = 0;
 	int i;
+	int j = 0;
+
+	if (!np)
+		return -ENODEV;
+
+	device = of_match_device(sun6i_a31_apb0_gates_clk_dt_ids, &pdev->dev);
+	if (!device)
+		return -ENODEV;
+	data = device->data;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	reg = devm_ioremap_resource(&pdev->dev, r);
@@ -37,57 +61,36 @@ static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
 	if (!clk_parent)
 		return -EINVAL;
 
-	ngates = of_property_count_strings(np, "clock-output-names");
-	if (ngates < 0)
-		return ngates;
-
-	if (!ngates || ngates > SUN6I_APB0_GATES_MAX_SIZE)
-		return -EINVAL;
-
 	clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
 				GFP_KERNEL);
 	if (!clk_data)
 		return -ENOMEM;
 
-	clk_data->clks = devm_kzalloc(&pdev->dev,
-				      SUN6I_APB0_GATES_MAX_SIZE *
-				      sizeof(struct clk *),
-				      GFP_KERNEL);
+	/* Worst-case size approximation and memory allocation */
+	ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE);
+	clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1),
+				      sizeof(struct clk *), GFP_KERNEL);
 	if (!clk_data->clks)
 		return -ENOMEM;
 
-	for (i = 0; i < ngates; i++) {
+	for_each_set_bit(i, data->mask, SUN6I_APB0_GATES_MAX_SIZE) {
 		of_property_read_string_index(np, "clock-output-names",
-					      i, &clk_name);
-
-		gate_id = i;
-		of_property_read_u32_index(np, "clock-indices", i, &gate_id);
-
-		WARN_ON(gate_id >= SUN6I_APB0_GATES_MAX_SIZE);
-		if (gate_id >= SUN6I_APB0_GATES_MAX_SIZE)
-			continue;
+					      j, &clk_name);
 
-		clk_data->clks[gate_id] = clk_register_gate(&pdev->dev,
-							    clk_name,
-							    clk_parent, 0,
-							    reg, gate_id,
-							    0, NULL);
-		WARN_ON(IS_ERR(clk_data->clks[gate_id]));
+		clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
+						      clk_parent, 0, reg, i,
+						      0, NULL);
+		WARN_ON(IS_ERR(clk_data->clks[i]));
+		clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
 
-		if (gate_id > gate_max)
-			gate_max = gate_id;
+		j++;
 	}
 
-	clk_data->clk_num = gate_max + 1;
+	clk_data->clk_num = ngates + 1;
 
 	return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
 }
 
-const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
-	{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk" },
-	{ /* sentinel */ }
-};
-
 static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
 	.driver = {
 		.name = "sun6i-a31-apb0-gates-clk",
-- 
2.0.1

Re: [PATCH v4 1/6] clk: sunxi: sun6i-apb0-gates: use bitmaps for valid gate indicies

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 702 bytes --]

Hi,

On Wed, Jul 09, 2014 at 03:54:34PM +0800, Chen-Yu Tsai wrote:
> sun6i-apb0-gates uses the "clock-indices" DT property to indicate
> valid gate bits or holes in between. However, the rest of sunxi
> clock drivers use bitmaps for this purpose.
> 
> This patch modifies sun6i-apb0-gates to use bitmaps as well, to be
> consistent with the sunxi platform. Also add the missing call to
> clk_register_clkdev, so system clock lookups will work.
> 
> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

Applied, and fixed the typo in the title.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[PATCH v4 2/6] clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 support

[Chen-Yu Tsai]

This patch adds "allwinner,sun8i-a23-apb0-gates-clk", a A23 specific
compatible to the sun6i-a31-apb0-gates clock driver, along with the
gate bitmap.

Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-sun6i-apb0-gates.c          | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 68dbd3d..d3a5c3c 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -34,6 +34,7 @@ Required properties:
 	"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
 	"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
 	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
+	"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
 	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
 	"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
 	"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
index 3bd8357..551f220 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
@@ -25,8 +25,13 @@ static const struct gates_data sun6i_a31_apb0_gates __initconst = {
 	.mask = {0x7F},
 };
 
+static const struct gates_data sun8i_a23_apb0_gates __initconst = {
+	.mask = {0x5D},
+};
+
 const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
+	{ .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
 	{ /* sentinel */ }
 };
 
-- 
2.0.1

Re: [PATCH v4 2/6] clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 436 bytes --]

On Wed, Jul 09, 2014 at 03:54:35PM +0800, Chen-Yu Tsai wrote:
> This patch adds "allwinner,sun8i-a23-apb0-gates-clk", a A23 specific
> compatible to the sun6i-a31-apb0-gates clock driver, along with the
> gate bitmap.
> 
> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

Applied, thanks.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[PATCH v4 3/6] mfd: sun6i-prcm: Add support for Allwinner A23 PRCM

[Chen-Yu Tsai]

The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
The differences are the AR100 clock can no longer be modified,
the APB0 clock has different divisors, and some clock gates are
gone.

This patch adds a compatible with a modified subdevice list for
the A23.

Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 .../devicetree/bindings/mfd/sun6i-prcm.txt         |  2 +-
 drivers/mfd/sun6i-prcm.c                           | 30 ++++++++++++++++++++++
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt b/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt
index 1f5a31f..03c5a55 100644
--- a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt
+++ b/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt
@@ -4,7 +4,7 @@ PRCM is an MFD device exposing several Power Management related devices
 (like clks and reset controllers).
 
 Required properties:
- - compatible: "allwinner,sun6i-a31-prcm"
+ - compatible: "allwinner,sun6i-a31-prcm" or "allwinner,sun8i-a23-prcm"
  - reg: The PRCM registers range
 
 The prcm node may contain several subdevices definitions:
diff --git a/drivers/mfd/sun6i-prcm.c b/drivers/mfd/sun6i-prcm.c
index 718fc4d..283ab8d 100644
--- a/drivers/mfd/sun6i-prcm.c
+++ b/drivers/mfd/sun6i-prcm.c
@@ -76,16 +76,46 @@ static const struct mfd_cell sun6i_a31_prcm_subdevs[] = {
 	},
 };
 
+static const struct mfd_cell sun8i_a23_prcm_subdevs[] = {
+	{
+		.name = "sun8i-a23-apb0-clk",
+		.of_compatible = "allwinner,sun8i-a23-apb0-clk",
+		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_clk_res),
+		.resources = sun6i_a31_apb0_clk_res,
+	},
+	{
+		.name = "sun6i-a31-apb0-gates-clk",
+		.of_compatible = "allwinner,sun8i-a23-apb0-gates-clk",
+		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_gates_clk_res),
+		.resources = sun6i_a31_apb0_gates_clk_res,
+	},
+	{
+		.name = "sun6i-a31-apb0-clock-reset",
+		.of_compatible = "allwinner,sun6i-a31-clock-reset",
+		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
+		.resources = sun6i_a31_apb0_rstc_res,
+	},
+};
+
 static const struct prcm_data sun6i_a31_prcm_data = {
 	.nsubdevs = ARRAY_SIZE(sun6i_a31_prcm_subdevs),
 	.subdevs = sun6i_a31_prcm_subdevs,
 };
 
+static const struct prcm_data sun8i_a23_prcm_data = {
+	.nsubdevs = ARRAY_SIZE(sun8i_a23_prcm_subdevs),
+	.subdevs = sun8i_a23_prcm_subdevs,
+};
+
 static const struct of_device_id sun6i_prcm_dt_ids[] = {
 	{
 		.compatible = "allwinner,sun6i-a31-prcm",
 		.data = &sun6i_a31_prcm_data,
 	},
+	{
+		.compatible = "allwinner,sun8i-a23-prcm",
+		.data = &sun8i_a23_prcm_data,
+	},
 	{ /* sentinel */ },
 };
 
-- 
2.0.1

Re: [PATCH v4 3/6] mfd: sun6i-prcm: Add support for Allwinner A23 PRCM

[Lee Jones]

On Wed, 09 Jul 2014, Chen-Yu Tsai wrote:

> The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
> The differences are the AR100 clock can no longer be modified,
> the APB0 clock has different divisors, and some clock gates are
> gone.
> 
> This patch adds a compatible with a modified subdevice list for
> the A23.
> 
> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
>  .../devicetree/bindings/mfd/sun6i-prcm.txt         |  2 +-
>  drivers/mfd/sun6i-prcm.c                           | 30 ++++++++++++++++++++++
>  2 files changed, 31 insertions(+), 1 deletion(-)

Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

-- 
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Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

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Re: [PATCH v4 3/6] mfd: sun6i-prcm: Add support for Allwinner A23 PRCM

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1146 bytes --]

Hi Lee,

On Thu, Jul 10, 2014 at 10:37:07AM +0100, Lee Jones wrote:
> On Wed, 09 Jul 2014, Chen-Yu Tsai wrote:
> 
> > The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
> > The differences are the AR100 clock can no longer be modified,
> > the APB0 clock has different divisors, and some clock gates are
> > gone.
> > 
> > This patch adds a compatible with a modified subdevice list for
> > the A23.
> > 
> > Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> > Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> > ---
> >  .../devicetree/bindings/mfd/sun6i-prcm.txt         |  2 +-
> >  drivers/mfd/sun6i-prcm.c                           | 30 ++++++++++++++++++++++
> >  2 files changed, 31 insertions(+), 1 deletion(-)
> 
> Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

We don't have any dependency on this driver, so it would be simpler if
you could just take it through your tree I guess.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH v4 3/6] mfd: sun6i-prcm: Add support for Allwinner A23 PRCM

[Lee Jones]

On Tue, 15 Jul 2014, Maxime Ripard wrote:

> Hi Lee,
> 
> On Thu, Jul 10, 2014 at 10:37:07AM +0100, Lee Jones wrote:
> > On Wed, 09 Jul 2014, Chen-Yu Tsai wrote:
> > 
> > > The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
> > > The differences are the AR100 clock can no longer be modified,
> > > the APB0 clock has different divisors, and some clock gates are
> > > gone.
> > > 
> > > This patch adds a compatible with a modified subdevice list for
> > > the A23.
> > > 
> > > Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> > > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > > ---
> > >  .../devicetree/bindings/mfd/sun6i-prcm.txt         |  2 +-
> > >  drivers/mfd/sun6i-prcm.c                           | 30 ++++++++++++++++++++++
> > >  2 files changed, 31 insertions(+), 1 deletion(-)
> > 
> > Acked-by: Lee Jones <lee.jones@linaro.org>
> 
> We don't have any dependency on this driver, so it would be simpler if
> you could just take it through your tree I guess.

Verll well, applied thanks.



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[PATCH v4 4/6] serial: 8250_dw: Add optional reset control support

[Chen-Yu Tsai]

The Allwinner A31 and A23 SoCs have a reset controller
maintaining the UART in reset by default.

This patch adds optional reset support to the driver.

Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt | 1 +
 drivers/tty/serial/8250/8250_dw.c                             | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
index f13f1c5..cb9af84 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
@@ -7,6 +7,7 @@ Required properties:
 - clock-frequency : the input clock frequency for the UART.
 
 Optional properties:
+- resets : phandle to the parent reset controller.
 - reg-shift : quantity to shift the register offsets by.  If this property is
   not present then the register offsets are not shifted.
 - reg-io-width : the size (in bytes) of the IO accesses that should be
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 51b307a..cb1b3dc 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -26,6 +26,7 @@
 #include <linux/slab.h>
 #include <linux/acpi.h>
 #include <linux/clk.h>
+#include <linux/reset.h>
 #include <linux/pm_runtime.h>
 
 #include <asm/byteorder.h>
@@ -59,6 +60,7 @@ struct dw8250_data {
 	int			last_mcr;
 	int			line;
 	struct clk		*clk;
+	struct reset_control	*rst;
 	struct uart_8250_dma	dma;
 };
 
@@ -408,6 +410,10 @@ static int dw8250_probe(struct platform_device *pdev)
 		uart.port.uartclk = clk_get_rate(data->clk);
 	}
 
+	data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
+	if (!IS_ERR(data->rst))
+		reset_control_deassert(data->rst);
+
 	data->dma.rx_chan_id = -1;
 	data->dma.tx_chan_id = -1;
 	data->dma.rx_param = data;
@@ -451,6 +457,9 @@ static int dw8250_remove(struct platform_device *pdev)
 
 	serial8250_unregister_port(data->line);
 
+	if (!IS_ERR(data->rst))
+		reset_control_assert(data->rst);
+
 	if (!IS_ERR(data->clk))
 		clk_disable_unprepare(data->clk);
 
-- 
2.0.1

[PATCH v4 5/6] serial: 8250_dw: Add support for deferred probing

[Chen-Yu Tsai]

The 8250_dw driver fails to probe if the specified clock isn't
registered at probe time. Even if a clock frequency is given,
the required clock might be gated because it wasn't properly
enabled.

This happened to me when the device is registered through DT,
and the clock was part of an MFD, the PRCM found on A31 and A23
SoCs. Unlike core clocks that are registered with OF_CLK_DECLARE,
which happen almost immediately after the kernel starts, the
clocks are registered as sub-devices of the PRCM MFD platform
device. Even though devices are registered in the order they are
found in the DT, the drivers are registered in a different,
arbitrary order. It is possible that the 8250_dw driver is
registered, and thus associated with the device and probed, before
the clock driver is registered and probed.

8250_dw then reports unable to get the clock, and fails. Without
a working console, the kernel panics.

This patch adds support for deferred probe handling for the clock
and reset controller.

Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
 drivers/tty/serial/8250/8250_dw.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index cb1b3dc..d9eeed7 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -405,12 +405,16 @@ static int dw8250_probe(struct platform_device *pdev)
 
 	data->usr_reg = DW_UART_USR;
 	data->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
+		return -EPROBE_DEFER;
 	if (!IS_ERR(data->clk)) {
 		clk_prepare_enable(data->clk);
 		uart.port.uartclk = clk_get_rate(data->clk);
 	}
 
 	data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
+	if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER)
+		return -EPROBE_DEFER;
 	if (!IS_ERR(data->rst))
 		reset_control_deassert(data->rst);
 
-- 
2.0.1

Re: [PATCH v4 5/6] serial: 8250_dw: Add support for deferred probing

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1420 bytes --]

On Wed, Jul 09, 2014 at 03:54:38PM +0800, Chen-Yu Tsai wrote:
> The 8250_dw driver fails to probe if the specified clock isn't
> registered at probe time. Even if a clock frequency is given,
> the required clock might be gated because it wasn't properly
> enabled.
> 
> This happened to me when the device is registered through DT,
> and the clock was part of an MFD, the PRCM found on A31 and A23
> SoCs. Unlike core clocks that are registered with OF_CLK_DECLARE,
> which happen almost immediately after the kernel starts, the
> clocks are registered as sub-devices of the PRCM MFD platform
> device. Even though devices are registered in the order they are
> found in the DT, the drivers are registered in a different,
> arbitrary order. It is possible that the 8250_dw driver is
> registered, and thus associated with the device and probed, before
> the clock driver is registered and probed.
> 
> 8250_dw then reports unable to get the clock, and fails. Without
> a working console, the kernel panics.
> 
> This patch adds support for deferred probe handling for the clock
> and reset controller.
> 
> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[PATCH v4 6/6] ARM: sun8i: Add PRCM clock and reset controller nodes to the DTSI

[Chen-Yu Tsai]

With sun8i PRCM support available, we can add the PRCM clock and
reset controller nodes to the DTSI. Also update R_UART's clock
phandle and add it's reset control phandle.

Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
 arch/arm/boot/dts/sun8i-a23.dtsi | 47 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 886776d..54ac0787 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -285,13 +285,58 @@
 			interrupts = <1 9 0xf04>;
 		};
 
+		prcm@01f01400 {
+			compatible = "allwinner,sun8i-a23-prcm";
+			reg = <0x01f01400 0x200>;
+
+			ar100: ar100_clk {
+				compatible = "fixed-factor-clock";
+				#clock-cells = <0>;
+				clock-div = <1>;
+				clock-mult = <1>;
+				clocks = <&osc24M>;
+				clock-output-names = "ar100";
+			};
+
+			ahb0: ahb0_clk {
+				compatible = "fixed-factor-clock";
+				#clock-cells = <0>;
+				clock-div = <1>;
+				clock-mult = <1>;
+				clocks = <&ar100>;
+				clock-output-names = "ahb0";
+			};
+
+			apb0: apb0_clk {
+				compatible = "allwinner,sun8i-a23-apb0-clk";
+				#clock-cells = <0>;
+				clocks = <&ahb0>;
+				clock-output-names = "apb0";
+			};
+
+			apb0_gates: apb0_gates_clk {
+				compatible = "allwinner,sun8i-a23-apb0-gates-clk";
+				#clock-cells = <1>;
+				clocks = <&apb0>;
+				clock-output-names = "apb0_pio", "apb0_timer",
+						"apb0_rsb", "apb0_uart",
+						"apb0_i2c";
+			};
+
+			apb0_rst: apb0_rst {
+				compatible = "allwinner,sun6i-a31-clock-reset";
+				#reset-cells = <1>;
+			};
+		};
+
 		r_uart: serial@01f02800 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01f02800 0x400>;
 			interrupts = <0 38 4>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&osc24M>;
+			clocks = <&apb0_gates 4>;
+			resets = <&apb0_rst 4>;
 			status = "disabled";
 		};
 	};
-- 
2.0.1

Re: [PATCH v4 6/6] ARM: sun8i: Add PRCM clock and reset controller nodes to the DTSI

[fireescapefire-Re5JQEeQqe8AvxtiuMwx3w]

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Hi!

I'm trying to get up to speed with everyone [ mostly Chen-Yu's ] work on 
the a23; I just got an "azpen a727".  Maybe this is a bit off thread, but 
I'd really like to get a response...

Maybe there is more/relevant information on linux-sunxi.org, but it seems 
to be down tonight.

Regardless, on fresh a pull of wens's u-boot-sunxi repo, 
```
$ make sun8i_config  
```
yeilds nothing on any branch other than lichee-dev-a23... 

... and lichee-dev-a23's config is looking for a relative path for the 
toolchain, i think that's what autoconf means by ".../gcc-linaro/!$#@$-gcc: 
no such file or !@#%"  

sun4i and sun5i work or wens's repo...  I haven't tried anything in a 
subfolder of origin from linux-sunxi's repo...

Is everyone on the working with same toolchain repo in ~?  [ maybe thats on 
linux-sunxi.org ]  Is this all I should need to current build u-boot.bin 
for a23?

I've only worked on well supported / figured out already hardware before 
and it's also likely I'm missing more basic uboot board config details, so 
I greatly appreciate any time, feedback, and guidance.
I can't wait to help!, and consider this documentation which I'm totally 
happy to wiki when its up again.

Best,

Ed


On Wednesday, July 9, 2014 3:54:50 AM UTC-4, Chen-Yu Tsai wrote:
>
> With sun8i PRCM support available, we can add the PRCM clock and 
> reset controller nodes to the DTSI. Also update R_UART's clock 
> phandle and add it's reset control phandle. 
>
> Signed-off-by: Chen-Yu Tsai <we...-jdAy2FN1RRM@public.gmane.org <javascript:>> 
> --- 
>  arch/arm/boot/dts/sun8i-a23.dtsi | 47 
> +++++++++++++++++++++++++++++++++++++++- 
>  1 file changed, 46 insertions(+), 1 deletion(-) 
>
> diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi 
> b/arch/arm/boot/dts/sun8i-a23.dtsi 
> index 886776d..54ac0787 100644 
> --- a/arch/arm/boot/dts/sun8i-a23.dtsi 
> +++ b/arch/arm/boot/dts/sun8i-a23.dtsi 
> @@ -285,13 +285,58 @@ 
>                          interrupts = <1 9 0xf04>; 
>                  }; 
>   
> +                prcm@01f01400 { 
> +                        compatible = "allwinner,sun8i-a23-prcm"; 
> +                        reg = <0x01f01400 0x200>; 
> + 
> +                        ar100: ar100_clk { 
> +                                compatible = "fixed-factor-clock"; 
> +                                #clock-cells = <0>; 
> +                                clock-div = <1>; 
> +                                clock-mult = <1>; 
> +                                clocks = <&osc24M>; 
> +                                clock-output-names = "ar100"; 
> +                        }; 
> + 
> +                        ahb0: ahb0_clk { 
> +                                compatible = "fixed-factor-clock"; 
> +                                #clock-cells = <0>; 
> +                                clock-div = <1>; 
> +                                clock-mult = <1>; 
> +                                clocks = <&ar100>; 
> +                                clock-output-names = "ahb0"; 
> +                        }; 
> + 
> +                        apb0: apb0_clk { 
> +                                compatible = 
> "allwinner,sun8i-a23-apb0-clk"; 
> +                                #clock-cells = <0>; 
> +                                clocks = <&ahb0>; 
> +                                clock-output-names = "apb0"; 
> +                        }; 
> + 
> +                        apb0_gates: apb0_gates_clk { 
> +                                compatible = 
> "allwinner,sun8i-a23-apb0-gates-clk"; 
> +                                #clock-cells = <1>; 
> +                                clocks = <&apb0>; 
> +                                clock-output-names = "apb0_pio", 
> "apb0_timer", 
> +                                                "apb0_rsb", "apb0_uart", 
> +                                                "apb0_i2c"; 
> +                        }; 
> + 
> +                        apb0_rst: apb0_rst { 
> +                                compatible = 
> "allwinner,sun6i-a31-clock-reset"; 
> +                                #reset-cells = <1>; 
> +                        }; 
> +                }; 
> + 
>                  r_uart: serial@01f02800 { 
>                          compatible = "snps,dw-apb-uart"; 
>                          reg = <0x01f02800 0x400>; 
>                          interrupts = <0 38 4>; 
>                          reg-shift = <2>; 
>                          reg-io-width = <4>; 
> -                        clocks = <&osc24M>; 
> +                        clocks = <&apb0_gates 4>; 
> +                        resets = <&apb0_rst 4>; 
>                          status = "disabled"; 
>                  }; 
>          }; 
> -- 
> 2.0.1 
>
>

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Re: [PATCH v4 6/6] ARM: sun8i: Add PRCM clock and reset controller nodes to the DTSI

[Maxime Ripard]

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On Wed, Jul 09, 2014 at 03:54:39PM +0800, Chen-Yu Tsai wrote:
> With sun8i PRCM support available, we can add the PRCM clock and
> reset controller nodes to the DTSI. Also update R_UART's clock
> phandle and add it's reset control phandle.
> 
> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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