* [RESEND PATCH 1/8] ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock
2014-07-14 10:42 [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data Kishon Vijay Abraham I
@ 2014-07-14 10:42 ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 2/8] ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I
` (6 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-14 10:42 UTC (permalink / raw)
To: linux-kernel, tony, devicetree, linux-arm-kernel, linux-omap
Cc: kishon, Keerthy, Rajendra Nayak, Tero Kristo, Paul Walmsley
From: Keerthy <j-keerthy@ti.com>
Add divider table to optfclk_pciephy_div clock. The 8th bit of
CM_CLKMODE_APLL_PCIE can be programmed to either 0x0 or 0x1
based on if the divider value is 0x2 or 0x1.
Figure 26-21. PCIe PHY Clock Generator Overview in vE of DRA7xx ES1.0 shows the
block diagram of Clock Generator Subsystem of PCIe PHY module. The divider
value if '1' should be programmed in order to get the correct
PCIE_PHY_DIV_GCLK frequency (2.5GHz).
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index b03cfe4..7148e7c 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1170,6 +1170,7 @@
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x021c>;
+ ti,dividers = <2>, <1>;
ti,bit-shift = <8>;
ti,max-div = <2>;
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [RESEND PATCH 2/8] ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
2014-07-14 10:42 [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 1/8] ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock Kishon Vijay Abraham I
@ 2014-07-14 10:42 ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 3/8] ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY Kishon Vijay Abraham I
` (5 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-14 10:42 UTC (permalink / raw)
To: linux-kernel, tony, devicetree, linux-arm-kernel, linux-omap
Cc: kishon, Keerthy, Rajendra Nayak, Tero Kristo, Paul Walmsley
From: Keerthy <j-keerthy@ti.com>
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM
shows the signal name for the output of post divider (M2) is CLKOUTLDO.
Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as
input to apll mux.
So the actual output of dpll is dpll_pcie_ref_m2ldo_ck which is also the input
of apll.
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 7148e7c..f5dca1f 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1152,7 +1152,7 @@
apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
compatible = "ti,mux-clock";
- clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+ clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
#clock-cells = <0>;
reg = <0x021c 0x4>;
ti,bit-shift = <7>;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [RESEND PATCH 3/8] ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
2014-07-14 10:42 [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 1/8] ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 2/8] ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I
@ 2014-07-14 10:42 ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 4/8] ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance Kishon Vijay Abraham I
` (4 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-14 10:42 UTC (permalink / raw)
To: linux-kernel, tony, devicetree, linux-arm-kernel, linux-omap
Cc: Mark Rutland, Paul Walmsley, Pawel Moll, Rajendra Nayak, kishon,
Tero Kristo, Rob Herring, Kumar Gala
Added missing 32KHz clock used by PCIe PHY.
Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows
32KHz is used by PCIe PHY.
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index f5dca1f..3ff6d7c 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,14 @@
reg = <0x021c>, <0x0220>;
};
+ optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b0>;
+ ti,bit-shift = <8>;
+ };
+
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [RESEND PATCH 4/8] ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance
2014-07-14 10:42 [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data Kishon Vijay Abraham I
` (2 preceding siblings ...)
2014-07-14 10:42 ` [RESEND PATCH 3/8] ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY Kishon Vijay Abraham I
@ 2014-07-14 10:42 ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 5/8] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe " Kishon Vijay Abraham I
` (3 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-14 10:42 UTC (permalink / raw)
To: linux-kernel, tony, devicetree, linux-arm-kernel, linux-omap
Cc: Mark Rutland, Paul Walmsley, Pawel Moll, Keerthy, Rajendra Nayak,
kishon, Tero Kristo, Rob Herring, Kumar Gala
There are two instances of PCIe PHY in DRA7xx. So renamed
optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to
optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk
respectively. This is needed for adding the clocks for second PCIe PHY
instance.
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 3ff6d7c..fe5db55 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,7 +1165,7 @@
reg = <0x021c>, <0x0220>;
};
- optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
+ optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
@@ -1183,7 +1183,7 @@
ti,max-div = <2>;
};
- optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+ optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
@@ -1191,7 +1191,7 @@
ti,bit-shift = <9>;
};
- optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+ optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [RESEND PATCH 5/8] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance
2014-07-14 10:42 [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data Kishon Vijay Abraham I
` (3 preceding siblings ...)
2014-07-14 10:42 ` [RESEND PATCH 4/8] ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance Kishon Vijay Abraham I
@ 2014-07-14 10:42 ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 6/8] ARM: dts: dra7: Add dt data for PCIe PHY control module Kishon Vijay Abraham I
` (2 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-14 10:42 UTC (permalink / raw)
To: linux-kernel, tony, devicetree, linux-arm-kernel, linux-omap
Cc: kishon, Rajendra Nayak, Tero Kristo, Paul Walmsley, Rob Herring,
Pawel Moll, Mark Rutland, Kumar Gala
Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index fe5db55..b48f18b 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1173,6 +1173,14 @@
ti,bit-shift = <8>;
};
+ optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b8>;
+ ti,bit-shift = <8>;
+ };
+
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
@@ -1191,6 +1199,14 @@
ti,bit-shift = <9>;
};
+ optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
+ compatible = "ti,gate-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b8>;
+ ti,bit-shift = <9>;
+ };
+
optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
@@ -1199,6 +1215,14 @@
ti,bit-shift = <10>;
};
+ optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
+ compatible = "ti,gate-clock";
+ clocks = <&optfclk_pciephy_div>;
+ #clock-cells = <0>;
+ reg = <0x13b8>;
+ ti,bit-shift = <10>;
+ };
+
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [RESEND PATCH 6/8] ARM: dts: dra7: Add dt data for PCIe PHY control module
2014-07-14 10:42 [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data Kishon Vijay Abraham I
` (4 preceding siblings ...)
2014-07-14 10:42 ` [RESEND PATCH 5/8] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe " Kishon Vijay Abraham I
@ 2014-07-14 10:42 ` Kishon Vijay Abraham I
2014-07-14 10:42 ` [RESEND PATCH 7/8] ARM: dts: dra7: Add dt data for PCIe PHY Kishon Vijay Abraham I
[not found] ` <1405334543-25509-1-git-send-email-kishon-l0cyMroinI0@public.gmane.org>
7 siblings, 0 replies; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-14 10:42 UTC (permalink / raw)
To: linux-kernel, tony, devicetree, linux-arm-kernel, linux-omap
Cc: kishon, Rob Herring, Pawel Moll, Mark Rutland, Kumar Gala
Added dt data for PCIe PHY control module used by PCIe PHY.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 961be6b..e4999e4 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -828,6 +828,23 @@
ti,hwmods = "sata";
};
+ omap_control_pcie1phy: control-phy@0x4a003c40 {
+ compatible = "ti,control-phy-pcie";
+ reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
+ reg-names = "power", "control_sma", "pcie_pcs";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ };
+
+ omap_control_pcie2phy: control-pcie@0x4a003c44 {
+ compatible = "ti,control-phy-pcie";
+ reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
+ reg-names = "power", "control_sma", "pcie_pcs";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ status = "disabled";
+ };
+
omap_control_usb2phy1: control-phy@4a002300 {
compatible = "ti,control-phy-usb2";
reg = <0x4a002300 0x4>;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [RESEND PATCH 7/8] ARM: dts: dra7: Add dt data for PCIe PHY
2014-07-14 10:42 [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data Kishon Vijay Abraham I
` (5 preceding siblings ...)
2014-07-14 10:42 ` [RESEND PATCH 6/8] ARM: dts: dra7: Add dt data for PCIe PHY control module Kishon Vijay Abraham I
@ 2014-07-14 10:42 ` Kishon Vijay Abraham I
[not found] ` <1405334543-25509-1-git-send-email-kishon-l0cyMroinI0@public.gmane.org>
7 siblings, 0 replies; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-14 10:42 UTC (permalink / raw)
To: linux-kernel, tony, devicetree, linux-arm-kernel, linux-omap
Cc: kishon, Rob Herring, Pawel Moll, Mark Rutland, Kumar Gala
Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
26.3.3 PCIe Shared PHY Subsystem Integration in vE of DRA7xx ES1.0
describes the PCIe PHY subsystem-related components integrated in the device.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 41 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index e4999e4..cbaf47d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -816,6 +816,47 @@
clock-names = "sysclk";
#phy-cells = <0>;
};
+
+ pcie1_phy: pciephy@4a094000 {
+ compatible = "ti,phy-pipe3-pcie";
+ reg = <0x4a094000 0x80>, /* phy_rx */
+ <0x4a094400 0x64>; /* phy_tx */
+ reg-names = "phy_rx", "phy_tx";
+ ctrl-module = <&omap_control_pcie1phy>;
+ clocks = <&dpll_pcie_ref_ck>,
+ <&dpll_pcie_ref_m2ldo_ck>,
+ <&optfclk_pciephy1_32khz>,
+ <&optfclk_pciephy1_clk>,
+ <&optfclk_pciephy1_div_clk>,
+ <&optfclk_pciephy_div>;
+ clock-names = "dpll_ref", "dpll_ref_m2",
+ "wkupclk", "refclk",
+ "div-clk", "phy-div";
+ #phy-cells = <0>;
+ id = <1>;
+ ti,hwmods = "pcie1-phy";
+ };
+
+ pcie2_phy: pciephy@4a095000 {
+ compatible = "ti,phy-pipe3-pcie";
+ reg = <0x4a095000 0x80>, /* phy_rx */
+ <0x4a095400 0x64>; /* phy_tx */
+ reg-names = "phy_rx", "phy_tx";
+ ctrl-module = <&omap_control_pcie2phy>;
+ clocks = <&dpll_pcie_ref_ck>,
+ <&dpll_pcie_ref_m2ldo_ck>,
+ <&optfclk_pciephy2_32khz>,
+ <&optfclk_pciephy2_clk>,
+ <&optfclk_pciephy2_div_clk>,
+ <&optfclk_pciephy_div>;
+ clock-names = "dpll_ref", "dpll_ref_m2",
+ "wkupclk", "refclk",
+ "div-clk", "phy-div";
+ #phy-cells = <0>;
+ ti,hwmods = "pcie2-phy";
+ id = <2>;
+ status = "disabled";
+ };
};
sata: sata@4a141100 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread[parent not found: <1405334543-25509-1-git-send-email-kishon-l0cyMroinI0@public.gmane.org>]
* [RESEND PATCH 8/8] ARM: dts: dra7: Add dt data for PCIe controller
[not found] ` <1405334543-25509-1-git-send-email-kishon-l0cyMroinI0@public.gmane.org>
@ 2014-07-14 10:42 ` Kishon Vijay Abraham I
2014-07-15 7:18 ` [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data Tony Lindgren
1 sibling, 0 replies; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-14 10:42 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, tony-4v6yS6AI5VpBDgjK7y7TUQ,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: kishon-l0cyMroinI0, Rob Herring, Pawel Moll, Mark Rutland,
Kumar Gala, Bjorn Helgaas, Jingoo Han, Jason Gunthorpe,
Marek Vasut, Arnd Bergmann
Added dt data for PCIe controller. This node contains dt data for
both the DRA7 part of designware controller and for the designware core.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Cc: Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Cc: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Cc: Jason Gunthorpe <jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
Cc: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Signed-off-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/dra7.dtsi | 69 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index cbaf47d..b6060d3 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -99,6 +99,75 @@
};
};
+ axi@0 {
+ compatible = "simple-bus";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges = <0x51000000 0x51000000 0x3000
+ 0x0 0x20000000 0x10000000>;
+ pcie@51000000 {
+ compatible = "ti,dra7-pcie";
+ reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
+ reg-names = "rc_dbics", "ti_conf", "config";
+ interrupts = <0 232 0x4>, <0 233 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0 0x03000 0 0x00010000
+ 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ ti,hwmods = "pcie1";
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy0";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 1>,
+ <0 0 0 2 &pcie1_intc 2>,
+ <0 0 0 3 &pcie1_intc 3>,
+ <0 0 0 4 &pcie1_intc 4>;
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ axi@1 {
+ compatible = "simple-bus";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges = <0x51800000 0x51800000 0x3000
+ 0x0 0x30000000 0x10000000>;
+ status = "disabled";
+ pcie@51000000 {
+ compatible = "ti,dra7-pcie";
+ reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
+ reg-names = "rc_dbics", "ti_conf", "config";
+ interrupts = <0 355 0x4>, <0 356 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0 0x03000 0 0x00010000
+ 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ ti,hwmods = "pcie2";
+ phys = <&pcie2_phy>;
+ phy-names = "pcie-phy0";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2_intc 1>,
+ <0 0 0 2 &pcie2_intc 2>,
+ <0 0 0 3 &pcie2_intc 3>,
+ <0 0 0 4 &pcie2_intc 4>;
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
cm_core_aon: cm_core_aon@4a005000 {
compatible = "ti,dra7-cm-core-aon";
reg = <0x4a005000 0x2000>;
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data
[not found] ` <1405334543-25509-1-git-send-email-kishon-l0cyMroinI0@public.gmane.org>
2014-07-14 10:42 ` [RESEND PATCH 8/8] ARM: dts: dra7: Add dt data for PCIe controller Kishon Vijay Abraham I
@ 2014-07-15 7:18 ` Tony Lindgren
2014-07-16 4:46 ` Kishon Vijay Abraham I
1 sibling, 1 reply; 11+ messages in thread
From: Tony Lindgren @ 2014-07-15 7:18 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-omap-u79uwXL29TY76Z2rM5mHXA
* Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org> [140714 03:44]:
> [1] is split into separate series in order for individual subsystem
> Maintainers to pick up the patches. This series handles the PCIe
> dt data for DRA7.
>
> This series has better commit logs than the previous one modified as
> suggested by Tero.
>
> [1] -> https://lkml.org/lkml/2014/5/29/258
>
> Keerthy (2):
> ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div
> clock
> ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to
> dpll_pcie_ref_m2ldo_ck
>
> Kishon Vijay Abraham I (6):
> ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
> ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY
> instance
> ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY
> instance
> ARM: dts: dra7: Add dt data for PCIe PHY control module
> ARM: dts: dra7: Add dt data for PCIe PHY
> ARM: dts: dra7: Add dt data for PCIe controller
>
> arch/arm/boot/dts/dra7.dtsi | 127 ++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/dra7xx-clocks.dtsi | 39 ++++++++++-
> 2 files changed, 163 insertions(+), 3 deletions(-)
Applying this series into omap-for-v3.17/dt thanks.
Tony
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^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data
2014-07-15 7:18 ` [RESEND PATCH 0/8] arm: dts: dra7: Add PCIe data and PCIe PHY data Tony Lindgren
@ 2014-07-16 4:46 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-16 4:46 UTC (permalink / raw)
To: Tony Lindgren; +Cc: linux-kernel, devicetree, linux-arm-kernel, linux-omap
On Tuesday 15 July 2014 12:48 PM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I <kishon@ti.com> [140714 03:44]:
>> [1] is split into separate series in order for individual subsystem
>> Maintainers to pick up the patches. This series handles the PCIe
>> dt data for DRA7.
>>
>> This series has better commit logs than the previous one modified as
>> suggested by Tero.
>>
>> [1] -> https://lkml.org/lkml/2014/5/29/258
>>
>> Keerthy (2):
>> ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div
>> clock
>> ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to
>> dpll_pcie_ref_m2ldo_ck
>>
>> Kishon Vijay Abraham I (6):
>> ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
>> ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY
>> instance
>> ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY
>> instance
>> ARM: dts: dra7: Add dt data for PCIe PHY control module
>> ARM: dts: dra7: Add dt data for PCIe PHY
>> ARM: dts: dra7: Add dt data for PCIe controller
>>
>> arch/arm/boot/dts/dra7.dtsi | 127 ++++++++++++++++++++++++++++++++++
>> arch/arm/boot/dts/dra7xx-clocks.dtsi | 39 ++++++++++-
>> 2 files changed, 163 insertions(+), 3 deletions(-)
>
> Applying this series into omap-for-v3.17/dt thanks.
Thanks :-)
-Kishon
>
> Tony
>
^ permalink raw reply [flat|nested] 11+ messages in thread