From: Tony Lindgren <tony@atomide.com>
To: Dan Murphy <dmurphy@ti.com>
Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org
Subject: Re: [v3 PATCH 2/6] dt: TI: Describe the ti reset DT entries
Date: Mon, 21 Jul 2014 00:01:25 -0700 [thread overview]
Message-ID: <20140721070125.GM18374@atomide.com> (raw)
In-Reply-To: <1405615531-15649-2-git-send-email-dmurphy@ti.com>
* Dan Murphy <dmurphy@ti.com> [140717 09:47]:
> +
> +example:
> + prm: prm@4ae06000 {
> + compatible = "ti,omap5-prm";
> + reg = <0x4ae06000 0x3000>;
> +
> + prm_resets: resets {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #reset-cells = <1>;
> + };
> + };
Probably the way to go with mapping various PRCM registers to separate
drivers is to provide one or more syscon entries like we already have
for the SCM. You may want to coordinate this with Tero.
Regards,
Tony
next prev parent reply other threads:[~2014-07-21 7:01 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-17 16:45 [v3 PATCH 1/6] drivers: reset: TI: SoC reset controller support Dan Murphy
2014-07-17 16:45 ` [v3 PATCH 2/6] dt: TI: Describe the ti reset DT entries Dan Murphy
2014-07-21 7:01 ` Tony Lindgren [this message]
2014-07-22 18:51 ` Suman Anna
2014-07-17 16:45 ` [v3 PATCH 3/6] ARM: dts: am33xx: Add prcm_resets node Dan Murphy
2014-07-22 18:54 ` Suman Anna
2014-07-17 16:45 ` [v3 PATCH 4/6] ARM: dts: am4372: " Dan Murphy
2014-07-22 19:01 ` Suman Anna
[not found] ` <1405615531-15649-1-git-send-email-dmurphy-l0cyMroinI0@public.gmane.org>
2014-07-17 16:45 ` [v3 PATCH 5/6] ARM: dts: dra7: Add prm_resets node Dan Murphy
2014-07-22 19:07 ` Suman Anna
2014-07-17 16:45 ` [v3 PATCH 6/6] ARM: dts: omap5: " Dan Murphy
2014-07-22 19:09 ` Suman Anna
2014-07-18 6:41 ` [v3 PATCH 1/6] drivers: reset: TI: SoC reset controller support Lothar Waßmann
2014-07-22 20:16 ` Suman Anna
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