[PATCH RFC v4 1/4] nand: pl353: Add basic driver for arm pl353 smc nand interface

[PATCH RFC v4 1/4] nand: pl353: Add basic driver for arm pl353 smc nand interface

[Punnaiah Choudary Kalluri]

Add driver for arm pl353 static memory controller nand interface with
HW ECC support. This controller is used in xilinx zynq soc for interfacing
the nand flash memory.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
---
Changes in v4:
 - Updated the driver to sync with pl353_smc driver APIs
Changes in v3:
 - implemented the proper error codes
 - further breakdown this patch to multiple sets
 - added the controller and driver details to Documentation section
 - updated the licenece to GPLv2
 - reorganized the pl353_nand_ecc_init function
Changes in v2:
 - use "depends on" rather than "select" option in kconfig
 - remove unused variable parts
 - remove dummy helper and use writel_relaxed directly
---
 drivers/mtd/nand/Kconfig      |    7 +
 drivers/mtd/nand/Makefile     |    1 +
 drivers/mtd/nand/pl353_nand.c |  857 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 865 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/pl353_nand.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index f1cf503..a3462e6 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -492,6 +492,13 @@ config MTD_NAND_NUC900
 	  This enables the driver for the NAND Flash on evaluation board based
 	  on w90p910 / NUC9xx.
 
+config MTD_NAND_PL353
+	tristate "ARM Pl353 NAND flash driver"
+	depends on MTD_NAND && ARM
+	depends on PL353_SMC
+	help
+	  This enables access to the NAND flash device on PL353 SMC controller.
+
 config MTD_NAND_JZ4740
 	tristate "Support for JZ4740 SoC NAND controller"
 	depends on MACH_JZ4740
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 542b568..a4c2679 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740_nand.o
 obj-$(CONFIG_MTD_NAND_GPMI_NAND)	+= gpmi-nand/
 obj-$(CONFIG_MTD_NAND_XWAY)		+= xway_nand.o
 obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash/
+obj-$(CONFIG_MTD_NAND_PL353)		+= pl353_nand.o
 
 nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/pl353_nand.c b/drivers/mtd/nand/pl353_nand.c
new file mode 100644
index 0000000..f97f428
--- /dev/null
+++ b/drivers/mtd/nand/pl353_nand.c
@@ -0,0 +1,857 @@
+/*
+ * ARM PL353 NAND Flash Controller Driver
+ *
+ * Copyright (C) 2009 - 2014 Xilinx, Inc.
+ *
+ * This driver is based on plat_nand.c and mxc_nand.c drivers
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/memory/pl353-smc.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_mtd.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#define PL353_NAND_DRIVER_NAME "pl353-nand"
+
+/* NAND flash driver defines */
+#define PL353_NAND_CMD_PHASE	1	/* End command valid in command phase */
+#define PL353_NAND_DATA_PHASE	2	/* End command valid in data phase */
+#define PL353_NAND_ECC_SIZE	512	/* Size of data for ECC operation */
+
+/* Flash memory controller operating parameters */
+
+#define PL353_NAND_ECC_CONFIG	(BIT(4)  |	/* ECC read at end of page */ \
+				 (0 << 5))	/* No Jumping */
+
+/* AXI Address definitions */
+#define START_CMD_SHIFT		3
+#define END_CMD_SHIFT		11
+#define END_CMD_VALID_SHIFT	20
+#define ADDR_CYCLES_SHIFT	21
+#define CLEAR_CS_SHIFT		21
+#define ECC_LAST_SHIFT		10
+#define COMMAND_PHASE		(0 << 19)
+#define DATA_PHASE		BIT(19)
+
+#define PL353_NAND_ECC_LAST	BIT(ECC_LAST_SHIFT)	/* Set ECC_Last */
+#define PL353_NAND_CLEAR_CS	BIT(CLEAR_CS_SHIFT)	/* Clear chip select */
+
+#define ONDIE_ECC_FEATURE_ADDR	0x90
+#define PL353_NAND_ECC_BUSY_TIMEOUT	(1 * HZ)
+#define PL353_NAND_DEV_BUSY_TIMEOUT	(1 * HZ)
+#define PL353_NAND_LAST_TRANSFER_LENGTH	4
+
+/**
+ * struct pl353_nand_command_format - Defines NAND flash command format
+ * @start_cmd:		First cycle command (Start command)
+ * @end_cmd:		Second cycle command (Last command)
+ * @addr_cycles:	Number of address cycles required to send the address
+ * @end_cmd_valid:	The second cycle command is valid for cmd or data phase
+ */
+struct pl353_nand_command_format {
+	int start_cmd;
+	int end_cmd;
+	u8 addr_cycles;
+	u8 end_cmd_valid;
+};
+
+/**
+ * struct pl353_nand_info - Defines the NAND flash driver instance
+ * @chip:		NAND chip information structure
+ * @mtd:		MTD information structure
+ * @nand_base:		Virtual address of the NAND flash device
+ * @end_cmd_pending:	End command is pending
+ * @end_cmd:		End command
+ * @ecc_mode:		ECC mode
+ */
+struct pl353_nand_info {
+	struct nand_chip chip;
+	struct mtd_info mtd;
+	void __iomem *nand_base;
+	unsigned long end_cmd_pending;
+	unsigned long end_cmd;
+	int ecc_mode;
+};
+
+/*
+ * The NAND flash operations command format
+ */
+static const struct pl353_nand_command_format pl353_nand_commands[] = {
+	{NAND_CMD_READ0, NAND_CMD_READSTART, 5, PL353_NAND_CMD_PHASE},
+	{NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, PL353_NAND_CMD_PHASE},
+	{NAND_CMD_READID, NAND_CMD_NONE, 1, NAND_CMD_NONE},
+	{NAND_CMD_STATUS, NAND_CMD_NONE, 0, NAND_CMD_NONE},
+	{NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, PL353_NAND_DATA_PHASE},
+	{NAND_CMD_RNDIN, NAND_CMD_NONE, 2, NAND_CMD_NONE},
+	{NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, PL353_NAND_CMD_PHASE},
+	{NAND_CMD_RESET, NAND_CMD_NONE, 0, NAND_CMD_NONE},
+	{NAND_CMD_PARAM, NAND_CMD_NONE, 1, NAND_CMD_NONE},
+	{NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE},
+	{NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE},
+	{NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
+	/* Add all the flash commands supported by the flash device and Linux */
+	/*
+	 * The cache program command is not supported by driver because driver
+	 * cant differentiate between page program and cached page program from
+	 * start command, these commands can be differentiated through end
+	 * command, which doesn't fit in to the driver design. The cache program
+	 * command is not supported by NAND subsystem also, look at 1612 line
+	 * number (in nand_write_page function) of nand_base.c file.
+	 * {NAND_CMD_SEQIN, NAND_CMD_CACHEDPROG, 5, PL353_NAND_YES},
+	 */
+};
+
+/* Define default oob placement schemes for large and small page devices */
+static struct nand_ecclayout nand_oob_16 = {
+	.eccbytes = 3,
+	.eccpos = {0, 1, 2},
+	.oobfree = {
+		{.offset = 8,
+		 . length = 8} }
+};
+
+static struct nand_ecclayout nand_oob_64 = {
+	.eccbytes = 12,
+	.eccpos = {
+		   52, 53, 54, 55, 56, 57,
+		   58, 59, 60, 61, 62, 63},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 50} }
+};
+
+/**
+ * pl353_nand_calculate_hwecc - Calculate Hardware ECC
+ * @mtd:	Pointer to the mtd_info structure
+ * @data:	Pointer to the page data
+ * @ecc_code:	Pointer to the ECC buffer where ECC data needs to be stored
+ *
+ * This function retrieves the Hardware ECC data from the controller and returns
+ * ECC data back to the MTD subsystem.
+ *
+ * Return:	0 on success or error value on failure
+ */
+static int pl353_nand_calculate_hwecc(struct mtd_info *mtd,
+				const u8 *data, u8 *ecc_code)
+{
+	u32 ecc_value, ecc_status;
+	u8 ecc_reg, ecc_byte;
+	unsigned long timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT;
+
+	/* Wait till the ECC operation is complete or timeout */
+	do {
+		if (pl353_smc_ecc_is_busy(mtd->dev.parent))
+			cpu_relax();
+		else
+			break;
+	} while (!time_after_eq(jiffies, timeout));
+
+	if (time_after_eq(jiffies, timeout)) {
+		pr_err("%s timed out\n", __func__);
+		return -ETIMEDOUT;
+	}
+
+	for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
+		/* Read ECC value for each block */
+		ecc_value = pl353_smc_get_ecc_val(mtd->dev.parent, ecc_reg);
+		ecc_status = (ecc_value >> 24) & 0xFF;
+		/* ECC value valid */
+		if (ecc_status & 0x40) {
+			for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
+				/* Copy ECC bytes to MTD buffer */
+				*ecc_code = ecc_value & 0xFF;
+				ecc_value = ecc_value >> 8;
+				ecc_code++;
+			}
+		} else {
+			pr_warn("%s status failed\n", __func__);
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+
+/**
+ * onehot - onehot function
+ * @value:	Value to check for onehot
+ *
+ * This function checks whether a value is onehot or not.
+ * onehot is if and only if onebit is set.
+ *
+ * Return:	1 if it is onehot else 0
+ */
+static int onehot(unsigned short value)
+{
+	return (value & (value - 1)) == 0;
+}
+
+/**
+ * pl353_nand_correct_data - ECC correction function
+ * @mtd:	Pointer to the mtd_info structure
+ * @buf:	Pointer to the page data
+ * @read_ecc:	Pointer to the ECC value read from spare data area
+ * @calc_ecc:	Pointer to the calculated ECC value
+ *
+ * This function corrects the ECC single bit errors & detects 2-bit errors.
+ *
+ * Return:	0 if no ECC errors found
+ *		1 if single bit error found and corrected.
+ *		-1 if multiple ECC errors found.
+ */
+static int pl353_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
+				unsigned char *read_ecc,
+				unsigned char *calc_ecc)
+{
+	unsigned char bit_addr;
+	unsigned int byte_addr;
+	unsigned short ecc_odd, ecc_even, read_ecc_lower, read_ecc_upper;
+	unsigned short calc_ecc_lower, calc_ecc_upper;
+
+	read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
+	read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
+
+	calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
+	calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
+
+	ecc_odd = read_ecc_lower ^ calc_ecc_lower;
+	ecc_even = read_ecc_upper ^ calc_ecc_upper;
+
+	if ((ecc_odd == 0) && (ecc_even == 0))
+		return 0;       /* no error */
+
+	if (ecc_odd == (~ecc_even & 0xfff)) {
+		/* bits [11:3] of error code is byte offset */
+		byte_addr = (ecc_odd >> 3) & 0x1ff;
+		/* bits [2:0] of error code is bit offset */
+		bit_addr = ecc_odd & 0x7;
+		/* Toggling error bit */
+		buf[byte_addr] ^= (1 << bit_addr);
+		return 1;
+	}
+
+	if (onehot(ecc_odd | ecc_even) == 1)
+		return 1; /* one error in parity */
+
+	return -EBADMSG; /* Uncorrectable error */
+}
+
+/**
+ * pl353_nand_read_oob - [REPLACABLE] the most common OOB data read function
+ * @mtd:	Pointer to the mtd info structure
+ * @chip:	Pointer to the NAND chip info structure
+ * @page:	Page number to read
+ *
+ * Return:	Always return zero
+ */
+static int pl353_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+			    int page)
+{
+	unsigned long data_phase_addr;
+	uint8_t *p;
+
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+
+	p = chip->oob_poi;
+	chip->read_buf(mtd, p,
+			(mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH));
+	p += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
+	data_phase_addr |= PL353_NAND_CLEAR_CS;
+	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+	chip->read_buf(mtd, p, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	return 0;
+}
+
+/**
+ * pl353_nand_write_oob - [REPLACABLE] the most common OOB data write function
+ * @mtd:	Pointer to the mtd info structure
+ * @chip:	Pointer to the NAND chip info structure
+ * @page:	Page number to write
+ *
+ * Return:	Zero on success and EIO on failure
+ */
+static int pl353_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+			     int page)
+{
+	int status = 0;
+	const uint8_t *buf = chip->oob_poi;
+	unsigned long data_phase_addr;
+
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+
+	chip->write_buf(mtd, buf,
+			(mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH));
+	buf += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
+	data_phase_addr |= PL353_NAND_CLEAR_CS;
+	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
+	chip->write_buf(mtd, buf, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	/* Send command to program the OOB data */
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+	status = chip->waitfunc(mtd, chip);
+
+	return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/**
+ * nand_write_page_hwecc - Hardware ECC based page write function
+ * @mtd:		Pointer to the mtd info structure
+ * @chip:		Pointer to the NAND chip info structure
+ * @buf:		Pointer to the data buffer
+ * @oob_required:	Caller requires OOB data read to chip->oob_poi
+ *
+ * This functions writes data and hardware generated ECC values in to the page.
+ *
+ * Return:	Zero on success and error on failure.
+ */
+static int pl353_nand_write_page_hwecc(struct mtd_info *mtd,
+				    struct nand_chip *chip, const uint8_t *buf,
+				    int oob_required)
+{
+	int i, status, eccsize = chip->ecc.size;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	const uint8_t *p = buf;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+	unsigned long data_phase_addr;
+	uint8_t *oob_ptr;
+
+	for ( ; (eccsteps - 1); eccsteps--) {
+		chip->write_buf(mtd, p, eccsize);
+		p += eccsize;
+	}
+	chip->write_buf(mtd, p, (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH));
+	p += (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	/* Set ECC Last bit to 1 */
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
+	data_phase_addr |= PL353_NAND_ECC_LAST;
+	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
+	chip->write_buf(mtd, p, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	/* Wait for ECC to be calculated and read the error values */
+	p = buf;
+	status = chip->ecc.calculate(mtd, p, &ecc_calc[0]);
+	if (status)
+		return status;
+
+	for (i = 0; i < chip->ecc.total; i++)
+		chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
+
+	/* Clear ECC last bit */
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
+	data_phase_addr &= ~PL353_NAND_ECC_LAST;
+	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
+
+	/* Write the spare area with ECC bytes */
+	oob_ptr = chip->oob_poi;
+	chip->write_buf(mtd, oob_ptr,
+			(mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH));
+
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
+	data_phase_addr |= PL353_NAND_CLEAR_CS;
+	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
+	oob_ptr += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+	chip->write_buf(mtd, oob_ptr, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	return 0;
+}
+
+/**
+ * pl353_nand_read_page_hwecc - Hardware ECC based page read function
+ * @mtd:		Pointer to the mtd info structure
+ * @chip:		Pointer to the NAND chip info structure
+ * @buf:		Pointer to the buffer to store read data
+ * @oob_required:	Caller requires OOB data read to chip->oob_poi
+ * @page:		Page number to read
+ *
+ * This functions reads data and checks the data integrity by comparing hardware
+ * generated ECC values and read ECC values from spare area.
+ *
+ * Return:	0 always and updates ECC operation status in to MTD structure
+ */
+static int pl353_nand_read_page_hwecc(struct mtd_info *mtd,
+				     struct nand_chip *chip,
+				     uint8_t *buf, int oob_required, int page)
+{
+	int i, stat, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	uint8_t *ecc_code = chip->buffers->ecccode;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+	unsigned long data_phase_addr;
+	uint8_t *oob_ptr;
+
+	for ( ; (eccsteps - 1); eccsteps--) {
+		chip->read_buf(mtd, p, eccsize);
+		p += eccsize;
+	}
+	chip->read_buf(mtd, p, (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH));
+	p += (eccsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	/* Set ECC Last bit to 1 */
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
+	data_phase_addr |= PL353_NAND_ECC_LAST;
+	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+	chip->read_buf(mtd, p, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	/* Read the calculated ECC value */
+	p = buf;
+	stat = chip->ecc.calculate(mtd, p, &ecc_calc[0]);
+	if (stat < 0)
+		return stat;
+
+	/* Clear ECC last bit */
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
+	data_phase_addr &= ~PL353_NAND_ECC_LAST;
+	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+
+	/* Read the stored ECC value */
+	oob_ptr = chip->oob_poi;
+	chip->read_buf(mtd, oob_ptr,
+			(mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH));
+
+	/* de-assert chip select */
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
+	data_phase_addr |= PL353_NAND_CLEAR_CS;
+	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+
+	oob_ptr += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+	chip->read_buf(mtd, oob_ptr, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	for (i = 0; i < chip->ecc.total; i++)
+		ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
+
+	eccsteps = chip->ecc.steps;
+	p = buf;
+
+	/* Check ECC error for all blocks and correct if it is correctable */
+	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+		if (stat < 0)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+	}
+	return 0;
+}
+
+/**
+ * pl353_nand_select_chip - Select the flash device
+ * @mtd:	Pointer to the mtd info structure
+ * @chip:	Pointer to the NAND chip info structure
+ *
+ * This function is empty as the NAND controller handles chip select line
+ * internally based on the chip address passed in command and data phase.
+ */
+static void pl353_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+	return;
+}
+
+/**
+ * pl353_nand_cmd_function - Send command to NAND device
+ * @mtd:	Pointer to the mtd_info structure
+ * @command:	The command to be sent to the flash device
+ * @column:	The column address for this command, -1 if none
+ * @page_addr:	The page address for this command, -1 if none
+ */
+static void pl353_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
+				 int column, int page_addr)
+{
+	struct nand_chip *chip = mtd->priv;
+	const struct pl353_nand_command_format *curr_cmd = NULL;
+	struct pl353_nand_info *xnand =
+		container_of(mtd, struct pl353_nand_info, mtd);
+	void __iomem *cmd_addr;
+	unsigned long cmd_data = 0, end_cmd_valid = 0;
+	unsigned long cmd_phase_addr, data_phase_addr, end_cmd, i;
+	unsigned long timeout = jiffies + PL353_NAND_DEV_BUSY_TIMEOUT;
+
+	if (xnand->end_cmd_pending) {
+		/*
+		 * Check for end command if this command request is same as the
+		 * pending command then return
+		 */
+		if (xnand->end_cmd == command) {
+			xnand->end_cmd = 0;
+			xnand->end_cmd_pending = 0;
+			return;
+		}
+	}
+
+	/* Emulate NAND_CMD_READOOB for large page device */
+	if ((mtd->writesize > PL353_NAND_ECC_SIZE) &&
+	    (command == NAND_CMD_READOOB)) {
+		column += mtd->writesize;
+		command = NAND_CMD_READ0;
+	}
+
+	/* Get the command format */
+	for (i = 0; (pl353_nand_commands[i].start_cmd != NAND_CMD_NONE ||
+		     pl353_nand_commands[i].end_cmd != NAND_CMD_NONE); i++)
+		if (command == pl353_nand_commands[i].start_cmd)
+			curr_cmd = &pl353_nand_commands[i];
+
+	if (curr_cmd == NULL)
+		return;
+
+	/* Clear interrupt */
+	pl353_smc_clr_nand_int(mtd->dev.parent);
+
+	/* Get the command phase address */
+	if (curr_cmd->end_cmd_valid == PL353_NAND_CMD_PHASE)
+		end_cmd_valid = 1;
+
+	if (curr_cmd->end_cmd == NAND_CMD_NONE)
+		end_cmd = 0x0;
+	else
+		end_cmd = curr_cmd->end_cmd;
+
+	cmd_phase_addr = (unsigned long __force)xnand->nand_base        |
+			 (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT)    |
+			 (end_cmd_valid << END_CMD_VALID_SHIFT)          |
+			 (COMMAND_PHASE)                                 |
+			 (end_cmd << END_CMD_SHIFT)                      |
+			 (curr_cmd->start_cmd << START_CMD_SHIFT);
+
+	cmd_addr = (void __iomem * __force)cmd_phase_addr;
+
+	/* Get the data phase address */
+	end_cmd_valid = 0;
+
+	data_phase_addr = (unsigned long __force)xnand->nand_base       |
+			  (0x0 << CLEAR_CS_SHIFT)                         |
+			  (end_cmd_valid << END_CMD_VALID_SHIFT)          |
+			  (DATA_PHASE)                                    |
+			  (end_cmd << END_CMD_SHIFT)                      |
+			  (0x0 << ECC_LAST_SHIFT);
+
+	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+	chip->IO_ADDR_W = chip->IO_ADDR_R;
+
+	/* Command phase AXI write */
+	/* Read & Write */
+	if (column != -1 && page_addr != -1) {
+		/* Adjust columns for 16 bit bus width */
+		if (chip->options & NAND_BUSWIDTH_16)
+			column >>= 1;
+		cmd_data = column;
+		if (mtd->writesize > PL353_NAND_ECC_SIZE) {
+			cmd_data |= page_addr << 16;
+			/* Another address cycle for devices > 128MiB */
+			if (chip->chipsize > (128 << 20)) {
+				writel_relaxed(cmd_data, cmd_addr);
+				cmd_data = (page_addr >> 16);
+			}
+		} else {
+			cmd_data |= page_addr << 8;
+		}
+	} else if (page_addr != -1) {
+		/* Erase */
+		cmd_data = page_addr;
+	} else if (column != -1) {
+		/*
+		 * Change read/write column, read id etc
+		 * Adjust columns for 16 bit bus width
+		 */
+		if ((chip->options & NAND_BUSWIDTH_16) &&
+			((command == NAND_CMD_READ0) ||
+			(command == NAND_CMD_SEQIN) ||
+			(command == NAND_CMD_RNDOUT) ||
+			(command == NAND_CMD_RNDIN)))
+				column >>= 1;
+		cmd_data = column;
+	}
+
+	writel_relaxed(cmd_data, cmd_addr);
+
+	if (curr_cmd->end_cmd_valid) {
+		xnand->end_cmd = curr_cmd->end_cmd;
+		xnand->end_cmd_pending = 1;
+	}
+
+	ndelay(100);
+
+	if ((command == NAND_CMD_READ0) ||
+	    (command == NAND_CMD_RESET) ||
+	    (command == NAND_CMD_PARAM) ||
+	    (command == NAND_CMD_GET_FEATURES)) {
+
+		/* Wait till the device is ready or timeout */
+		do {
+			if (chip->dev_ready(mtd))
+				break;
+			else
+				cpu_relax();
+		} while (!time_after_eq(jiffies, timeout));
+
+		if (time_after_eq(jiffies, timeout))
+			pr_err("%s timed out\n", __func__);
+		return;
+	}
+}
+
+/**
+ * pl353_nand_read_buf - read chip data into buffer
+ * @mtd:	Pointer to the mtd info structure
+ * @buf:	Pointer to the buffer to store read data
+ * @len:	Number of bytes to read
+ */
+static void pl353_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *chip = mtd->priv;
+	unsigned long *ptr = (unsigned long *)buf;
+
+	len >>= 2;
+	for (i = 0; i < len; i++)
+		ptr[i] = readl(chip->IO_ADDR_R);
+}
+
+/**
+ * pl353_nand_write_buf - write buffer to chip
+ * @mtd:	Pointer to the mtd info structure
+ * @buf:	Pointer to the buffer to store read data
+ * @len:	Number of bytes to write
+ */
+static void pl353_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
+				int len)
+{
+	int i;
+	struct nand_chip *chip = mtd->priv;
+	unsigned long *ptr = (unsigned long *)buf;
+
+	len >>= 2;
+
+	for (i = 0; i < len; i++)
+		writel(ptr[i], chip->IO_ADDR_W);
+}
+
+/**
+ * pl353_nand_device_ready - Check device ready/busy line
+ * @mtd:	Pointer to the mtd_info structure
+ *
+ * Return:	0 on busy or 1 on ready state
+ */
+static int pl353_nand_device_ready(struct mtd_info *mtd)
+{
+	if (pl353_smc_get_nand_int_status_raw(mtd->dev.parent)) {
+		pl353_smc_clr_nand_int(mtd->dev.parent);
+		return 1;
+	}
+	return 0;
+}
+
+/**
+ * pl353_nand_ecc_init - Initialize the ecc information as per the ecc mode
+ * @mtd:	Pointer to the mtd_info structure
+ *
+ * This function initializes the ecc block and functional pointers as per the
+ * ecc mode
+ *
+ * Return:	Zero on success and error on failure.
+ */
+static int pl353_nand_ecc_init(struct mtd_info *mtd)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct pl353_nand_info *xnand =
+		container_of(mtd, struct pl353_nand_info, mtd);
+
+	nand_chip->ecc.read_oob = pl353_nand_read_oob;
+	nand_chip->ecc.write_oob = pl353_nand_write_oob;
+	nand_chip->ecc.strength = 1;
+
+	switch (xnand->ecc_mode) {
+	case NAND_ECC_HW:
+		if (mtd->writesize > 2048) {
+			pr_warn("hardware ECC not possible\n");
+			return -ENOTSUPP;
+		}
+
+		nand_chip->ecc.mode = NAND_ECC_HW;
+		nand_chip->ecc.calculate = pl353_nand_calculate_hwecc;
+		nand_chip->ecc.correct = pl353_nand_correct_data;
+		nand_chip->ecc.hwctl = NULL;
+		nand_chip->ecc.read_page = pl353_nand_read_page_hwecc;
+		nand_chip->ecc.size = PL353_NAND_ECC_SIZE;
+		nand_chip->ecc.write_page = pl353_nand_write_page_hwecc;
+		pl353_smc_set_ecc_pg_size(mtd->dev.parent, mtd->writesize);
+		pl353_smc_set_ecc_mode(mtd->dev.parent, PL353_SMC_ECCMODE_APB);
+		/* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
+		nand_chip->ecc.bytes = 3;
+
+		if (mtd->oobsize == 16)
+			nand_chip->ecc.layout = &nand_oob_16;
+		else
+			nand_chip->ecc.layout = &nand_oob_64;
+
+		break;
+	default:
+		return -ENOTSUPP;
+	}
+
+	return 0;
+}
+
+/**
+ * pl353_nand_probe - Probe method for the NAND driver
+ * @pdev:	Pointer to the platform_device structure
+ *
+ * This function initializes the driver data structures and the hardware.
+ *
+ * Return:	0 on success or error value on failure
+ */
+static int pl353_nand_probe(struct platform_device *pdev)
+{
+	struct pl353_nand_info *xnand;
+	struct mtd_info *mtd;
+	struct nand_chip *nand_chip;
+	struct resource *res;
+	struct mtd_part_parser_data ppdata;
+
+	xnand = devm_kzalloc(&pdev->dev, sizeof(*xnand), GFP_KERNEL);
+	if (!xnand)
+		return -ENOMEM;
+
+	/* Map physical address of NAND flash */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	xnand->nand_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(xnand->nand_base))
+		return PTR_ERR(xnand->nand_base);
+
+	/* Link the private data with the MTD structure */
+	mtd = &xnand->mtd;
+	nand_chip = &xnand->chip;
+
+	nand_chip->priv = xnand;
+	mtd->priv = nand_chip;
+	mtd->dev.parent = pdev->dev.parent;
+	mtd->owner = THIS_MODULE;
+	mtd->name = PL353_NAND_DRIVER_NAME;
+
+	/* Set address of NAND IO lines */
+	nand_chip->IO_ADDR_R = xnand->nand_base;
+	nand_chip->IO_ADDR_W = xnand->nand_base;
+
+	/* Set the driver entry points for MTD */
+	nand_chip->cmdfunc = pl353_nand_cmd_function;
+	nand_chip->dev_ready = pl353_nand_device_ready;
+	nand_chip->select_chip = pl353_nand_select_chip;
+
+	/* If we don't set this delay driver sets 20us by default */
+	nand_chip->chip_delay = 30;
+
+	/* Buffer read/write routines */
+	nand_chip->read_buf = pl353_nand_read_buf;
+	nand_chip->write_buf = pl353_nand_write_buf;
+
+	/* Set the device option and flash width */
+	nand_chip->options = NAND_BUSWIDTH_AUTO;
+	nand_chip->bbt_options = NAND_BBT_USE_FLASH;
+
+	platform_set_drvdata(pdev, xnand);
+
+	/* first scan to find the device and get the page size */
+	if (nand_scan_ident(mtd, 1, NULL)) {
+		dev_err(&pdev->dev, "nand_scan_ident for NAND failed\n");
+		return -ENXIO;
+	}
+
+	xnand->ecc_mode = of_get_nand_ecc_mode(pdev->dev.of_node);
+	if (xnand->ecc_mode < 0)
+		xnand->ecc_mode = NAND_ECC_HW;
+
+	if (pl353_nand_ecc_init(mtd))
+		return -ENOTSUPP;
+
+	if (nand_chip->options & NAND_BUSWIDTH_16)
+		pl353_smc_set_buswidth(pdev->dev.parent,
+					PL353_SMC_MEM_WIDTH_16);
+
+	/* second phase scan */
+	if (nand_scan_tail(mtd)) {
+		dev_err(&pdev->dev, "nand_scan_tail for NAND failed\n");
+		return -ENXIO;
+	}
+
+	ppdata.of_node = pdev->dev.of_node;
+
+	mtd_device_parse_register(&xnand->mtd, NULL, &ppdata, NULL, 0);
+
+	return 0;
+}
+
+/**
+ * pl353_nand_remove - Remove method for the NAND driver
+ * @pdev:	Pointer to the platform_device structure
+ *
+ * This function is called if the driver module is being unloaded. It frees all
+ * resources allocated to the device.
+ *
+ * Return:	0 on success or error value on failure
+ */
+static int pl353_nand_remove(struct platform_device *pdev)
+{
+	struct pl353_nand_info *xnand = platform_get_drvdata(pdev);
+
+	/* Release resources, unregister device */
+	nand_release(&xnand->mtd);
+
+	return 0;
+}
+
+/* Match table for device tree binding */
+static const struct of_device_id pl353_nand_of_match[] = {
+	{ .compatible = "arm,pl353-nand-r2p1" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, pl353_nand_of_match);
+
+/*
+ * pl353_nand_driver - This structure defines the NAND subsystem platform driver
+ */
+static struct platform_driver pl353_nand_driver = {
+	.probe		= pl353_nand_probe,
+	.remove		= pl353_nand_remove,
+	.driver		= {
+		.name	= PL353_NAND_DRIVER_NAME,
+		.owner	= THIS_MODULE,
+		.of_match_table = pl353_nand_of_match,
+	},
+};
+
+module_platform_driver(pl353_nand_driver);
+
+MODULE_AUTHOR("Punnaiah Choudary Kalluri <punnaia@xilinx.com>");
+MODULE_ALIAS("platform:" PL353_NAND_DRIVER_NAME);
+MODULE_DESCRIPTION("ARM PL353 NAND Flash Driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.4

[PATCH RFC v4 2/4] nand: pl353: Add software ecc support

[Punnaiah Choudary Kalluri]

Added software ecc support.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
---
Changes in v4:
- Updated the driver to sync with pl353_smc driver APIs
---
 drivers/mtd/nand/pl353_nand.c |  164 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 164 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/pl353_nand.c b/drivers/mtd/nand/pl353_nand.c
index f97f428..93dc4ca 100644
--- a/drivers/mtd/nand/pl353_nand.c
+++ b/drivers/mtd/nand/pl353_nand.c
@@ -319,6 +319,71 @@ static int pl353_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 }
 
 /**
+ * pl353_nand_read_page_raw - [Intern] read raw page data without ecc
+ * @mtd:		Pointer to the mtd info structure
+ * @chip:		Pointer to the NAND chip info structure
+ * @buf:		Pointer to the data buffer
+ * @oob_required:	Caller requires OOB data read to chip->oob_poi
+ * @page:		Page number to read
+ *
+ * Return:	Always return zero
+ */
+static int pl353_nand_read_page_raw(struct mtd_info *mtd,
+				struct nand_chip *chip,
+				uint8_t *buf, int oob_required, int page)
+{
+	unsigned long data_phase_addr;
+	uint8_t *p;
+
+	chip->read_buf(mtd, buf, mtd->writesize);
+
+	p = chip->oob_poi;
+	chip->read_buf(mtd, p,
+			(mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH));
+	p += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_R;
+	data_phase_addr |= PL353_NAND_CLEAR_CS;
+	chip->IO_ADDR_R = (void __iomem * __force)data_phase_addr;
+
+	chip->read_buf(mtd, p, PL353_NAND_LAST_TRANSFER_LENGTH);
+	return 0;
+}
+
+/**
+ * pl353_nand_write_page_raw - [Intern] raw page write function
+ * @mtd:		Pointer to the mtd info structure
+ * @chip:		Pointer to the NAND chip info structure
+ * @buf:		Pointer to the data buffer
+ * @oob_required:	Caller requires OOB data read to chip->oob_poi
+ *
+ * Return:	Always return zero
+ */
+static int pl353_nand_write_page_raw(struct mtd_info *mtd,
+				    struct nand_chip *chip,
+				    const uint8_t *buf, int oob_required)
+{
+	unsigned long data_phase_addr;
+	uint8_t *p;
+
+	chip->write_buf(mtd, buf, mtd->writesize);
+
+	p = chip->oob_poi;
+	chip->write_buf(mtd, p,
+			(mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH));
+	p += (mtd->oobsize - PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	data_phase_addr = (unsigned long __force)chip->IO_ADDR_W;
+	data_phase_addr |= PL353_NAND_CLEAR_CS;
+	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+	chip->IO_ADDR_W = (void __iomem * __force)data_phase_addr;
+
+	chip->write_buf(mtd, p, PL353_NAND_LAST_TRANSFER_LENGTH);
+
+	return 0;
+}
+
+/**
  * nand_write_page_hwecc - Hardware ECC based page write function
  * @mtd:		Pointer to the mtd info structure
  * @chip:		Pointer to the NAND chip info structure
@@ -384,6 +449,39 @@ static int pl353_nand_write_page_hwecc(struct mtd_info *mtd,
 }
 
 /**
+ * pl353_nand_write_page_swecc - [REPLACABLE] software ecc based page write
+ * function
+ * @mtd:		Pointer to the mtd info structure
+ * @chip:		Pointer to the NAND chip info structure
+ * @buf:		Pointer to the data buffer
+ * @oob_required:	Caller requires OOB data read to chip->oob_poi
+ *
+ * Return:	Always return zero
+ */
+static int pl353_nand_write_page_swecc(struct mtd_info *mtd,
+				    struct nand_chip *chip, const uint8_t *buf,
+				    int oob_required)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	const uint8_t *p = buf;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+
+	/* Software ecc calculation */
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+	for (i = 0; i < chip->ecc.total; i++)
+		chip->oob_poi[eccpos[i]] = ecc_calc[i];
+
+	chip->ecc.write_page_raw(mtd, chip, buf, 1);
+
+	return 0;
+}
+
+/**
  * pl353_nand_read_page_hwecc - Hardware ECC based page read function
  * @mtd:		Pointer to the mtd info structure
  * @chip:		Pointer to the NAND chip info structure
@@ -465,6 +563,52 @@ static int pl353_nand_read_page_hwecc(struct mtd_info *mtd,
 }
 
 /**
+ * pl353_nand_read_page_swecc - [REPLACABLE] software ecc based page read
+ * function
+ * @mtd:		Pointer to the mtd info structure
+ * @chip:		Pointer to the NAND chip info structure
+ * @buf:		Pointer to the buffer to store read data
+ * @oob_required:	Caller requires OOB data read to chip->oob_poi
+ * @page:		Page number to read
+ *
+ * Return:	Always return zero
+ */
+static int pl353_nand_read_page_swecc(struct mtd_info *mtd,
+				     struct nand_chip *chip,
+				     uint8_t *buf,  int oob_required, int page)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	uint8_t *ecc_code = chip->buffers->ecccode;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+
+	chip->ecc.read_page_raw(mtd, chip, buf, page, 1);
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+	for (i = 0; i < chip->ecc.total; i++)
+		ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+	eccsteps = chip->ecc.steps;
+	p = buf;
+
+	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		int stat;
+
+		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+		if (stat < 0)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+	}
+	return 0;
+}
+
+/**
  * pl353_nand_select_chip - Select the flash device
  * @mtd:	Pointer to the mtd info structure
  * @chip:	Pointer to the NAND chip info structure
@@ -689,6 +833,8 @@ static int pl353_nand_ecc_init(struct mtd_info *mtd)
 	nand_chip->ecc.read_oob = pl353_nand_read_oob;
 	nand_chip->ecc.write_oob = pl353_nand_write_oob;
 	nand_chip->ecc.strength = 1;
+	nand_chip->ecc.read_page_raw = pl353_nand_read_page_raw;
+	nand_chip->ecc.write_page_raw = pl353_nand_write_page_raw;
 
 	switch (xnand->ecc_mode) {
 	case NAND_ECC_HW:
@@ -715,6 +861,24 @@ static int pl353_nand_ecc_init(struct mtd_info *mtd)
 			nand_chip->ecc.layout = &nand_oob_64;
 
 		break;
+	case NAND_ECC_SOFT:
+		/*
+		 * The software ECC routines won't work with the
+		 * SMC controller
+		 */
+		nand_chip->ecc.mode = NAND_ECC_HW;
+		nand_chip->ecc.calculate = nand_calculate_ecc;
+		nand_chip->ecc.correct = nand_correct_data;
+		nand_chip->ecc.read_page = pl353_nand_read_page_swecc;
+		nand_chip->ecc.write_page = pl353_nand_write_page_swecc;
+		nand_chip->ecc.size = 256;
+		nand_chip->ecc.bytes = 3;
+		/* Bypass the controller ECC block */
+		pl353_smc_set_ecc_pg_size(mtd->dev.parent, mtd->writesize);
+		pl353_smc_set_ecc_mode(mtd->dev.parent,
+					PL353_SMC_ECCMODE_BYPASS);
+
+		break;
 	default:
 		return -ENOTSUPP;
 	}
-- 
1.7.4

[PATCH RFC v4 3/4] nand: pl353: Add ONDIE ECC support

[Punnaiah Choudary Kalluri]

Added ONDIE ECC support. Currently this ecc mode is supported for
specific micron parts with oob size 64 bytes.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
---
Changes in v4:
- Updated the driver to sync with pl353_smc driver APIs
---
 drivers/mtd/nand/pl353_nand.c |  162 ++++++++++++++++++++++++++++++++++++-----
 1 files changed, 144 insertions(+), 18 deletions(-)

diff --git a/drivers/mtd/nand/pl353_nand.c b/drivers/mtd/nand/pl353_nand.c
index 93dc4ca..5c9b60d 100644
--- a/drivers/mtd/nand/pl353_nand.c
+++ b/drivers/mtd/nand/pl353_nand.c
@@ -140,6 +140,48 @@ static struct nand_ecclayout nand_oob_64 = {
 		 .length = 50} }
 };
 
+static struct nand_ecclayout ondie_nand_oob_64 = {
+	.eccbytes = 32,
+
+	.eccpos = {
+		8, 9, 10, 11, 12, 13, 14, 15,
+		24, 25, 26, 27, 28, 29, 30, 31,
+		40, 41, 42, 43, 44, 45, 46, 47,
+		56, 57, 58, 59, 60, 61, 62, 63
+	},
+
+	.oobfree = {
+		{ .offset = 4, .length = 4 },
+		{ .offset = 20, .length = 4 },
+		{ .offset = 36, .length = 4 },
+		{ .offset = 52, .length = 4 }
+	}
+};
+
+/* Generic flash bbt decriptors */
+static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
+static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 4,
+	.len = 4,
+	.veroffs = 20,
+	.maxblocks = 4,
+	.pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 4,
+	.len = 4,
+	.veroffs = 20,
+	.maxblocks = 4,
+	.pattern = mirror_pattern
+};
+
 /**
  * pl353_nand_calculate_hwecc - Calculate Hardware ECC
  * @mtd:	Pointer to the mtd_info structure
@@ -816,15 +858,74 @@ static int pl353_nand_device_ready(struct mtd_info *mtd)
 }
 
 /**
+ * pl353_nand_detect_ondie_ecc - Get the flash ondie ecc state
+ * @mtd:	Pointer to the mtd_info structure
+ *
+ * This function enables the ondie ecc for the Micron ondie ecc capable devices
+ *
+ * Return:	1 on detect, 0 if fail to detect
+ */
+static int pl353_nand_detect_ondie_ecc(struct mtd_info *mtd)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	u8 maf_id, dev_id, i, get_feature;
+	u8 set_feature[4] = { 0x08, 0x00, 0x00, 0x00 };
+
+	/* Check if On-Die ECC flash */
+	nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+	nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+	/* Read manufacturer and device IDs */
+	maf_id = readb(nand_chip->IO_ADDR_R);
+	dev_id = readb(nand_chip->IO_ADDR_R);
+
+	if ((maf_id == NAND_MFR_MICRON) &&
+	    ((dev_id == 0xf1) || (dev_id == 0xa1) ||
+	     (dev_id == 0xb1) || (dev_id == 0xaa) ||
+	     (dev_id == 0xba) || (dev_id == 0xda) ||
+	     (dev_id == 0xca) || (dev_id == 0xac) ||
+	     (dev_id == 0xbc) || (dev_id == 0xdc) ||
+	     (dev_id == 0xcc) || (dev_id == 0xa3) ||
+	     (dev_id == 0xb3) ||
+	     (dev_id == 0xd3) || (dev_id == 0xc3))) {
+
+		nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
+				   ONDIE_ECC_FEATURE_ADDR, -1);
+		get_feature = readb(nand_chip->IO_ADDR_R);
+
+		if (get_feature & 0x08) {
+			return 1;
+		} else {
+			nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
+					   ONDIE_ECC_FEATURE_ADDR, -1);
+			for (i = 0; i < 4; i++)
+				writeb(set_feature[i], nand_chip->IO_ADDR_W);
+
+			ndelay(1000);
+
+			nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
+					   ONDIE_ECC_FEATURE_ADDR, -1);
+			get_feature = readb(nand_chip->IO_ADDR_R);
+
+			if (get_feature & 0x08)
+				return 1;
+		}
+	}
+
+	return 0;
+}
+
+/**
  * pl353_nand_ecc_init - Initialize the ecc information as per the ecc mode
  * @mtd:	Pointer to the mtd_info structure
+ * @ondie_ecc_state:	ondie ecc status
  *
  * This function initializes the ecc block and functional pointers as per the
  * ecc mode
  *
  * Return:	Zero on success and error on failure.
  */
-static int pl353_nand_ecc_init(struct mtd_info *mtd)
+static int pl353_nand_ecc_init(struct mtd_info *mtd, int ondie_ecc_state)
 {
 	struct nand_chip *nand_chip = mtd->priv;
 	struct pl353_nand_info *xnand =
@@ -838,27 +939,50 @@ static int pl353_nand_ecc_init(struct mtd_info *mtd)
 
 	switch (xnand->ecc_mode) {
 	case NAND_ECC_HW:
-		if (mtd->writesize > 2048) {
+		if ((mtd->writesize > 2048) || ((ondie_ecc_state) &&
+						(mtd->oobsize != 64))) {
 			pr_warn("hardware ECC not possible\n");
 			return -ENOTSUPP;
 		}
 
 		nand_chip->ecc.mode = NAND_ECC_HW;
-		nand_chip->ecc.calculate = pl353_nand_calculate_hwecc;
-		nand_chip->ecc.correct = pl353_nand_correct_data;
-		nand_chip->ecc.hwctl = NULL;
-		nand_chip->ecc.read_page = pl353_nand_read_page_hwecc;
-		nand_chip->ecc.size = PL353_NAND_ECC_SIZE;
-		nand_chip->ecc.write_page = pl353_nand_write_page_hwecc;
-		pl353_smc_set_ecc_pg_size(mtd->dev.parent, mtd->writesize);
-		pl353_smc_set_ecc_mode(mtd->dev.parent, PL353_SMC_ECCMODE_APB);
-		/* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
-		nand_chip->ecc.bytes = 3;
-
-		if (mtd->oobsize == 16)
-			nand_chip->ecc.layout = &nand_oob_16;
-		else
-			nand_chip->ecc.layout = &nand_oob_64;
+		if (ondie_ecc_state) {
+			/* Bypass the controller ECC block */
+			pl353_smc_set_ecc_mode(mtd->dev.parent,
+						PL353_SMC_ECCMODE_BYPASS);
+			nand_chip->ecc.bytes = 0;
+			nand_chip->ecc.layout = &ondie_nand_oob_64;
+			nand_chip->ecc.read_page = pl353_nand_read_page_raw;
+			nand_chip->ecc.write_page = pl353_nand_write_page_raw;
+			nand_chip->ecc.size = mtd->writesize;
+			/*
+			 * On-Die ECC spare bytes offset 8 is used for ECC codes
+			 * Use the BBT pattern descriptors
+			 */
+			nand_chip->bbt_td = &bbt_main_descr;
+			nand_chip->bbt_md = &bbt_mirror_descr;
+		} else {
+			nand_chip->ecc.calculate = pl353_nand_calculate_hwecc;
+			nand_chip->ecc.correct = pl353_nand_correct_data;
+			nand_chip->ecc.hwctl = NULL;
+			nand_chip->ecc.read_page = pl353_nand_read_page_hwecc;
+			nand_chip->ecc.size = PL353_NAND_ECC_SIZE;
+			nand_chip->ecc.write_page = pl353_nand_write_page_hwecc;
+			pl353_smc_set_ecc_pg_size(mtd->dev.parent,
+							mtd->writesize);
+			pl353_smc_set_ecc_mode(mtd->dev.parent,
+							PL353_SMC_ECCMODE_APB);
+			/*
+			 * Hardware ECC generates 3 bytes ECC code for each
+			 * 512 bytes
+			 */
+			nand_chip->ecc.bytes = 3;
+
+			if (mtd->oobsize == 16)
+				nand_chip->ecc.layout = &nand_oob_16;
+			else
+				nand_chip->ecc.layout = &nand_oob_64;
+		}
 
 		break;
 	case NAND_ECC_SOFT:
@@ -901,6 +1025,7 @@ static int pl353_nand_probe(struct platform_device *pdev)
 	struct nand_chip *nand_chip;
 	struct resource *res;
 	struct mtd_part_parser_data ppdata;
+	int ondie_ecc_state;
 
 	xnand = devm_kzalloc(&pdev->dev, sizeof(*xnand), GFP_KERNEL);
 	if (!xnand)
@@ -944,6 +1069,7 @@ static int pl353_nand_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, xnand);
 
+	ondie_ecc_state = pl353_nand_detect_ondie_ecc(mtd);
 	/* first scan to find the device and get the page size */
 	if (nand_scan_ident(mtd, 1, NULL)) {
 		dev_err(&pdev->dev, "nand_scan_ident for NAND failed\n");
@@ -954,7 +1080,7 @@ static int pl353_nand_probe(struct platform_device *pdev)
 	if (xnand->ecc_mode < 0)
 		xnand->ecc_mode = NAND_ECC_HW;
 
-	if (pl353_nand_ecc_init(mtd))
+	if (pl353_nand_ecc_init(mtd, ondie_ecc_state))
 		return -ENOTSUPP;
 
 	if (nand_chip->options & NAND_BUSWIDTH_16)
-- 
1.7.4

Re: [PATCH RFC v4 3/4] nand: pl353: Add ONDIE ECC support

[Brian Norris]

Hi Punnaiah,

I haven't looked too closely at everything here, but a few comments:

On Mon, Jul 28, 2014 at 09:01:39PM +0530, Punnaiah Choudary Kalluri wrote:
> Added ONDIE ECC support. Currently this ecc mode is supported for
> specific micron parts with oob size 64 bytes.
> 
> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> ---
> Changes in v4:
> - Updated the driver to sync with pl353_smc driver APIs
> ---
>  drivers/mtd/nand/pl353_nand.c |  162 ++++++++++++++++++++++++++++++++++++-----
>  1 files changed, 144 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/mtd/nand/pl353_nand.c b/drivers/mtd/nand/pl353_nand.c
> index 93dc4ca..5c9b60d 100644
> --- a/drivers/mtd/nand/pl353_nand.c
> +++ b/drivers/mtd/nand/pl353_nand.c
> @@ -140,6 +140,48 @@ static struct nand_ecclayout nand_oob_64 = {
>  		 .length = 50} }
>  };
>  
> +static struct nand_ecclayout ondie_nand_oob_64 = {
> +	.eccbytes = 32,
> +
> +	.eccpos = {
> +		8, 9, 10, 11, 12, 13, 14, 15,
> +		24, 25, 26, 27, 28, 29, 30, 31,
> +		40, 41, 42, 43, 44, 45, 46, 47,
> +		56, 57, 58, 59, 60, 61, 62, 63
> +	},
> +
> +	.oobfree = {
> +		{ .offset = 4, .length = 4 },
> +		{ .offset = 20, .length = 4 },
> +		{ .offset = 36, .length = 4 },
> +		{ .offset = 52, .length = 4 }
> +	}
> +};
> +
> +/* Generic flash bbt decriptors */
> +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
> +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
> +
> +static struct nand_bbt_descr bbt_main_descr = {
> +	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
> +		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
> +	.offs = 4,
> +	.len = 4,
> +	.veroffs = 20,
> +	.maxblocks = 4,
> +	.pattern = bbt_pattern
> +};
> +
> +static struct nand_bbt_descr bbt_mirror_descr = {
> +	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
> +		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
> +	.offs = 4,
> +	.len = 4,
> +	.veroffs = 20,
> +	.maxblocks = 4,
> +	.pattern = mirror_pattern
> +};

Why do you need a custom BBT descriptor? It's much better to use the
standard ones. Perhaps you just want the NAND_BBT_NO_OOB_BBM option, so
you get the bbt_{main,mirror}_no_oob_descr structs from nand_bbt.c.

> +
>  /**
>   * pl353_nand_calculate_hwecc - Calculate Hardware ECC
>   * @mtd:	Pointer to the mtd_info structure
> @@ -816,15 +858,74 @@ static int pl353_nand_device_ready(struct mtd_info *mtd)
>  }
>  
>  /**
> + * pl353_nand_detect_ondie_ecc - Get the flash ondie ecc state
> + * @mtd:	Pointer to the mtd_info structure
> + *
> + * This function enables the ondie ecc for the Micron ondie ecc capable devices
> + *
> + * Return:	1 on detect, 0 if fail to detect
> + */
> +static int pl353_nand_detect_ondie_ecc(struct mtd_info *mtd)

No. On-die ECC support should not be added to a specific NAND driver; it
needs to be written generically as part of nand_base. There have been
recent attempts to do this for Toshiba (try searching the linux-mtd
archives, in the last 4 months or so), but they fell a little short. I'd
rather start with a nand_base approach though.

> +{
> +	struct nand_chip *nand_chip = mtd->priv;
> +	u8 maf_id, dev_id, i, get_feature;
> +	u8 set_feature[4] = { 0x08, 0x00, 0x00, 0x00 };
> +
> +	/* Check if On-Die ECC flash */
> +	nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
> +	nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
> +
> +	/* Read manufacturer and device IDs */
> +	maf_id = readb(nand_chip->IO_ADDR_R);
> +	dev_id = readb(nand_chip->IO_ADDR_R);
> +
> +	if ((maf_id == NAND_MFR_MICRON) &&
> +	    ((dev_id == 0xf1) || (dev_id == 0xa1) ||
> +	     (dev_id == 0xb1) || (dev_id == 0xaa) ||
> +	     (dev_id == 0xba) || (dev_id == 0xda) ||
> +	     (dev_id == 0xca) || (dev_id == 0xac) ||
> +	     (dev_id == 0xbc) || (dev_id == 0xdc) ||
> +	     (dev_id == 0xcc) || (dev_id == 0xa3) ||
> +	     (dev_id == 0xb3) ||
> +	     (dev_id == 0xd3) || (dev_id == 0xc3))) {

So you're writing this with a list of device IDs? Would it make more
sense to use the ONFI parameters?

> +
> +		nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
> +				   ONDIE_ECC_FEATURE_ADDR, -1);
> +		get_feature = readb(nand_chip->IO_ADDR_R);
> +
> +		if (get_feature & 0x08) {
> +			return 1;
> +		} else {
> +			nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
> +					   ONDIE_ECC_FEATURE_ADDR, -1);
> +			for (i = 0; i < 4; i++)
> +				writeb(set_feature[i], nand_chip->IO_ADDR_W);
> +
> +			ndelay(1000);
> +
> +			nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
> +					   ONDIE_ECC_FEATURE_ADDR, -1);
> +			get_feature = readb(nand_chip->IO_ADDR_R);
> +
> +			if (get_feature & 0x08)
> +				return 1;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +/**
>   * pl353_nand_ecc_init - Initialize the ecc information as per the ecc mode
>   * @mtd:	Pointer to the mtd_info structure
> + * @ondie_ecc_state:	ondie ecc status
>   *
>   * This function initializes the ecc block and functional pointers as per the
>   * ecc mode
>   *
>   * Return:	Zero on success and error on failure.
>   */
> -static int pl353_nand_ecc_init(struct mtd_info *mtd)
> +static int pl353_nand_ecc_init(struct mtd_info *mtd, int ondie_ecc_state)
>  {
>  	struct nand_chip *nand_chip = mtd->priv;
>  	struct pl353_nand_info *xnand =
> @@ -838,27 +939,50 @@ static int pl353_nand_ecc_init(struct mtd_info *mtd)
>  
>  	switch (xnand->ecc_mode) {
>  	case NAND_ECC_HW:
> -		if (mtd->writesize > 2048) {
> +		if ((mtd->writesize > 2048) || ((ondie_ecc_state) &&
> +						(mtd->oobsize != 64))) {
>  			pr_warn("hardware ECC not possible\n");
>  			return -ENOTSUPP;
>  		}
>  
>  		nand_chip->ecc.mode = NAND_ECC_HW;
> -		nand_chip->ecc.calculate = pl353_nand_calculate_hwecc;
> -		nand_chip->ecc.correct = pl353_nand_correct_data;
> -		nand_chip->ecc.hwctl = NULL;
> -		nand_chip->ecc.read_page = pl353_nand_read_page_hwecc;
> -		nand_chip->ecc.size = PL353_NAND_ECC_SIZE;
> -		nand_chip->ecc.write_page = pl353_nand_write_page_hwecc;
> -		pl353_smc_set_ecc_pg_size(mtd->dev.parent, mtd->writesize);
> -		pl353_smc_set_ecc_mode(mtd->dev.parent, PL353_SMC_ECCMODE_APB);
> -		/* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
> -		nand_chip->ecc.bytes = 3;
> -
> -		if (mtd->oobsize == 16)
> -			nand_chip->ecc.layout = &nand_oob_16;
> -		else
> -			nand_chip->ecc.layout = &nand_oob_64;
> +		if (ondie_ecc_state) {
> +			/* Bypass the controller ECC block */
> +			pl353_smc_set_ecc_mode(mtd->dev.parent,
> +						PL353_SMC_ECCMODE_BYPASS);
> +			nand_chip->ecc.bytes = 0;
> +			nand_chip->ecc.layout = &ondie_nand_oob_64;
> +			nand_chip->ecc.read_page = pl353_nand_read_page_raw;
> +			nand_chip->ecc.write_page = pl353_nand_write_page_raw;
> +			nand_chip->ecc.size = mtd->writesize;
> +			/*
> +			 * On-Die ECC spare bytes offset 8 is used for ECC codes
> +			 * Use the BBT pattern descriptors
> +			 */
> +			nand_chip->bbt_td = &bbt_main_descr;
> +			nand_chip->bbt_md = &bbt_mirror_descr;
> +		} else {
> +			nand_chip->ecc.calculate = pl353_nand_calculate_hwecc;
> +			nand_chip->ecc.correct = pl353_nand_correct_data;
> +			nand_chip->ecc.hwctl = NULL;
> +			nand_chip->ecc.read_page = pl353_nand_read_page_hwecc;
> +			nand_chip->ecc.size = PL353_NAND_ECC_SIZE;
> +			nand_chip->ecc.write_page = pl353_nand_write_page_hwecc;
> +			pl353_smc_set_ecc_pg_size(mtd->dev.parent,
> +							mtd->writesize);
> +			pl353_smc_set_ecc_mode(mtd->dev.parent,
> +							PL353_SMC_ECCMODE_APB);
> +			/*
> +			 * Hardware ECC generates 3 bytes ECC code for each
> +			 * 512 bytes
> +			 */
> +			nand_chip->ecc.bytes = 3;
> +
> +			if (mtd->oobsize == 16)
> +				nand_chip->ecc.layout = &nand_oob_16;
> +			else
> +				nand_chip->ecc.layout = &nand_oob_64;
> +		}
>  
>  		break;
>  	case NAND_ECC_SOFT:
> @@ -901,6 +1025,7 @@ static int pl353_nand_probe(struct platform_device *pdev)
>  	struct nand_chip *nand_chip;
>  	struct resource *res;
>  	struct mtd_part_parser_data ppdata;
> +	int ondie_ecc_state;
>  
>  	xnand = devm_kzalloc(&pdev->dev, sizeof(*xnand), GFP_KERNEL);
>  	if (!xnand)
> @@ -944,6 +1069,7 @@ static int pl353_nand_probe(struct platform_device *pdev)
>  
>  	platform_set_drvdata(pdev, xnand);
>  
> +	ondie_ecc_state = pl353_nand_detect_ondie_ecc(mtd);
>  	/* first scan to find the device and get the page size */
>  	if (nand_scan_ident(mtd, 1, NULL)) {
>  		dev_err(&pdev->dev, "nand_scan_ident for NAND failed\n");
> @@ -954,7 +1080,7 @@ static int pl353_nand_probe(struct platform_device *pdev)
>  	if (xnand->ecc_mode < 0)
>  		xnand->ecc_mode = NAND_ECC_HW;
>  
> -	if (pl353_nand_ecc_init(mtd))
> +	if (pl353_nand_ecc_init(mtd, ondie_ecc_state))
>  		return -ENOTSUPP;
>  
>  	if (nand_chip->options & NAND_BUSWIDTH_16)

Brian

Re: [PATCH RFC v4 3/4] nand: pl353: Add ONDIE ECC support

[Brian Norris]

On Thu, Jul 31, 2014 at 12:06:43AM -0700, Brian Norris wrote:
> On Mon, Jul 28, 2014 at 09:01:39PM +0530, Punnaiah Choudary Kalluri wrote:
> > +/* Generic flash bbt decriptors */
> > +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
> > +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
> > +
> > +static struct nand_bbt_descr bbt_main_descr = {
> > +	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
> > +		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
> > +	.offs = 4,
> > +	.len = 4,
> > +	.veroffs = 20,
> > +	.maxblocks = 4,
> > +	.pattern = bbt_pattern
> > +};
> > +
> > +static struct nand_bbt_descr bbt_mirror_descr = {
> > +	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
> > +		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
> > +	.offs = 4,
> > +	.len = 4,
> > +	.veroffs = 20,
> > +	.maxblocks = 4,
> > +	.pattern = mirror_pattern
> > +};
> 
> Why do you need a custom BBT descriptor? It's much better to use the
> standard ones. Perhaps you just want the NAND_BBT_NO_OOB_BBM option, so
> you get the bbt_{main,mirror}_no_oob_descr structs from nand_bbt.c.

I see you answered this:

 http://lists.infradead.org/pipermail/linux-mtd/2014-April/053451.html

That's unfortunate.

Brian

RE: [PATCH RFC v4 3/4] nand: pl353: Add ONDIE ECC support

[Punnaiah Choudary Kalluri]

Hi Boris,

>-----Original Message-----
>From: Brian Norris [mailto:computersforpeace@gmail.com]
>Sent: Thursday, July 31, 2014 12:37 PM
>To: Punnaiah Choudary Kalluri
>Cc: robh+dt@kernel.org; pawel.moll@arm.com; mark.rutland@arm.com;
>ijc+devicetree@hellion.org.uk; galak@codeaurora.org; rob@landley.net;
>Michal Simek; grant.likely@linaro.org; gregkh@linuxfoundation.org;
>jason@lakedaemon.net; ezequiel.garcia@free-electrons.com;
>arnd@arndb.de; dwmw2@infradead.org; artem.bityutskiy@linux.intel.com;
>pekon@ti.com; jussi.kivilinna@iki.fi; acourbot@nvidia.com;
>ivan.khoronzhuk@ti.com; joern@logfs.org; devicetree@vger.kernel.org;
>linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
>mtd@lists.infradead.org; kpc528@gmail.com;
>kalluripunnaiahchoudary@gmail.com; Anirudha Sarangi; Srikanth Vemula;
>Punnaiah Choudary Kalluri
>Subject: Re: [PATCH RFC v4 3/4] nand: pl353: Add ONDIE ECC support
>
>Hi Punnaiah,
>
>I haven't looked too closely at everything here, but a few comments:
>
>On Mon, Jul 28, 2014 at 09:01:39PM +0530, Punnaiah Choudary Kalluri wrote:
>> Added ONDIE ECC support. Currently this ecc mode is supported for
>> specific micron parts with oob size 64 bytes.
>>
>> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
>> ---
>> Changes in v4:
>> - Updated the driver to sync with pl353_smc driver APIs
>> ---
>>  drivers/mtd/nand/pl353_nand.c |  162
>++++++++++++++++++++++++++++++++++++-----
>>  1 files changed, 144 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/pl353_nand.c
>b/drivers/mtd/nand/pl353_nand.c
>> index 93dc4ca..5c9b60d 100644
>> --- a/drivers/mtd/nand/pl353_nand.c
>> +++ b/drivers/mtd/nand/pl353_nand.c
>> @@ -140,6 +140,48 @@ static struct nand_ecclayout nand_oob_64 = {
>>  		 .length = 50} }
>>  };
>>
>> +static struct nand_ecclayout ondie_nand_oob_64 = {
>> +	.eccbytes = 32,
>> +
>> +	.eccpos = {
>> +		8, 9, 10, 11, 12, 13, 14, 15,
>> +		24, 25, 26, 27, 28, 29, 30, 31,
>> +		40, 41, 42, 43, 44, 45, 46, 47,
>> +		56, 57, 58, 59, 60, 61, 62, 63
>> +	},
>> +
>> +	.oobfree = {
>> +		{ .offset = 4, .length = 4 },
>> +		{ .offset = 20, .length = 4 },
>> +		{ .offset = 36, .length = 4 },
>> +		{ .offset = 52, .length = 4 }
>> +	}
>> +};
>> +
>> +/* Generic flash bbt decriptors */
>> +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
>> +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
>> +
>> +static struct nand_bbt_descr bbt_main_descr = {
>> +	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
>NAND_BBT_WRITE
>> +		| NAND_BBT_2BIT | NAND_BBT_VERSION |
>NAND_BBT_PERCHIP,
>> +	.offs = 4,
>> +	.len = 4,
>> +	.veroffs = 20,
>> +	.maxblocks = 4,
>> +	.pattern = bbt_pattern
>> +};
>> +
>> +static struct nand_bbt_descr bbt_mirror_descr = {
>> +	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
>NAND_BBT_WRITE
>> +		| NAND_BBT_2BIT | NAND_BBT_VERSION |
>NAND_BBT_PERCHIP,
>> +	.offs = 4,
>> +	.len = 4,
>> +	.veroffs = 20,
>> +	.maxblocks = 4,
>> +	.pattern = mirror_pattern
>> +};
>
>Why do you need a custom BBT descriptor? It's much better to use the
>standard ones. Perhaps you just want the NAND_BBT_NO_OOB_BBM option,
>so
>you get the bbt_{main,mirror}_no_oob_descr structs from nand_bbt.c.
>
>> +
>>  /**
>>   * pl353_nand_calculate_hwecc - Calculate Hardware ECC
>>   * @mtd:	Pointer to the mtd_info structure
>> @@ -816,15 +858,74 @@ static int pl353_nand_device_ready(struct
>mtd_info *mtd)
>>  }
>>
>>  /**
>> + * pl353_nand_detect_ondie_ecc - Get the flash ondie ecc state
>> + * @mtd:	Pointer to the mtd_info structure
>> + *
>> + * This function enables the ondie ecc for the Micron ondie ecc capable
>devices
>> + *
>> + * Return:	1 on detect, 0 if fail to detect
>> + */
>> +static int pl353_nand_detect_ondie_ecc(struct mtd_info *mtd)
>
>No. On-die ECC support should not be added to a specific NAND driver; it
>needs to be written generically as part of nand_base. There have been
>recent attempts to do this for Toshiba (try searching the linux-mtd
>archives, in the last 4 months or so), but they fell a little short. I'd
>rather start with a nand_base approach though.

Ok. In this case, time being I will drop this particular patch and see the
Previous implementations and come up with generic solution.
Hope this will be ok for you.

Also I request your time for reviewing the other patches in this series.
 So that at least first i can push the basic version and start work on
Enhancements. 

>
>> +{
>> +	struct nand_chip *nand_chip = mtd->priv;
>> +	u8 maf_id, dev_id, i, get_feature;
>> +	u8 set_feature[4] = { 0x08, 0x00, 0x00, 0x00 };
>> +
>> +	/* Check if On-Die ECC flash */
>> +	nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
>> +	nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
>> +
>> +	/* Read manufacturer and device IDs */
>> +	maf_id = readb(nand_chip->IO_ADDR_R);
>> +	dev_id = readb(nand_chip->IO_ADDR_R);
>> +
>> +	if ((maf_id == NAND_MFR_MICRON) &&
>> +	    ((dev_id == 0xf1) || (dev_id == 0xa1) ||
>> +	     (dev_id == 0xb1) || (dev_id == 0xaa) ||
>> +	     (dev_id == 0xba) || (dev_id == 0xda) ||
>> +	     (dev_id == 0xca) || (dev_id == 0xac) ||
>> +	     (dev_id == 0xbc) || (dev_id == 0xdc) ||
>> +	     (dev_id == 0xcc) || (dev_id == 0xa3) ||
>> +	     (dev_id == 0xb3) ||
>> +	     (dev_id == 0xd3) || (dev_id == 0xc3))) {
>
>So you're writing this with a list of device IDs? Would it make more
>sense to use the ONFI parameters?

Yes,  Checking the flash ondie ecc status using ONFI parameter is ideal,
But if the flash supports ondie ecc and if it is not enabled, then this driver
Is enabling it. In order to use ONFI parameters, the nand_scan_ident function
Should be called and after that function, the read_byte function is pointing to
the nand_read_byte16 for 16 bit nand flash devices and causing issues while
enabling the ondie ecc. Probably I will recheck again or as discussed above
I will come up with generic solution.

Thanks for the  review.

Regards
Punnaiah
>
>> +
>> +		nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
>> +				   ONDIE_ECC_FEATURE_ADDR, -1);
>> +		get_feature = readb(nand_chip->IO_ADDR_R);
>> +
>> +		if (get_feature & 0x08) {
>> +			return 1;
>> +		} else {
>> +			nand_chip->cmdfunc(mtd,
>NAND_CMD_SET_FEATURES,
>> +					   ONDIE_ECC_FEATURE_ADDR, -1);
>> +			for (i = 0; i < 4; i++)
>> +				writeb(set_feature[i], nand_chip-
>>IO_ADDR_W);
>> +
>> +			ndelay(1000);
>> +
>> +			nand_chip->cmdfunc(mtd,
>NAND_CMD_GET_FEATURES,
>> +					   ONDIE_ECC_FEATURE_ADDR, -1);
>> +			get_feature = readb(nand_chip->IO_ADDR_R);
>> +
>> +			if (get_feature & 0x08)
>> +				return 1;
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +/**
>>   * pl353_nand_ecc_init - Initialize the ecc information as per the ecc mode
>>   * @mtd:	Pointer to the mtd_info structure
>> + * @ondie_ecc_state:	ondie ecc status
>>   *
>>   * This function initializes the ecc block and functional pointers as per the
>>   * ecc mode
>>   *
>>   * Return:	Zero on success and error on failure.
>>   */
>> -static int pl353_nand_ecc_init(struct mtd_info *mtd)
>> +static int pl353_nand_ecc_init(struct mtd_info *mtd, int ondie_ecc_state)
>>  {
>>  	struct nand_chip *nand_chip = mtd->priv;
>>  	struct pl353_nand_info *xnand =
>> @@ -838,27 +939,50 @@ static int pl353_nand_ecc_init(struct mtd_info
>*mtd)
>>
>>  	switch (xnand->ecc_mode) {
>>  	case NAND_ECC_HW:
>> -		if (mtd->writesize > 2048) {
>> +		if ((mtd->writesize > 2048) || ((ondie_ecc_state) &&
>> +						(mtd->oobsize != 64))) {
>>  			pr_warn("hardware ECC not possible\n");
>>  			return -ENOTSUPP;
>>  		}
>>
>>  		nand_chip->ecc.mode = NAND_ECC_HW;
>> -		nand_chip->ecc.calculate = pl353_nand_calculate_hwecc;
>> -		nand_chip->ecc.correct = pl353_nand_correct_data;
>> -		nand_chip->ecc.hwctl = NULL;
>> -		nand_chip->ecc.read_page = pl353_nand_read_page_hwecc;
>> -		nand_chip->ecc.size = PL353_NAND_ECC_SIZE;
>> -		nand_chip->ecc.write_page =
>pl353_nand_write_page_hwecc;
>> -		pl353_smc_set_ecc_pg_size(mtd->dev.parent, mtd-
>>writesize);
>> -		pl353_smc_set_ecc_mode(mtd->dev.parent,
>PL353_SMC_ECCMODE_APB);
>> -		/* Hardware ECC generates 3 bytes ECC code for each 512
>bytes */
>> -		nand_chip->ecc.bytes = 3;
>> -
>> -		if (mtd->oobsize == 16)
>> -			nand_chip->ecc.layout = &nand_oob_16;
>> -		else
>> -			nand_chip->ecc.layout = &nand_oob_64;
>> +		if (ondie_ecc_state) {
>> +			/* Bypass the controller ECC block */
>> +			pl353_smc_set_ecc_mode(mtd->dev.parent,
>> +
>	PL353_SMC_ECCMODE_BYPASS);
>> +			nand_chip->ecc.bytes = 0;
>> +			nand_chip->ecc.layout = &ondie_nand_oob_64;
>> +			nand_chip->ecc.read_page =
>pl353_nand_read_page_raw;
>> +			nand_chip->ecc.write_page =
>pl353_nand_write_page_raw;
>> +			nand_chip->ecc.size = mtd->writesize;
>> +			/*
>> +			 * On-Die ECC spare bytes offset 8 is used for ECC
>codes
>> +			 * Use the BBT pattern descriptors
>> +			 */
>> +			nand_chip->bbt_td = &bbt_main_descr;
>> +			nand_chip->bbt_md = &bbt_mirror_descr;
>> +		} else {
>> +			nand_chip->ecc.calculate =
>pl353_nand_calculate_hwecc;
>> +			nand_chip->ecc.correct = pl353_nand_correct_data;
>> +			nand_chip->ecc.hwctl = NULL;
>> +			nand_chip->ecc.read_page =
>pl353_nand_read_page_hwecc;
>> +			nand_chip->ecc.size = PL353_NAND_ECC_SIZE;
>> +			nand_chip->ecc.write_page =
>pl353_nand_write_page_hwecc;
>> +			pl353_smc_set_ecc_pg_size(mtd->dev.parent,
>> +							mtd->writesize);
>> +			pl353_smc_set_ecc_mode(mtd->dev.parent,
>> +
>	PL353_SMC_ECCMODE_APB);
>> +			/*
>> +			 * Hardware ECC generates 3 bytes ECC code for each
>> +			 * 512 bytes
>> +			 */
>> +			nand_chip->ecc.bytes = 3;
>> +
>> +			if (mtd->oobsize == 16)
>> +				nand_chip->ecc.layout = &nand_oob_16;
>> +			else
>> +				nand_chip->ecc.layout = &nand_oob_64;
>> +		}
>>
>>  		break;
>>  	case NAND_ECC_SOFT:
>> @@ -901,6 +1025,7 @@ static int pl353_nand_probe(struct platform_device
>*pdev)
>>  	struct nand_chip *nand_chip;
>>  	struct resource *res;
>>  	struct mtd_part_parser_data ppdata;
>> +	int ondie_ecc_state;
>>
>>  	xnand = devm_kzalloc(&pdev->dev, sizeof(*xnand), GFP_KERNEL);
>>  	if (!xnand)
>> @@ -944,6 +1069,7 @@ static int pl353_nand_probe(struct platform_device
>*pdev)
>>
>>  	platform_set_drvdata(pdev, xnand);
>>
>> +	ondie_ecc_state = pl353_nand_detect_ondie_ecc(mtd);
>>  	/* first scan to find the device and get the page size */
>>  	if (nand_scan_ident(mtd, 1, NULL)) {
>>  		dev_err(&pdev->dev, "nand_scan_ident for NAND failed\n");
>> @@ -954,7 +1080,7 @@ static int pl353_nand_probe(struct platform_device
>*pdev)
>>  	if (xnand->ecc_mode < 0)
>>  		xnand->ecc_mode = NAND_ECC_HW;
>>
>> -	if (pl353_nand_ecc_init(mtd))
>> +	if (pl353_nand_ecc_init(mtd, ondie_ecc_state))
>>  		return -ENOTSUPP;
>>
>>  	if (nand_chip->options & NAND_BUSWIDTH_16)
>
>Brian

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH RFC v4 4/4] Documentation: nand: pl353: Add documentation for controller and driver

[Punnaiah Choudary Kalluri]

Added notes about the controller and driver

Signed-off-by: Punnaiah Choudary Kalluri <punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
Changes in v4:
- None
---
 Documentation/mtd/nand/pl353-nand.txt |   92 +++++++++++++++++++++++++++++++++
 1 files changed, 92 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/mtd/nand/pl353-nand.txt

diff --git a/Documentation/mtd/nand/pl353-nand.txt b/Documentation/mtd/nand/pl353-nand.txt
new file mode 100644
index 0000000..4deac94
--- /dev/null
+++ b/Documentation/mtd/nand/pl353-nand.txt
@@ -0,0 +1,92 @@
+This documents provides some notes about the ARM pl353 smc controller used in
+Zynq SOC and confined to NAND specific details.
+
+Overview of the controller
+==========================
+	The SMC (PL353) supports two memory interfaces:
+	Interface 0 type SRAM.
+	Interface 1 type NAND.
+	This configuration supports the following configurable options:
+	   . 32-bit or 64-bit AXI data width
+	   . 8-bit, 16-bit, or 32-bit memory data width for interface 0
+	   . 8-bit, or 16-bit memory data width for interface 1
+	   . 1-4 chip selects on each interface
+	   . SLC ECC block for interface 1
+
+For more information, refer the below link for TRM
+http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/
+DDI0380G_smc_pl350_series_r2p1_trm.pdf
+
+NAND memory accesses
+====================
+	. Two phase NAND accesses
+	. NAND command phase transfers
+	. NAND data phase transfers
+
+Two phase NAND accesses
+	The SMC defines two phases of commands when transferring data to or from
+NAND flash.
+
+Command phase
+	Commands and optional address information are written to the NAND flash.
+The command and address can be associated with either a data phase operation to
+write to or read from the array, or a status/ID register transfer.
+
+Data phase
+ Data is either written to or read from the NAND flash. This data can be either
+data transferred to or from the array, or status/ID register information.
+
+NAND AXI address setup
+       AXI address      Command phase      Data phase
+	[31:24]         Chip address       Chip address
+	[23]            NoOfAddCycles_2    Reserved
+	[22]            NoOfAddCycles_1    Reserved
+	[21]            NoOfAddCycles_0    ClearCS
+	[20]            End command valid  End command valid
+	[19]            0                  1
+	[18:11]         End command        End command
+	[10:3]          Start command      [10] ECC Last
+					   [9:3] Reserved
+	[2:0]           Reserved           Reserved
+
+ECC
+===
+    It operates on a number of 512 byte blocks of NAND memory and can be
+programmed to store the ECC codes after the data in memory. For writes,
+the ECC is written to the spare area of the page. For reads, the result of
+a block ECC check are made available to the device driver.
+
+------------------------------------------------------------------------
+|               n * 512 blocks                  | extra  | ecc    |     |
+|                                               | block  | codes  |     |
+------------------------------------------------------------------------
+
+The ECC calculation uses a simple Hamming code, using 1-bit correction 2-bit
+detection. It starts when a valid read or write command with a 512 byte aligned
+address is detected on the memory interface.
+
+Driver details
+==============
+	The NAND driver has dependancy with the pl353_smc memory controller
+driver for intializing the nand timing parameters, bus width, ECC modes,
+control and status information.
+
+Since the controller expects that the chipselect bit should be cleared for the
+last data transfer i.e last 4 data bytes, the existing nandbase page
+read/write routines for soft ecc and ecc none modes will not work. So, inorder
+to make this driver work, it always updates the ecc mode as HW ECC and
+implemented the page read/write functions for supporting the SW ECC.
+
+HW ECC mode:
+	Upto 2K page size is supported and beyond that it retuns
+-ENOSUPPORT error. If the flsh has ONDIE ecc controller then the
+priority has given to the ONDIE ecc controller. Also the current
+implementation has support for upto 64 byte oob area
+
+SW ECC mode:
+	It supports all the pgae sizes. But since, zynq soc bootrom uses
+HW ECC for the devices that have pgae size <=2K so, to avoid any ecc related
+issues during boot, prefer HW ECC over SW ECC.
+
+For devicetree binding information please refer the below dt binding file
+Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
-- 
1.7.4


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Re: [PATCH RFC v4 4/4] Documentation: nand: pl353: Add documentation for controller and driver

[Randy Dunlap]

On 07/28/14 08:31, Punnaiah Choudary Kalluri wrote:
> Added notes about the controller and driver
> 
> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> ---
> Changes in v4:
> - None
> ---
>  Documentation/mtd/nand/pl353-nand.txt |   92 +++++++++++++++++++++++++++++++++
>  1 files changed, 92 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/mtd/nand/pl353-nand.txt
> 
> diff --git a/Documentation/mtd/nand/pl353-nand.txt b/Documentation/mtd/nand/pl353-nand.txt
> new file mode 100644
> index 0000000..4deac94
> --- /dev/null
> +++ b/Documentation/mtd/nand/pl353-nand.txt
> @@ -0,0 +1,92 @@
> +This documents provides some notes about the ARM pl353 smc controller used in

                                                    PL353 SMC

> +Zynq SOC and confined to NAND specific details.

            and is confined to

> +
> +Overview of the controller
> +==========================
> +	The SMC (PL353) supports two memory interfaces:
> +	Interface 0 type SRAM.
> +	Interface 1 type NAND.
> +	This configuration supports the following configurable options:
> +	   . 32-bit or 64-bit AXI data width
> +	   . 8-bit, 16-bit, or 32-bit memory data width for interface 0
> +	   . 8-bit, or 16-bit memory data width for interface 1
> +	   . 1-4 chip selects on each interface
> +	   . SLC ECC block for interface 1
> +
> +For more information, refer the below link for TRM

                         refer to the below link for TRM.

> +http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/
> +DDI0380G_smc_pl350_series_r2p1_trm.pdf
> +
> +NAND memory accesses
> +====================
> +	. Two phase NAND accesses
> +	. NAND command phase transfers
> +	. NAND data phase transfers
> +
> +Two phase NAND accesses
> +	The SMC defines two phases of commands when transferring data to or from
> +NAND flash.
> +
> +Command phase
> +	Commands and optional address information are written to the NAND flash.
> +The command and address can be associated with either a data phase operation to
> +write to or read from the array, or a status/ID register transfer.
> +
> +Data phase
> + Data is either written to or read from the NAND flash. This data can be either
> +data transferred to or from the array, or status/ID register information.
> +
> +NAND AXI address setup
> +       AXI address      Command phase      Data phase
> +	[31:24]         Chip address       Chip address
> +	[23]            NoOfAddCycles_2    Reserved
> +	[22]            NoOfAddCycles_1    Reserved
> +	[21]            NoOfAddCycles_0    ClearCS
> +	[20]            End command valid  End command valid
> +	[19]            0                  1
> +	[18:11]         End command        End command
> +	[10:3]          Start command      [10] ECC Last
> +					   [9:3] Reserved
> +	[2:0]           Reserved           Reserved
> +
> +ECC
> +===
> +    It operates on a number of 512 byte blocks of NAND memory and can be

                                  512-byte blocks

> +programmed to store the ECC codes after the data in memory. For writes,
> +the ECC is written to the spare area of the page. For reads, the result of
> +a block ECC check are made available to the device driver.
> +
> +------------------------------------------------------------------------
> +|               n * 512 blocks                  | extra  | ecc    |     |

                                                              ECC

> +|                                               | block  | codes  |     |
> +------------------------------------------------------------------------
> +
> +The ECC calculation uses a simple Hamming code, using 1-bit correction 2-bit
> +detection. It starts when a valid read or write command with a 512 byte aligned

                                                                  512-byte

> +address is detected on the memory interface.
> +
> +Driver details
> +==============
> +	The NAND driver has dependancy with the pl353_smc memory controller

	                    dependency          PL353 SMC
 
> +driver for intializing the nand timing parameters, bus width, ECC modes,

              initializing the NAND

> +control and status information.
> +
> +Since the controller expects that the chipselect bit should be cleared for the
> +last data transfer i.e last 4 data bytes, the existing nandbase page

             transfer,

> +read/write routines for soft ecc and ecc none modes will not work. So, inorder

                                ECC and ECC                               in order

> +to make this driver work, it always updates the ecc mode as HW ECC and

                                                   ECC

> +implemented the page read/write functions for supporting the SW ECC.

   implements

> +
> +HW ECC mode:
> +	Upto 2K page size is supported and beyond that it retuns

	Up to                                             returns

> +-ENOSUPPORT error. If the flsh has ONDIE ecc controller then the

                             flash          ECC

> +priority has given to the ONDIE ecc controller. Also the current

            is given               ECC

> +implementation has support for upto 64 byte oob area

                                  up to 64-byte OOB area.

> +
> +SW ECC mode:
> +	It supports all the pgae sizes. But since, zynq soc bootrom uses

	                    page sizes, but since Zynq SOC boot ROM

> +HW ECC for the devices that have pgae size <=2K so, to avoid any ecc related

                                    page size <= 2K, to avoid any ECC-related

> +issues during boot, prefer HW ECC over SW ECC.
> +
> +For devicetree binding information please refer the below dt binding file

                                             refer to the below

> +Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> 


-- 
~Randy

Re: [PATCH RFC v4 4/4] Documentation: nand: pl353: Add documentation for controller and driver

[Punnaiah Choudary]

[-- Attachment #1: Type: text/plain, Size: 6470 bytes --]

Hi Randy,

  Thanks for the review. I will fix the below review comments in my next
submission.

Regards,
Punnaiah

On Tue, Jul 29, 2014 at 6:01 AM, Randy Dunlap <rdunlap@infradead.org> wrote:

> On 07/28/14 08:31, Punnaiah Choudary Kalluri wrote:
> > Added notes about the controller and driver
> >
> > Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> > ---
> > Changes in v4:
> > - None
> > ---
> >  Documentation/mtd/nand/pl353-nand.txt |   92
> +++++++++++++++++++++++++++++++++
> >  1 files changed, 92 insertions(+), 0 deletions(-)
> >  create mode 100644 Documentation/mtd/nand/pl353-nand.txt
> >
> > diff --git a/Documentation/mtd/nand/pl353-nand.txt
> b/Documentation/mtd/nand/pl353-nand.txt
> > new file mode 100644
> > index 0000000..4deac94
> > --- /dev/null
> > +++ b/Documentation/mtd/nand/pl353-nand.txt
> > @@ -0,0 +1,92 @@
> > +This documents provides some notes about the ARM pl353 smc controller
> used in
>
>                                                     PL353 SMC
>
> > +Zynq SOC and confined to NAND specific details.
>
>             and is confined to
>
> > +
> > +Overview of the controller
> > +==========================
> > +     The SMC (PL353) supports two memory interfaces:
> > +     Interface 0 type SRAM.
> > +     Interface 1 type NAND.
> > +     This configuration supports the following configurable options:
> > +        . 32-bit or 64-bit AXI data width
> > +        . 8-bit, 16-bit, or 32-bit memory data width for interface 0
> > +        . 8-bit, or 16-bit memory data width for interface 1
> > +        . 1-4 chip selects on each interface
> > +        . SLC ECC block for interface 1
> > +
> > +For more information, refer the below link for TRM
>
>                          refer to the below link for TRM.
>
> > +http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/
> > +DDI0380G_smc_pl350_series_r2p1_trm.pdf
> > +
> > +NAND memory accesses
> > +====================
> > +     . Two phase NAND accesses
> > +     . NAND command phase transfers
> > +     . NAND data phase transfers
> > +
> > +Two phase NAND accesses
> > +     The SMC defines two phases of commands when transferring data to
> or from
> > +NAND flash.
> > +
> > +Command phase
> > +     Commands and optional address information are written to the NAND
> flash.
> > +The command and address can be associated with either a data phase
> operation to
> > +write to or read from the array, or a status/ID register transfer.
> > +
> > +Data phase
> > + Data is either written to or read from the NAND flash. This data can
> be either
> > +data transferred to or from the array, or status/ID register
> information.
> > +
> > +NAND AXI address setup
> > +       AXI address      Command phase      Data phase
> > +     [31:24]         Chip address       Chip address
> > +     [23]            NoOfAddCycles_2    Reserved
> > +     [22]            NoOfAddCycles_1    Reserved
> > +     [21]            NoOfAddCycles_0    ClearCS
> > +     [20]            End command valid  End command valid
> > +     [19]            0                  1
> > +     [18:11]         End command        End command
> > +     [10:3]          Start command      [10] ECC Last
> > +                                        [9:3] Reserved
> > +     [2:0]           Reserved           Reserved
> > +
> > +ECC
> > +===
> > +    It operates on a number of 512 byte blocks of NAND memory and can be
>
>                                   512-byte blocks
>
> > +programmed to store the ECC codes after the data in memory. For writes,
> > +the ECC is written to the spare area of the page. For reads, the result
> of
> > +a block ECC check are made available to the device driver.
> > +
> > +------------------------------------------------------------------------
> > +|               n * 512 blocks                  | extra  | ecc    |
> |
>
>                                                               ECC
>
> > +|                                               | block  | codes  |
> |
> > +------------------------------------------------------------------------
> > +
> > +The ECC calculation uses a simple Hamming code, using 1-bit correction
> 2-bit
> > +detection. It starts when a valid read or write command with a 512 byte
> aligned
>
>                                                                   512-byte
>
> > +address is detected on the memory interface.
> > +
> > +Driver details
> > +==============
> > +     The NAND driver has dependancy with the pl353_smc memory controller
>
>                             dependency          PL353 SMC
>
> > +driver for intializing the nand timing parameters, bus width, ECC modes,
>
>               initializing the NAND
>
> > +control and status information.
> > +
> > +Since the controller expects that the chipselect bit should be cleared
> for the
> > +last data transfer i.e last 4 data bytes, the existing nandbase page
>
>              transfer,
>
> > +read/write routines for soft ecc and ecc none modes will not work. So,
> inorder
>
>                                 ECC and ECC
> in order
>
> > +to make this driver work, it always updates the ecc mode as HW ECC and
>
>                                                    ECC
>
> > +implemented the page read/write functions for supporting the SW ECC.
>
>    implements
>
> > +
> > +HW ECC mode:
> > +     Upto 2K page size is supported and beyond that it retuns
>
>         Up to                                             returns
>
> > +-ENOSUPPORT error. If the flsh has ONDIE ecc controller then the
>
>                              flash          ECC
>
> > +priority has given to the ONDIE ecc controller. Also the current
>
>             is given               ECC
>
> > +implementation has support for upto 64 byte oob area
>
>                                   up to 64-byte OOB area.
>
> > +
> > +SW ECC mode:
> > +     It supports all the pgae sizes. But since, zynq soc bootrom uses
>
>                             page sizes, but since Zynq SOC boot ROM
>
> > +HW ECC for the devices that have pgae size <=2K so, to avoid any ecc
> related
>
>                                     page size <= 2K, to avoid any
> ECC-related
>
> > +issues during boot, prefer HW ECC over SW ECC.
> > +
> > +For devicetree binding information please refer the below dt binding
> file
>
>                                              refer to the below
>
> > +Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
> >
>
>
> --
> ~Randy
>

[-- Attachment #2: Type: text/html, Size: 8915 bytes --]

Re: [PATCH RFC v4 4/4] Documentation: nand: pl353: Add documentation for controller and driver

[Punnaiah Choudary]

Hi Randy,

  Thanks for the review. I will fix the below review comments in my
next submission.

Regards,
Punnaiah

On Tue, Jul 29, 2014 at 6:01 AM, Randy Dunlap <rdunlap@infradead.org> wrote:
> On 07/28/14 08:31, Punnaiah Choudary Kalluri wrote:
>> Added notes about the controller and driver
>>
>> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
>> ---
>> Changes in v4:
>> - None
>> ---
>>  Documentation/mtd/nand/pl353-nand.txt |   92 +++++++++++++++++++++++++++++++++
>>  1 files changed, 92 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/mtd/nand/pl353-nand.txt
>>
>> diff --git a/Documentation/mtd/nand/pl353-nand.txt b/Documentation/mtd/nand/pl353-nand.txt
>> new file mode 100644
>> index 0000000..4deac94
>> --- /dev/null
>> +++ b/Documentation/mtd/nand/pl353-nand.txt
>> @@ -0,0 +1,92 @@
>> +This documents provides some notes about the ARM pl353 smc controller used in
>
>                                                     PL353 SMC
>
>> +Zynq SOC and confined to NAND specific details.
>
>             and is confined to
>
>> +
>> +Overview of the controller
>> +==========================
>> +     The SMC (PL353) supports two memory interfaces:
>> +     Interface 0 type SRAM.
>> +     Interface 1 type NAND.
>> +     This configuration supports the following configurable options:
>> +        . 32-bit or 64-bit AXI data width
>> +        . 8-bit, 16-bit, or 32-bit memory data width for interface 0
>> +        . 8-bit, or 16-bit memory data width for interface 1
>> +        . 1-4 chip selects on each interface
>> +        . SLC ECC block for interface 1
>> +
>> +For more information, refer the below link for TRM
>
>                          refer to the below link for TRM.
>
>> +http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/
>> +DDI0380G_smc_pl350_series_r2p1_trm.pdf
>> +
>> +NAND memory accesses
>> +====================
>> +     . Two phase NAND accesses
>> +     . NAND command phase transfers
>> +     . NAND data phase transfers
>> +
>> +Two phase NAND accesses
>> +     The SMC defines two phases of commands when transferring data to or from
>> +NAND flash.
>> +
>> +Command phase
>> +     Commands and optional address information are written to the NAND flash.
>> +The command and address can be associated with either a data phase operation to
>> +write to or read from the array, or a status/ID register transfer.
>> +
>> +Data phase
>> + Data is either written to or read from the NAND flash. This data can be either
>> +data transferred to or from the array, or status/ID register information.
>> +
>> +NAND AXI address setup
>> +       AXI address      Command phase      Data phase
>> +     [31:24]         Chip address       Chip address
>> +     [23]            NoOfAddCycles_2    Reserved
>> +     [22]            NoOfAddCycles_1    Reserved
>> +     [21]            NoOfAddCycles_0    ClearCS
>> +     [20]            End command valid  End command valid
>> +     [19]            0                  1
>> +     [18:11]         End command        End command
>> +     [10:3]          Start command      [10] ECC Last
>> +                                        [9:3] Reserved
>> +     [2:0]           Reserved           Reserved
>> +
>> +ECC
>> +===
>> +    It operates on a number of 512 byte blocks of NAND memory and can be
>
>                                   512-byte blocks
>
>> +programmed to store the ECC codes after the data in memory. For writes,
>> +the ECC is written to the spare area of the page. For reads, the result of
>> +a block ECC check are made available to the device driver.
>> +
>> +------------------------------------------------------------------------
>> +|               n * 512 blocks                  | extra  | ecc    |     |
>
>                                                               ECC
>
>> +|                                               | block  | codes  |     |
>> +------------------------------------------------------------------------
>> +
>> +The ECC calculation uses a simple Hamming code, using 1-bit correction 2-bit
>> +detection. It starts when a valid read or write command with a 512 byte aligned
>
>                                                                   512-byte
>
>> +address is detected on the memory interface.
>> +
>> +Driver details
>> +==============
>> +     The NAND driver has dependancy with the pl353_smc memory controller
>
>                             dependency          PL353 SMC
>
>> +driver for intializing the nand timing parameters, bus width, ECC modes,
>
>               initializing the NAND
>
>> +control and status information.
>> +
>> +Since the controller expects that the chipselect bit should be cleared for the
>> +last data transfer i.e last 4 data bytes, the existing nandbase page
>
>              transfer,
>
>> +read/write routines for soft ecc and ecc none modes will not work. So, inorder
>
>                                 ECC and ECC                               in order
>
>> +to make this driver work, it always updates the ecc mode as HW ECC and
>
>                                                    ECC
>
>> +implemented the page read/write functions for supporting the SW ECC.
>
>    implements
>
>> +
>> +HW ECC mode:
>> +     Upto 2K page size is supported and beyond that it retuns
>
>         Up to                                             returns
>
>> +-ENOSUPPORT error. If the flsh has ONDIE ecc controller then the
>
>                              flash          ECC
>
>> +priority has given to the ONDIE ecc controller. Also the current
>
>             is given               ECC
>
>> +implementation has support for upto 64 byte oob area
>
>                                   up to 64-byte OOB area.
>
>> +
>> +SW ECC mode:
>> +     It supports all the pgae sizes. But since, zynq soc bootrom uses
>
>                             page sizes, but since Zynq SOC boot ROM
>
>> +HW ECC for the devices that have pgae size <=2K so, to avoid any ecc related
>
>                                     page size <= 2K, to avoid any ECC-related
>
>> +issues during boot, prefer HW ECC over SW ECC.
>> +
>> +For devicetree binding information please refer the below dt binding file
>
>                                              refer to the below
>
>> +Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
>>
>
>
> --
> ~Randy