* [PATCH v2 0/4] Add Mediatek SoC Pinctrl/GPIO driver for MT8135.
@ 2014-09-23 3:39 Hongzhou.Yang
2014-09-23 3:39 ` [PATCH v2 1/4] arm: mediatek: Add config option for mediatek SoCs Hongzhou.Yang
` (4 more replies)
0 siblings, 5 replies; 27+ messages in thread
From: Hongzhou.Yang @ 2014-09-23 3:39 UTC (permalink / raw)
To: Rob Herring, Linus Walleij, Matthias Brugger
Cc: Mark Rutland, devicetree, Vladimir Murzin, Russell King,
srv_heupstream, Pawel Moll, Ian Campbell, Hongzhou Yang,
Catalin Marinas, linux-kernel, Ashwin Chaugule, Sascha Hauer,
Kumar Gala, Grant Likely, Joe.C, dandan.he, linux-arm-kernel
This is v2 of add Mediatek SoC Pinctrl/GPIO drvier for MT8135.
It is based on Joe.C' basic device tree support.
See http://lists.infradead.org/pipermail/linux-arm-kernel/2014-September/288582.html
This driver include common and MT8135 part, other Mediatek SoCs will share the common part,
and MT8135 part only support MT8135. MT8135 has GPIO controller, it includes 203 pins.
Changes in v2:
- According to Heiko Stubner' suggestion, use generic pinconfig.
- Remove pinmux_ops.disable implement.
- Due to limit of message body, move mt8135-pinfunc.h to '[PATCH 3/4] add pinctrl node for MT8135'.
Hongzhou Yang (3):
ARM: mediatek: Add Pinctrl/GPIO driver for mt8135.
dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
ARM: dts: mt8135: Add pinctrl node for mt8135.
Joe.C (1):
arm: mediatek: Add config option for mediatek SoCs.
.../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 98 +
arch/arm/boot/dts/mt8135-pinfunc.h | 1304 +++++++++++
arch/arm/boot/dts/mt8135.dtsi | 11 +
arch/arm/mach-mediatek/Kconfig | 23 +-
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mediatek/Kconfig | 12 +
drivers/pinctrl/mediatek/Makefile | 5 +
drivers/pinctrl/mediatek/pinctrl-mt8135.c | 82 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 792 +++++++
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 95 +
drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h | 2460 ++++++++++++++++++++
include/dt-bindings/pinctrl/mt65xx.h | 23 +
13 files changed, 4904 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
create mode 100644 arch/arm/boot/dts/mt8135-pinfunc.h
create mode 100644 drivers/pinctrl/mediatek/Kconfig
create mode 100644 drivers/pinctrl/mediatek/Makefile
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8135.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
create mode 100644 include/dt-bindings/pinctrl/mt65xx.h
--
1.8.1.1.dirty
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH v2 1/4] arm: mediatek: Add config option for mediatek SoCs. 2014-09-23 3:39 [PATCH v2 0/4] Add Mediatek SoC Pinctrl/GPIO driver for MT8135 Hongzhou.Yang @ 2014-09-23 3:39 ` Hongzhou.Yang 2014-09-23 3:39 ` [PATCH v2 2/4] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135 Hongzhou.Yang ` (3 subsequent siblings) 4 siblings, 0 replies; 27+ messages in thread From: Hongzhou.Yang @ 2014-09-23 3:39 UTC (permalink / raw) To: Rob Herring, Linus Walleij, Matthias Brugger Cc: Mark Rutland, devicetree, Vladimir Murzin, Russell King, srv_heupstream, Pawel Moll, Ian Campbell, Hongzhou Yang, Catalin Marinas, linux-kernel, Ashwin Chaugule, Sascha Hauer, Kumar Gala, Grant Likely, Joe.C, dandan.he, linux-arm-kernel From: "Joe.C" <yingjoe.chen@mediatek.com> Add config options for ARCH_MT6589, ARCH_MT8127, ARCH_MT8135. This allow drivers to isolate support base on these options. Signed-off-by: Joe.C <yingjoe.chen@mediatek.com> --- arch/arm/mach-mediatek/Kconfig | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 2c043a2..25fe6cf 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -1,6 +1,22 @@ -config ARCH_MEDIATEK - bool "Mediatek MT6589 SoC" if ARCH_MULTI_V7 +menuconfig ARCH_MEDIATEK + bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7 select ARM_GIC select MTK_TIMER help - Support for Mediatek Cortex-A7 Quad-Core-SoC MT6589. + Support for Mediatek MT65xx & MT81xx SoCs + +if ARCH_MEDIATEK + +config MACH_MT6589 + bool "MediaTek MT6589 SoCs support" + default ARCH_MEDIATEK + +config MACH_MT8127 + bool "MediaTek MT8127 SoCs support" + default ARCH_MEDIATEK + +config MACH_MT8135 + bool "MediaTek MT8135 SoCs support" + default ARCH_MEDIATEK + +endif -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 2/4] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135. 2014-09-23 3:39 [PATCH v2 0/4] Add Mediatek SoC Pinctrl/GPIO driver for MT8135 Hongzhou.Yang 2014-09-23 3:39 ` [PATCH v2 1/4] arm: mediatek: Add config option for mediatek SoCs Hongzhou.Yang @ 2014-09-23 3:39 ` Hongzhou.Yang 2014-10-02 13:38 ` Linus Walleij 2014-09-23 3:39 ` [PATCH v2 3/4] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx Hongzhou.Yang ` (2 subsequent siblings) 4 siblings, 1 reply; 27+ messages in thread From: Hongzhou.Yang @ 2014-09-23 3:39 UTC (permalink / raw) To: Rob Herring, Linus Walleij, Matthias Brugger Cc: Mark Rutland, devicetree, Vladimir Murzin, Russell King, srv_heupstream, Pawel Moll, Ian Campbell, Hongzhou Yang, Catalin Marinas, linux-kernel, Ashwin Chaugule, Sascha Hauer, Kumar Gala, Grant Likely, Joe.C, dandan.he, linux-arm-kernel From: Hongzhou Yang <hongzhou.yang@mediatek.com> The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs. The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control. This driver include common and mt8135 part. It implements the pinctrl part and gpio part. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> --- arch/arm/mach-mediatek/Kconfig | 1 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/mediatek/Kconfig | 12 + drivers/pinctrl/mediatek/Makefile | 5 + drivers/pinctrl/mediatek/pinctrl-mt8135.c | 82 + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 792 ++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 95 + drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h | 2460 +++++++++++++++++++++++++ include/dt-bindings/pinctrl/mt65xx.h | 23 + 10 files changed, 3472 insertions(+) create mode 100644 drivers/pinctrl/mediatek/Kconfig create mode 100644 drivers/pinctrl/mediatek/Makefile create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8135.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h create mode 100644 include/dt-bindings/pinctrl/mt65xx.h diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 25fe6cf..cd57639 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -1,6 +1,7 @@ menuconfig ARCH_MEDIATEK bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7 select ARM_GIC + select PINCTRL select MTK_TIMER help Support for Mediatek MT65xx & MT81xx SoCs diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index bfd2c2e..0be9314 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -314,6 +314,7 @@ source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" +source "drivers/pinctrl/mediatek/Kconfig" config PINCTRL_XWAY bool diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 05d2275..f9b69a0 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -64,3 +64,4 @@ obj-$(CONFIG_SUPERH) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig new file mode 100644 index 0000000..bae4be6 --- /dev/null +++ b/drivers/pinctrl/mediatek/Kconfig @@ -0,0 +1,12 @@ +if ARCH_MEDIATEK + +config PINCTRL_MTK_COMMON + bool + select PINMUX + select GENERIC_PINCONF + +config PINCTRL_MT8135 + def_bool MACH_MT8135 + select PINCTRL_MTK_COMMON + +endif diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile new file mode 100644 index 0000000..8157dad --- /dev/null +++ b/drivers/pinctrl/mediatek/Makefile @@ -0,0 +1,5 @@ +# Core +obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o + +# SoC Drivers +obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c new file mode 100644 index 0000000..f6367a2 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt8135.h" + +static const struct mt_gpio_devdata mt8135_pinctrl_data = { + .pins = mt_pins_mt8135, + .npins = ARRAY_SIZE(mt_pins_mt8135), + .dir_offset = 0x0000, + .pullen_offset = 0x0200, + .pullsel_offset = 0x0400, + .invser_offset = 0x0600, + .dout_offset = 0x0800, + .din_offset = 0x0A00, + .pinmux_offset = 0x0C00, + .type1_start = 34, + .type1_end = 149, +}; + +static int mt8135_pinctrl_probe(struct platform_device *pdev) +{ + return mt_pctrl_init(pdev, &mt8135_pinctrl_data); +} + +static int mt8135_pinctrl_remove(struct platform_device *pdev) +{ + return mt_pctrl_remove(pdev); +} + + +static struct of_device_id mt8135_pctrl_match[] = { + { + .compatible = "mediatek,mt8135-pinctrl", + }, { + } +}; +MODULE_DEVICE_TABLE(of, mt8135_pctrl_match); + +static struct platform_driver mt_pinctrl_driver = { + .probe = mt8135_pinctrl_probe, + .remove = mt8135_pinctrl_remove, + .driver = { + .name = "mediatek-pinctrl", + .owner = THIS_MODULE, + .of_match_table = mt8135_pctrl_match, + }, +}; + +static int __init mtk_pinctrl_init(void) +{ + return platform_driver_register(&mt_pinctrl_driver); +} + +static void __exit mtk_pinctrl_exit(void) +{ + platform_driver_unregister(&mt_pinctrl_driver); +} + +postcore_initcall(mtk_pinctrl_init); +module_exit(mtk_pinctrl_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); +MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c new file mode 100644 index 0000000..6f7dc73 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -0,0 +1,792 @@ +/* + * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver. + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <dt-bindings/pinctrl/mt65xx.h> + +#include "../pinconf.h" +#include "pinctrl-mtk-common.h" + +#define PINMUX_MAX_VAL 8 +#define MAX_GPIO_MODE_PER_REG 5 +#define GPIO_MODE_BITS 3 + +static const char * const mt_gpio_functions[] = { + "func0", "func1", "func2", "func3", + "func4", "func5", "func6", "func7", +}; + +static void __iomem *mt_get_base_addr(struct mt_pinctrl *pctl, + unsigned long pin) +{ + if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) + return pctl->membase2; + return pctl->membase1; +} + +static void mt_pctrl_write_reg(struct mt_pinctrl *pctl, + unsigned long pin, + u32 reg, u32 d) +{ + writel(d, mt_get_base_addr(pctl, pin) + reg); +} + +static unsigned int mt_get_port(unsigned long pin) +{ + return ((pin >> 4) & 0xf) << 4; +} + +static int mt_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset, + bool input) +{ + unsigned int reg_addr; + unsigned int bit; + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + reg_addr = mt_get_port(offset) + pctl->devdata->dir_offset; + bit = 1 << (offset & 0xf); + + if (input) + reg_addr += (4 << 1); + else + reg_addr += 4; + + writel(bit, pctl->membase1 + reg_addr); + return 0; +} + +static void mt_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + unsigned int reg_addr; + unsigned int bit; + struct mt_pinctrl *pctl = dev_get_drvdata(chip->dev); + + reg_addr = mt_get_port(offset) + pctl->devdata->dout_offset; + bit = 1 << (offset & 0xf); + + if (value) + writel(bit, pctl->membase1 + reg_addr + 4); + else + writel(bit, pctl->membase1 + reg_addr + (4 << 1)); +} + +static int mt_gpio_set_pull_conf(struct pinctrl_dev *pctldev, + unsigned long pin, enum pin_config_param param, + enum pin_config_param argument) +{ + unsigned int reg_pullen, reg_pullsel; + unsigned int bit; + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + int pullen = 0; + int pullsel = 0; + + bit = 1 << (pin & 0xf); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + pullen = 0; + pullsel = 0; + break; + case PIN_CONFIG_BIAS_PULL_UP: + mt_pmx_gpio_set_direction(pctldev, NULL, pin, 1); + pullen = 1; + pullsel = 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + mt_pmx_gpio_set_direction(pctldev, NULL, pin, 1); + pullen = 1; + pullsel = 0; + break; + + case PIN_CONFIG_INPUT_ENABLE: + mt_pmx_gpio_set_direction(pctldev, NULL, pin, 1); + break; + + case PIN_CONFIG_OUTPUT: + mt_pmx_gpio_set_direction(pctldev, NULL, pin, 0); + mt_gpio_set(pctl->chip, pin, argument); + return 0; + + default: + return -EINVAL; + } + + if (pullen) + reg_pullen = mt_get_port(pin) + + pctl->devdata->pullen_offset + 4; + else + reg_pullen = mt_get_port(pin) + + pctl->devdata->pullen_offset + (4 << 1); + + if (pullsel) + reg_pullsel = mt_get_port(pin) + + pctl->devdata->pullsel_offset + 4; + else + reg_pullsel = mt_get_port(pin) + + pctl->devdata->pullsel_offset + (4 << 1); + + mt_pctrl_write_reg(pctl, pin, reg_pullen, bit); + mt_pctrl_write_reg(pctl, pin, reg_pullsel, bit); + return 0; +} + +static int mt_pconf_group_get(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *config) +{ + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *config = pctl->groups[group].config; + + return 0; +} + +static int mt_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, + unsigned long *configs, unsigned num_configs) +{ + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct mt_pinctrl_group *g = &pctl->groups[group]; + int i; + + for (i = 0; i < num_configs; i++) { + mt_gpio_set_pull_conf(pctldev, g->pin, + pinconf_to_config_param(configs[i]), + pinconf_to_config_argument(configs[i])); + + g->config = configs[i]; + } + + return 0; +} + +static const struct pinconf_ops mt_pconf_ops = { + .pin_config_group_get = mt_pconf_group_get, + .pin_config_group_set = mt_pconf_group_set, +}; + +static struct mt_pinctrl_group * +mt_pctrl_find_group_by_pin(struct mt_pinctrl *pctl, u32 pin) +{ + int i; + + for (i = 0; i < pctl->ngroups; i++) { + struct mt_pinctrl_group *grp = pctl->groups + i; + + if (grp->pin == pin) + return grp; + } + + return NULL; +} + +static int mt_pctrl_is_function_valid(struct mt_pinctrl *pctl, + u32 pin_num, u32 fnum) +{ + int i; + + for (i = 0; i < pctl->devdata->npins; i++) { + const struct mt_desc_pin *pin = pctl->devdata->pins + i; + + if (pin->pin.number == pin_num) { + struct mt_desc_function *func = pin->functions + fnum; + + if (func->name) + return 1; + else + return 0; + } + } + + return 0; +} + +static int mt_pctrl_dt_node_to_map_func(struct mt_pinctrl *pctl, u32 pin, + u32 fnum, struct pinctrl_map **maps) +{ + int ret; + struct mt_pinctrl_group *grp; + struct pinctrl_map *map = *maps; + + grp = mt_pctrl_find_group_by_pin(pctl, pin); + if (!grp) { + dev_err(pctl->dev, "unable to match pin %d to group\n", pin); + return -EINVAL; + } + + map->type = PIN_MAP_TYPE_MUX_GROUP; + map->data.mux.group = grp->name; + + ret = mt_pctrl_is_function_valid(pctl, pin, fnum); + if (!ret) { + dev_err(pctl->dev, "invalid mediatek,function %d on pin %d .\n", + fnum, pin); + return -EINVAL; + } + + map->data.mux.function = mt_gpio_functions[fnum]; + (*maps)++; + + return 0; +} + +static int mt_pctrl_dt_node_to_map_config(struct mt_pinctrl *pctl, u32 pin, + unsigned long *configs, unsigned num_configs, + struct pinctrl_map **maps) +{ + struct mt_pinctrl_group *grp; + unsigned long *cfgs; + struct pinctrl_map *map = *maps; + + cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), + GFP_KERNEL); + if (cfgs == NULL) + return -ENOMEM; + + grp = mt_pctrl_find_group_by_pin(pctl, pin); + if (!grp) { + dev_err(pctl->dev, "unable to match pin %d to group\n", pin); + return -EINVAL; + } + + map->type = PIN_MAP_TYPE_CONFIGS_GROUP; + map->data.configs.group_or_pin = grp->name; + map->data.configs.configs = cfgs; + map->data.configs.num_configs = num_configs; + (*maps)++; + + return 0; +} + +static void mt_pctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) { + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) + kfree(map[i].data.configs.configs); + } + + kfree(map); +} + +static int mt_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *node, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct pinctrl_map *maps, *cur_map; + struct property *pins; + u32 pinfunc, pin, func; + int num_pins, num_funcs, maps_per_pin; + unsigned long *configs; + unsigned int num_configs; + bool has_config = 0; + int i, err; + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *map = NULL; + *num_maps = 0; + + pins = of_find_property(node, "mediatek,pinfunc", NULL); + if (!pins) { + dev_err(pctl->dev, "missing mediatek,pinfunc property in node %s .\n", + node->name); + return -EINVAL; + } + + err = pinconf_generic_parse_dt_config(node, &configs, &num_configs); + if (num_configs) + has_config = 1; + + num_pins = pins->length / sizeof(u32); + num_funcs = num_pins; + + maps_per_pin = 0; + if (num_funcs) + maps_per_pin++; + if (has_config && num_pins >= 1) + maps_per_pin++; + + cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps), + GFP_KERNEL); + if (!maps) + return -ENOMEM; + + for (i = 0; i < num_pins; i++) { + err = of_property_read_u32_index(node, "mediatek,pinfunc", + i, &pinfunc); + if (err) + goto fail; + + pin = MT_GET_PIN_NO(pinfunc); + func = MT_GET_PIN_FUNC(pinfunc); + + if (pin >= pctl->devdata->npins || + func >= ARRAY_SIZE(mt_gpio_functions)) { + dev_err(pctl->dev, "invalid mediatek,pinfunc value.\n"); + err = -EINVAL; + goto fail; + } + + err = mt_pctrl_dt_node_to_map_func(pctl, pin, func, &cur_map); + if (err) + goto fail; + + if (has_config) { + err = mt_pctrl_dt_node_to_map_config(pctl, pin, + configs, num_configs, &cur_map); + if (err) + goto fail; + } + } + + *map = maps; + *num_maps = num_pins * maps_per_pin; + return 0; + +fail: + mt_pctrl_dt_free_map(pctldev, maps, num_pins * maps_per_pin); + return err; +} + +static int mt_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->ngroups; +} + +static const char *mt_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->groups[group].name; +} + +static int mt_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *pins = (unsigned *)&pctl->groups[group].pin; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops mt_pctrl_ops = { + .dt_node_to_map = mt_pctrl_dt_node_to_map, + .dt_free_map = mt_pctrl_dt_free_map, + .get_groups_count = mt_pctrl_get_groups_count, + .get_group_name = mt_pctrl_get_group_name, + .get_group_pins = mt_pctrl_get_group_pins, +}; + +static int mt_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(mt_gpio_functions); +} + +static const char *mt_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return mt_gpio_functions[selector]; +} + +static int mt_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctl->grp_names; + *num_groups = pctl->ngroups; + + return 0; +} + +static int mt_gpio_set_mode(struct pinctrl_dev *pctldev, + unsigned long pin, unsigned long mode) +{ + unsigned int reg_addr; + unsigned char bit; + unsigned int val; + unsigned long flags; + unsigned int mask = (1L << GPIO_MODE_BITS) - 1; + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + reg_addr = ((pin / 5) << 4) + pctl->devdata->pinmux_offset; + + spin_lock_irqsave(&pctl->lock, flags); + val = readl(pctl->membase1 + reg_addr); + bit = pin % MAX_GPIO_MODE_PER_REG; + val &= ~(mask << (GPIO_MODE_BITS * bit)); + val |= (mode << (GPIO_MODE_BITS * bit)); + writel(val, pctl->membase1 + reg_addr); + spin_unlock_irqrestore(&pctl->lock, flags); + return 0; +} + +static struct mt_desc_function * +mt_pctrl_desc_find_function_by_number(struct mt_pinctrl *pctl, + const char *pin_name, + unsigned number) +{ + int i; + + for (i = 0; i < pctl->devdata->npins; i++) { + const struct mt_desc_pin *pin = pctl->devdata->pins + i; + + if (!strcmp(pin->pin.name, pin_name)) { + struct mt_desc_function *func = pin->functions; + + return func + number; + } + } + + return NULL; +} + +static struct mt_desc_function * +mt_pctrl_desc_find_irq_by_name(struct mt_pinctrl *pctl, + const char *pin_name) +{ + int i, j; + + for (i = 0; i < pctl->devdata->npins; i++) { + const struct mt_desc_pin *pin = pctl->devdata->pins + i; + + if (!strcmp(pin->pin.name, pin_name)) { + struct mt_desc_function *func = pin->functions; + + for (j = 0; j < PINMUX_MAX_VAL; j++) { + if (func->irqnum != 255) + return func; + + func++; + } + } + } + + return NULL; +} + +static int mt_pmx_enable(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + int ret; + struct mt_desc_function *desc; + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct mt_pinctrl_group *g = pctl->groups + group; + + ret = mt_pctrl_is_function_valid(pctl, g->pin, function); + if (!ret) { + dev_err(pctl->dev, "invaild function %d on group %d .\n", + function, group); + return -EINVAL; + } + + desc = mt_pctrl_desc_find_function_by_number(pctl, g->name, function); + if (!desc) + return -EINVAL; + mt_gpio_set_mode(pctldev, g->pin, desc->muxval); + return 0; +} + +static const struct pinmux_ops mt_pmx_ops = { + .get_functions_count = mt_pmx_get_funcs_cnt, + .get_function_name = mt_pmx_get_func_name, + .get_function_groups = mt_pmx_get_func_groups, + .enable = mt_pmx_enable, + .gpio_set_direction = mt_pmx_gpio_set_direction, +}; + +static int mt_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void mt_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int mt_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int mt_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + return pinctrl_gpio_direction_output(chip->base + offset); +} + +static int mt_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +{ + unsigned int reg_addr; + unsigned int bit; + unsigned int read_val = 0; + + struct mt_pinctrl *pctl = dev_get_drvdata(chip->dev); + + reg_addr = mt_get_port(offset) + pctl->devdata->dir_offset; + bit = 1 << (offset & 0xf); + read_val = readl(pctl->membase1 + reg_addr); + return ((read_val & bit) != 0) ? 1 : 0; +} + +static int mt_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + unsigned int reg_addr; + unsigned int bit; + unsigned int read_val = 0; + struct mt_pinctrl *pctl = dev_get_drvdata(chip->dev); + + if (mt_gpio_get_direction(chip, offset)) + reg_addr = mt_get_port(offset) + pctl->devdata->dout_offset; + else + reg_addr = mt_get_port(offset) + pctl->devdata->din_offset; + + bit = 1 << (offset & 0xf); + read_val = readl(pctl->membase1 + reg_addr); + return ((read_val & bit) != 0) ? 1 : 0; +} + +static int mt_gpio_of_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, + u32 *flags) +{ + int pin; + + pin = gpiospec->args[0]; + + if (pin > (gc->base + gc->ngpio)) + return -EINVAL; + + if (flags) + *flags = gpiospec->args[1]; + + return pin; +} + +static int mt_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct mt_pinctrl *pctl = dev_get_drvdata(chip->dev); + struct mt_pinctrl_group *g = pctl->groups + offset; + struct mt_desc_function *desc = mt_pctrl_desc_find_irq_by_name( + pctl, g->name); + if (!desc) + return -EINVAL; + + mt_gpio_set_mode(pctl->pctl_dev, g->pin, desc->muxval); + return desc->irqnum; +} + +static struct gpio_chip mt_gpio_chip = { + .owner = THIS_MODULE, + .request = mt_gpio_request, + .free = mt_gpio_free, + .direction_input = mt_gpio_direction_input, + .direction_output = mt_gpio_direction_output, + .get = mt_gpio_get, + .set = mt_gpio_set, + .of_xlate = mt_gpio_of_xlate, + .to_irq = mt_gpio_to_irq, + .of_gpio_n_cells = 2, +}; + +static int mt_pctrl_build_state(struct platform_device *pdev) +{ + struct mt_pinctrl *pctl = platform_get_drvdata(pdev); + int i; + + pctl->ngroups = pctl->devdata->npins; + + pctl->groups = devm_kzalloc(&pdev->dev, + pctl->ngroups * sizeof(*pctl->groups), + GFP_KERNEL); + if (!pctl->groups) + return -ENOMEM; + + pctl->grp_names = devm_kzalloc(&pdev->dev, + pctl->ngroups * sizeof(*pctl->grp_names), + GFP_KERNEL); + if (!pctl->grp_names) + return -ENOMEM; + + for (i = 0; i < pctl->devdata->npins; i++) { + const struct mt_desc_pin *pin = pctl->devdata->pins + i; + struct mt_pinctrl_group *group = pctl->groups + i; + const char **func_grp; + + group->name = pin->pin.name; + group->pin = pin->pin.number; + + func_grp = pctl->grp_names; + while (*func_grp) + func_grp++; + + *func_grp = pin->pin.name; + } + + return 0; +} + +static struct pinctrl_desc mt_pctrl_desc = { + .confops = &mt_pconf_ops, + .pctlops = &mt_pctrl_ops, + .pmxops = &mt_pmx_ops, +}; + +int mt_pctrl_init(struct platform_device *pdev, + const struct mt_gpio_devdata *data) +{ + struct pinctrl_pin_desc *pins; + struct mt_pinctrl *pctl; + struct resource *res; + int i, ret; + + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctl); + + spin_lock_init(&pctl->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pctl->membase1 = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctl->membase1)) + return PTR_ERR(pctl->membase1); + + /* Only 8135 has two base addr, other SoCs have only one. */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + pctl->membase2 = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctl->membase2)) + return PTR_ERR(pctl->membase2); + + pctl->devdata = data; + ret = mt_pctrl_build_state(pdev); + if (ret) { + dev_err(&pdev->dev, "build state failed: %d\n", ret); + return -EINVAL; + } + + pins = devm_kzalloc(&pdev->dev, + pctl->devdata->npins * sizeof(*pins), + GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < pctl->devdata->npins; i++) + pins[i] = pctl->devdata->pins[i].pin; + mt_pctrl_desc.name = dev_name(&pdev->dev); + mt_pctrl_desc.owner = THIS_MODULE; + mt_pctrl_desc.pins = pins; + mt_pctrl_desc.npins = pctl->devdata->npins; + pctl->dev = &pdev->dev; + pctl->pctl_dev = pinctrl_register(&mt_pctrl_desc, &pdev->dev, pctl); + if (!pctl->pctl_dev) { + dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); + return -EINVAL; + } + + pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); + if (!pctl->chip) { + ret = -ENOMEM; + goto pctrl_error; + } + + pctl->chip = &mt_gpio_chip; + pctl->chip->ngpio = pctl->devdata->npins; + pctl->chip->label = dev_name(&pdev->dev); + pctl->chip->dev = &pdev->dev; + pctl->chip->base = 0; + + ret = gpiochip_add(pctl->chip); + if (ret) { + ret = -EINVAL; + goto pctrl_error; + } + + for (i = 0; i < pctl->devdata->npins; i++) { + const struct mt_desc_pin *pin = pctl->devdata->pins + i; + + ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), + pin->pin.number, + pin->pin.number, 1); + if (ret) { + ret = -EINVAL; + goto chip_error; + } + } + + return 0; + +chip_error: + if (gpiochip_remove(pctl->chip)) + dev_err(&pdev->dev, "failed to remove gpio chip\n"); + +pctrl_error: + pinctrl_unregister(pctl->pctl_dev); + return ret; +} + +int mt_pctrl_remove(struct platform_device *pdev) +{ + int ret; + struct mt_pinctrl *pctl = platform_get_drvdata(pdev); + + pinctrl_unregister(pctl->pctl_dev); + + ret = gpiochip_remove(pctl->chip); + if (ret) { + dev_err(&pdev->dev, "%s failed, %d\n", __func__, ret); + return ret; + } + + return 0; +} + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); +MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h new file mode 100644 index 0000000..06c7ebd --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PINCTRL_MTK_H +#define __PINCTRL_MTK_H + +#include <linux/pinctrl/pinctrl.h> +#include <linux/spinlock.h> + +struct mt_desc_function { + const char *name; + unsigned char muxval; + unsigned char irqnum; +}; + +struct mt_desc_pin { + struct pinctrl_pin_desc pin; + const char *chip; + struct mt_desc_function *functions; +}; + +#define MT_PIN(_pin, _pad, _chip, ...) \ + { \ + .pin = _pin, \ + .chip = _chip, \ + .functions = (struct mt_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + +#define MT_FUNCTION(_val, _name) \ + { \ + .name = _name, \ + .muxval = _val, \ + .irqnum = 255, \ + } + +#define MT_FUNCTION_IRQ(_val, _name, _irq) \ + { \ + .name = _name, \ + .muxval = _val, \ + .irqnum = _irq, \ + } + +struct mt_pinctrl_group { + const char *name; + unsigned long config; + unsigned pin; +}; + +struct mt_gpio_devdata { + const struct mt_desc_pin *pins; + int npins; + unsigned int dir_offset; + unsigned int ies_offset; + unsigned int pullen_offset; + unsigned int pullsel_offset; + unsigned int drv_offset; + unsigned int invser_offset; + unsigned int dout_offset; + unsigned int din_offset; + unsigned int pinmux_offset; + unsigned short type1_start; + unsigned short type1_end; +}; + +struct mt_pinctrl { + void __iomem *membase1; + void __iomem *membase2; + struct device *dev; + struct gpio_chip *chip; + spinlock_t lock; + struct mt_pinctrl_group *groups; + unsigned ngroups; + const char **grp_names; + struct pinctrl_dev *pctl_dev; + const struct mt_gpio_devdata *devdata; +}; + +int mt_pctrl_init(struct platform_device *pdev, + const struct mt_gpio_devdata *data); + +int mt_pctrl_remove(struct platform_device *pdev); + +#endif /* __PINCTRL_MT65XX_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h new file mode 100644 index 0000000..5f7d82c --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h @@ -0,0 +1,2460 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PINCTRL_MTK_MT8135_H +#define __PINCTRL_MTK_MT8135_H + +#include <linux/pinctrl/pinctrl.h> +#include <pinctrl-mtk-common.h> + +static const struct mt_desc_pin mt_pins_mt8135[] = { + MT_PIN( + PINCTRL_PIN(0, "MSDC0_DAT7"), + "D21", "mt8135", + MT_FUNCTION(0, "GPIO0"), + MT_FUNCTION(1, "MSDC0_DAT7"), + MT_FUNCTION_IRQ(2, "EINT49", 49), + MT_FUNCTION(3, "I2SOUT_DAT"), + MT_FUNCTION(4, "DAC_DAT_OUT"), + MT_FUNCTION(5, "PCM1_DO"), + MT_FUNCTION(6, "SPI1_MO"), + MT_FUNCTION(7, "NALE") + ), + MT_PIN( + PINCTRL_PIN(1, "MSDC0_DAT6"), + "D22", "mt8135", + MT_FUNCTION(0, "GPIO1"), + MT_FUNCTION(1, "MSDC0_DAT6"), + MT_FUNCTION_IRQ(2, "EINT48", 48), + MT_FUNCTION(3, "I2SIN_WS"), + MT_FUNCTION(4, "DAC_WS"), + MT_FUNCTION(5, "PCM1_WS"), + MT_FUNCTION(6, "SPI1_CSN"), + MT_FUNCTION(7, "NCLE") + ), + MT_PIN( + PINCTRL_PIN(2, "MSDC0_DAT5"), + "E22", "mt8135", + MT_FUNCTION(0, "GPIO2"), + MT_FUNCTION(1, "MSDC0_DAT5"), + MT_FUNCTION_IRQ(2, "EINT47", 47), + MT_FUNCTION(3, "I2SIN_CK"), + MT_FUNCTION(4, "DAC_CK"), + MT_FUNCTION(5, "PCM1_CK"), + MT_FUNCTION(6, "SPI1_CLK"), + MT_FUNCTION(7, "NLD4") + ), + MT_PIN( + PINCTRL_PIN(3, "MSDC0_DAT4"), + "F21", "mt8135", + MT_FUNCTION(0, "GPIO3"), + MT_FUNCTION(1, "MSDC0_DAT4"), + MT_FUNCTION_IRQ(2, "EINT46", 46), + MT_FUNCTION(3, "A_FUNC_CK"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "LSCE1B_2X"), + MT_FUNCTION(7, "NLD5") + ), + MT_PIN( + PINCTRL_PIN(4, "MSDC0_CMD"), + "F20", "mt8135", + MT_FUNCTION(0, "GPIO4"), + MT_FUNCTION(1, "MSDC0_CMD"), + MT_FUNCTION_IRQ(2, "EINT41", 41), + MT_FUNCTION(3, "A_FUNC_DOUT[0]"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[0]"), + MT_FUNCTION(6, "LRSTB_2X"), + MT_FUNCTION(7, "NRNB") + ), + MT_PIN( + PINCTRL_PIN(5, "MSDC0_CLK"), + "G18", "mt8135", + MT_FUNCTION(0, "GPIO5"), + MT_FUNCTION(1, "MSDC0_CLK"), + MT_FUNCTION_IRQ(2, "EINT40", 40), + MT_FUNCTION(3, "A_FUNC_DOUT[1]"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[1]"), + MT_FUNCTION(6, "LPTE"), + MT_FUNCTION(7, "NREB") + ), + MT_PIN( + PINCTRL_PIN(6, "MSDC0_DAT3"), + "G21", "mt8135", + MT_FUNCTION(0, "GPIO6"), + MT_FUNCTION(1, "MSDC0_DAT3"), + MT_FUNCTION_IRQ(2, "EINT45", 45), + MT_FUNCTION(3, "A_FUNC_DOUT[2]"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[2]"), + MT_FUNCTION(6, "LSCE0B_2X"), + MT_FUNCTION(7, "NLD7") + ), + MT_PIN( + PINCTRL_PIN(7, "MSDC0_DAT2"), + "E21", "mt8135", + MT_FUNCTION(0, "GPIO7"), + MT_FUNCTION(1, "MSDC0_DAT2"), + MT_FUNCTION_IRQ(2, "EINT44", 44), + MT_FUNCTION(3, "A_FUNC_DOUT[3]"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[3]"), + MT_FUNCTION(6, "LSA0_2X"), + MT_FUNCTION(7, "NLD14") + ), + MT_PIN( + PINCTRL_PIN(8, "MSDC0_DAT1"), + "E23", "mt8135", + MT_FUNCTION(0, "GPIO8"), + MT_FUNCTION(1, "MSDC0_DAT1"), + MT_FUNCTION_IRQ(2, "EINT43", 43), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[4]"), + MT_FUNCTION(6, "LSCK_2X"), + MT_FUNCTION(7, "NLD11") + ), + MT_PIN( + PINCTRL_PIN(9, "MSDC0_DAT0"), + "F22", "mt8135", + MT_FUNCTION(0, "GPIO9"), + MT_FUNCTION(1, "MSDC0_DAT0"), + MT_FUNCTION_IRQ(2, "EINT42", 42), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[5]"), + MT_FUNCTION(6, "LSDA_2X"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(10, "NCEB0"), + "G20", "mt8135", + MT_FUNCTION(0, "GPIO10"), + MT_FUNCTION(1, "NCEB0"), + MT_FUNCTION_IRQ(2, "EINT139", 139), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT4") + ), + MT_PIN( + PINCTRL_PIN(11, "NCEB1"), + "L17", "mt8135", + MT_FUNCTION(0, "GPIO11"), + MT_FUNCTION(1, "NCEB1"), + MT_FUNCTION_IRQ(2, "EINT140", 140), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "USB_DRVVBUS"), + MT_FUNCTION(7, "TESTA_OUT5") + ), + MT_PIN( + PINCTRL_PIN(12, "NRNB"), + "G19", "mt8135", + MT_FUNCTION(0, "GPIO12"), + MT_FUNCTION(1, "NRNB"), + MT_FUNCTION_IRQ(2, "EINT141", 141), + MT_FUNCTION(3, "A_FUNC_DOUT[4]"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT6") + ), + MT_PIN( + PINCTRL_PIN(13, "NCLE"), + "J18", "mt8135", + MT_FUNCTION(0, "GPIO13"), + MT_FUNCTION(1, "NCLE"), + MT_FUNCTION_IRQ(2, "EINT142", 142), + MT_FUNCTION(3, "A_FUNC_DOUT[5]"), + MT_FUNCTION(4, "CM2PDN_1X"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "NALE"), + MT_FUNCTION(7, "TESTA_OUT7") + ), + MT_PIN( + PINCTRL_PIN(14, "NALE"), + "J19", "mt8135", + MT_FUNCTION(0, "GPIO14"), + MT_FUNCTION(1, "NALE"), + MT_FUNCTION_IRQ(2, "EINT143", 143), + MT_FUNCTION(3, "A_FUNC_DOUT[6]"), + MT_FUNCTION(4, "CM2MCLK_1X"), + MT_FUNCTION(5, "IRDA_RXD"), + MT_FUNCTION(6, "NCLE"), + MT_FUNCTION(7, "TESTA_OUT8") + ), + MT_PIN( + PINCTRL_PIN(15, "NREB"), + "L18", "mt8135", + MT_FUNCTION(0, "GPIO15"), + MT_FUNCTION(1, "NREB"), + MT_FUNCTION_IRQ(2, "EINT144", 144), + MT_FUNCTION(3, "A_FUNC_DOUT[7]"), + MT_FUNCTION(4, "CM2RST_1X"), + MT_FUNCTION(5, "IRDA_TXD"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT9") + ), + MT_PIN( + PINCTRL_PIN(16, "NWEB"), + "J20", "mt8135", + MT_FUNCTION(0, "GPIO16"), + MT_FUNCTION(1, "NWEB"), + MT_FUNCTION_IRQ(2, "EINT145", 145), + MT_FUNCTION(3, "A_FUNC_DIN[0]"), + MT_FUNCTION(4, "CM2PCLK_1X"), + MT_FUNCTION(5, "IRDA_PDN"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT10") + ), + MT_PIN( + PINCTRL_PIN(17, "NLD0"), + "K21", "mt8135", + MT_FUNCTION(0, "GPIO17"), + MT_FUNCTION(1, "NLD0"), + MT_FUNCTION_IRQ(2, "EINT146", 146), + MT_FUNCTION(3, "A_FUNC_DIN[1]"), + MT_FUNCTION(4, "CM2DAT_1X[0]"), + MT_FUNCTION(5, "I2SIN_CK"), + MT_FUNCTION(6, "DAC_CK"), + MT_FUNCTION(7, "TESTA_OUT11") + ), + MT_PIN( + PINCTRL_PIN(18, "NLD1"), + "K22", "mt8135", + MT_FUNCTION(0, "GPIO18"), + MT_FUNCTION(1, "NLD1"), + MT_FUNCTION_IRQ(2, "EINT147", 147), + MT_FUNCTION(3, "A_FUNC_DIN[2]"), + MT_FUNCTION(4, "CM2DAT_1X[1]"), + MT_FUNCTION(5, "I2SIN_WS"), + MT_FUNCTION(6, "DAC_WS"), + MT_FUNCTION(7, "TESTA_OUT12") + ), + MT_PIN( + PINCTRL_PIN(19, "NLD2"), + "J21", "mt8135", + MT_FUNCTION(0, "GPIO19"), + MT_FUNCTION(1, "NLD2"), + MT_FUNCTION_IRQ(2, "EINT148", 148), + MT_FUNCTION(3, "A_FUNC_DIN[3]"), + MT_FUNCTION(4, "CM2DAT_1X[2]"), + MT_FUNCTION(5, "I2SOUT_DAT"), + MT_FUNCTION(6, "DAC_DAT_OUT"), + MT_FUNCTION(7, "TESTA_OUT13") + ), + MT_PIN( + PINCTRL_PIN(20, "NLD3"), + "J23", "mt8135", + MT_FUNCTION(0, "GPIO20"), + MT_FUNCTION(1, "NLD3"), + MT_FUNCTION_IRQ(2, "EINT149", 149), + MT_FUNCTION(3, "A_FUNC_DIN[4]"), + MT_FUNCTION(4, "CM2DAT_1X[3]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT14") + ), + MT_PIN( + PINCTRL_PIN(21, "NLD4"), + "J22", "mt8135", + MT_FUNCTION(0, "GPIO21"), + MT_FUNCTION(1, "NLD4"), + MT_FUNCTION_IRQ(2, "EINT150", 150), + MT_FUNCTION(3, "A_FUNC_DIN[5]"), + MT_FUNCTION(4, "CM2DAT_1X[4]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT15") + ), + MT_PIN( + PINCTRL_PIN(22, "NLD5"), + "H21", "mt8135", + MT_FUNCTION(0, "GPIO22"), + MT_FUNCTION(1, "NLD5"), + MT_FUNCTION_IRQ(2, "EINT151", 151), + MT_FUNCTION(3, "A_FUNC_DIN[6]"), + MT_FUNCTION(4, "CM2DAT_1X[5]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT16") + ), + MT_PIN( + PINCTRL_PIN(23, "NLD6"), + "H22", "mt8135", + MT_FUNCTION(0, "GPIO23"), + MT_FUNCTION(1, "NLD6"), + MT_FUNCTION_IRQ(2, "EINT152", 152), + MT_FUNCTION(3, "A_FUNC_DIN[7]"), + MT_FUNCTION(4, "CM2DAT_1X[6]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT17") + ), + MT_PIN( + PINCTRL_PIN(24, "NLD7"), + "H20", "mt8135", + MT_FUNCTION(0, "GPIO24"), + MT_FUNCTION(1, "NLD7"), + MT_FUNCTION_IRQ(2, "EINT153", 153), + MT_FUNCTION(3, "A_FUNC_DIN[8]"), + MT_FUNCTION(4, "CM2DAT_1X[7]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT18") + ), + MT_PIN( + PINCTRL_PIN(25, "NLD8"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO25"), + MT_FUNCTION(1, "NLD8"), + MT_FUNCTION_IRQ(2, "EINT154", 154), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2DAT_1X[8]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(26, "NLD9"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO26"), + MT_FUNCTION(1, "NLD9"), + MT_FUNCTION_IRQ(2, "EINT155", 155), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2DAT_1X[9]"), + MT_FUNCTION(5, "PWM1"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(27, "NLD10"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO27"), + MT_FUNCTION(1, "NLD10"), + MT_FUNCTION_IRQ(2, "EINT156", 156), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2VSYNC_1X"), + MT_FUNCTION(5, "PWM2"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(28, "NLD11"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO28"), + MT_FUNCTION(1, "NLD11"), + MT_FUNCTION_IRQ(2, "EINT157", 157), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2HSYNC_1X"), + MT_FUNCTION(5, "PWM3"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(29, "NLD12"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO29"), + MT_FUNCTION(1, "NLD12"), + MT_FUNCTION_IRQ(2, "EINT158", 158), + MT_FUNCTION(3, "I2SIN_CK"), + MT_FUNCTION(4, "DAC_CK"), + MT_FUNCTION(5, "PCM1_CK"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(30, "NLD13"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO30"), + MT_FUNCTION(1, "NLD13"), + MT_FUNCTION_IRQ(2, "EINT159", 159), + MT_FUNCTION(3, "I2SIN_WS"), + MT_FUNCTION(4, "DAC_WS"), + MT_FUNCTION(5, "PCM1_WS"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(31, "NLD14"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO31"), + MT_FUNCTION(1, "NLD14"), + MT_FUNCTION_IRQ(2, "EINT160", 160), + MT_FUNCTION(3, "I2SOUT_DAT"), + MT_FUNCTION(4, "DAC_DAT_OUT"), + MT_FUNCTION(5, "PCM1_DO"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(32, "NLD15"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO32"), + MT_FUNCTION(1, "NLD15"), + MT_FUNCTION_IRQ(2, "EINT161", 161), + MT_FUNCTION(3, "DISP_PWM"), + MT_FUNCTION(4, "PWM4"), + MT_FUNCTION(5, "PCM1_DI"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(33, "MSDC0_RSTB"), + "G22", "mt8135", + MT_FUNCTION(0, "GPIO33"), + MT_FUNCTION(1, "MSDC0_RSTB"), + MT_FUNCTION_IRQ(2, "EINT50", 50), + MT_FUNCTION(3, "I2SIN_DAT"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "PCM1_DI"), + MT_FUNCTION(6, "SPI1_MI"), + MT_FUNCTION(7, "NLD10") + ), + MT_PIN( + PINCTRL_PIN(34, "IDDIG"), + "N17", "mt8135", + MT_FUNCTION(0, "GPIO34"), + MT_FUNCTION(1, "IDDIG"), + MT_FUNCTION_IRQ(2, "EINT34", 34), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(35, "SCL3"), + "L19", "mt8135", + MT_FUNCTION(0, "GPIO35"), + MT_FUNCTION(1, "SCL3"), + MT_FUNCTION_IRQ(2, "EINT96", 96), + MT_FUNCTION(3, "CLKM6"), + MT_FUNCTION(4, "PWM6"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(36, "SDA3"), + "L20", "mt8135", + MT_FUNCTION(0, "GPIO36"), + MT_FUNCTION(1, "SDA3"), + MT_FUNCTION_IRQ(2, "EINT97", 97), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(37, "AUD_CLK_MOSI"), + "L21", "mt8135", + MT_FUNCTION(0, "GPIO37"), + MT_FUNCTION(1, "AUD_CLK"), + MT_FUNCTION(2, "ADC_CK"), + MT_FUNCTION(3, " HDMI_SDATA0"), + MT_FUNCTION_IRQ(4, "EINT19", 19), + MT_FUNCTION(5, "USB_TEST_IO[6]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT19") + ), + MT_PIN( + PINCTRL_PIN(38, "AUD_DAT_MOSI"), + "L23", "mt8135", + MT_FUNCTION(0, "GPIO38"), + MT_FUNCTION(1, "AUD_DAT_MOSI"), + MT_FUNCTION(2, "ADC_WS"), + MT_FUNCTION(3, "AUD_DAT_MISO"), + MT_FUNCTION_IRQ(4, "EINT21", 21), + MT_FUNCTION(5, "USB_TEST_IO[7]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT20") + ), + MT_PIN( + PINCTRL_PIN(39, "AUD_DAT_MISO"), + "L22", "mt8135", + MT_FUNCTION(0, "GPIO39"), + MT_FUNCTION(1, "AUD_DAT_MISO"), + MT_FUNCTION(2, "ADC_DAT_IN"), + MT_FUNCTION(3, "AUD_DAT_MOSI"), + MT_FUNCTION_IRQ(4, "EINT20", 20), + MT_FUNCTION(5, "USB_TEST_IO[8]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT21") + ), + MT_PIN( + PINCTRL_PIN(40, "DAC_CLK"), + "P21", "mt8135", + MT_FUNCTION(0, "GPIO40"), + MT_FUNCTION(1, "DAC_CK"), + MT_FUNCTION_IRQ(2, "EINT22", 22), + MT_FUNCTION(3, " HDMI_SDATA1"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[9]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT22") + ), + MT_PIN( + PINCTRL_PIN(41, "DAC_WS"), + "N18", "mt8135", + MT_FUNCTION(0, "GPIO41"), + MT_FUNCTION(1, "DAC_WS"), + MT_FUNCTION_IRQ(2, "EINT24", 24), + MT_FUNCTION(3, " HDMI_SDATA2"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[10]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT23") + ), + MT_PIN( + PINCTRL_PIN(42, "DAC_DAT_OUT"), + "N22", "mt8135", + MT_FUNCTION(0, "GPIO42"), + MT_FUNCTION(1, "DAC_DAT_OUT"), + MT_FUNCTION_IRQ(2, "EINT23", 23), + MT_FUNCTION(3, " HDMI_SDATA3"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[11]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT24") + ), + MT_PIN( + PINCTRL_PIN(43, "PWRAP_SPI0_MO"), + "M22", "mt8135", + MT_FUNCTION(0, "GPIO43"), + MT_FUNCTION(1, "PWRAP_SPIDI"), + MT_FUNCTION_IRQ(2, "EINT29", 29), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(44, "PWRAP_SPI0_MI"), + "P23", "mt8135", + MT_FUNCTION(0, "GPIO44"), + MT_FUNCTION(1, "PWRAP_SPIDO"), + MT_FUNCTION_IRQ(2, "EINT28", 28), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(45, "PWRAP_SPI0_CSN"), + "M21", "mt8135", + MT_FUNCTION(0, "GPIO45"), + MT_FUNCTION(1, "PWRAP_SPICS_B_I"), + MT_FUNCTION_IRQ(2, "EINT27", 27), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(46, "PWRAP_SPI0_CLK"), + "P22", "mt8135", + MT_FUNCTION(0, "GPIO46"), + MT_FUNCTION(1, "PWRAP_SPICK_I"), + MT_FUNCTION_IRQ(2, "EINT26", 26), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(47, "PWRAP_EVENT"), + "M23", "mt8135", + MT_FUNCTION(0, "GPIO47"), + MT_FUNCTION(1, "PWRAP_EVENT_IN"), + MT_FUNCTION_IRQ(2, "EINT25", 25), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT2") + ), + MT_PIN( + PINCTRL_PIN(48, "RTC32K_CK"), + "N20", "mt8135", + MT_FUNCTION(0, "GPIO48"), + MT_FUNCTION(1, "RTC32K_CK"), + MT_FUNCTION(2, NULL), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(49, "WATCHDOG"), + "R22", "mt8135", + MT_FUNCTION(0, "GPIO49"), + MT_FUNCTION(1, "WATCHDOG"), + MT_FUNCTION_IRQ(2, "EINT36", 36), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(50, "SRCLKENA"), + "T22", "mt8135", + MT_FUNCTION(0, "GPIO50"), + MT_FUNCTION(1, "SRCLKENA"), + MT_FUNCTION_IRQ(2, "EINT38", 38), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(51, "SRCVOLTEN"), + "T23", "mt8135", + MT_FUNCTION(0, "GPIO51"), + MT_FUNCTION(1, "SRCVOLTEN"), + MT_FUNCTION_IRQ(2, "EINT37", 37), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(52, "EINT0"), + "T21", "mt8135", + MT_FUNCTION(0, "GPIO52"), + MT_FUNCTION_IRQ(1, "EINT0", 0), + MT_FUNCTION(2, "PWM1"), + MT_FUNCTION(3, "CLKM0"), + MT_FUNCTION(4, " SPDIF_OUT"), + MT_FUNCTION(5, "USB_TEST_IO[12]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "USB_SCL") + ), + MT_PIN( + PINCTRL_PIN(53, "URXD2"), + "R18", "mt8135", + MT_FUNCTION(0, "GPIO53"), + MT_FUNCTION(1, "URXD2"), + MT_FUNCTION_IRQ(2, "EINT83", 83), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, " HDMI_LRCK"), + MT_FUNCTION(5, "CLKM3"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "UTXD2") + ), + MT_PIN( + PINCTRL_PIN(54, "UTXD2"), + "R17", "mt8135", + MT_FUNCTION(0, "GPIO54"), + MT_FUNCTION(1, "UTXD2"), + MT_FUNCTION_IRQ(2, "EINT82", 82), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, " HDMI_BCK_OUT"), + MT_FUNCTION(5, "CLKM2"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "URXD2") + ), + MT_PIN( + PINCTRL_PIN(55, "UCTS2"), + "R20", "mt8135", + MT_FUNCTION(0, "GPIO55"), + MT_FUNCTION(1, "UCTS2"), + MT_FUNCTION_IRQ(2, "EINT84", 84), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "PWM1"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "URTS2") + ), + MT_PIN( + PINCTRL_PIN(56, "URTS2"), + "R19", "mt8135", + MT_FUNCTION(0, "GPIO56"), + MT_FUNCTION(1, "URTS2"), + MT_FUNCTION_IRQ(2, "EINT85", 85), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "PWM2"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "UCTS2") + ), + MT_PIN( + PINCTRL_PIN(57, "JTCK"), + "V17", "mt8135", + MT_FUNCTION(0, "GPIO57"), + MT_FUNCTION(1, "JTCK"), + MT_FUNCTION_IRQ(2, "EINT188", 188), + MT_FUNCTION(3, "DSP1_ICK"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(58, "JTDO"), + "T16", "mt8135", + MT_FUNCTION(0, "GPIO58"), + MT_FUNCTION(1, "JTDO"), + MT_FUNCTION_IRQ(2, "EINT190", 190), + MT_FUNCTION(3, "DSP2_IMS"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(59, "JTRST_B"), + "T19", "mt8135", + MT_FUNCTION(0, "GPIO59"), + MT_FUNCTION(1, "JTRST_B"), + MT_FUNCTION_IRQ(2, "EINT0", 0), + MT_FUNCTION(3, "DSP2_ICK"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(60, "JTDI"), + "T18", "mt8135", + MT_FUNCTION(0, "GPIO60"), + MT_FUNCTION(1, "JTDI"), + MT_FUNCTION_IRQ(2, "EINT189", 189), + MT_FUNCTION(3, "DSP1_IMS"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(61, "JRTCK"), + "T20", "mt8135", + MT_FUNCTION(0, "GPIO61"), + MT_FUNCTION(1, "JRTCK"), + MT_FUNCTION_IRQ(2, "EINT187", 187), + MT_FUNCTION(3, "DSP1_ID"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(62, "JTMS"), + "T17", "mt8135", + MT_FUNCTION(0, "GPIO62"), + MT_FUNCTION(1, "JTMS"), + MT_FUNCTION_IRQ(2, "EINT191", 191), + MT_FUNCTION(3, "DSP2_ID"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(63, "MSDC1_INSI"), + "V18", "mt8135", + MT_FUNCTION(0, "GPIO63"), + MT_FUNCTION(1, "MSDC1_INSI"), + MT_FUNCTION_IRQ(2, "EINT57", 57), + MT_FUNCTION(3, "SCL5"), + MT_FUNCTION(4, "PWM6"), + MT_FUNCTION(5, "CLKM5"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTB_OUT6") + ), + MT_PIN( + PINCTRL_PIN(64, "MSDC1_SDWPI"), + "W18", "mt8135", + MT_FUNCTION(0, "GPIO64"), + MT_FUNCTION(1, "MSDC1_SDWPI"), + MT_FUNCTION_IRQ(2, "EINT58", 58), + MT_FUNCTION(3, "SDA5"), + MT_FUNCTION(4, "PWM7"), + MT_FUNCTION(5, "CLKM6"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTB_OUT7") + ), + MT_PIN( + PINCTRL_PIN(65, "MSDC2_INSI"), + "U22", "mt8135", + MT_FUNCTION(0, "GPIO65"), + MT_FUNCTION(1, "MSDC2_INSI"), + MT_FUNCTION_IRQ(2, "EINT65", 65), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[27]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT3") + ), + MT_PIN( + PINCTRL_PIN(66, "MSDC2_SDWPI"), + "U21", "mt8135", + MT_FUNCTION(0, "GPIO66"), + MT_FUNCTION(1, "MSDC2_SDWPI"), + MT_FUNCTION_IRQ(2, "EINT66", 66), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[28]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(67, "URXD4"), + "V23", "mt8135", + MT_FUNCTION(0, "GPIO67"), + MT_FUNCTION(1, "URXD4"), + MT_FUNCTION_IRQ(2, "EINT89", 89), + MT_FUNCTION(3, "URXD1"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "UTXD4"), + MT_FUNCTION(7, "TESTB_OUT10") + ), + MT_PIN( + PINCTRL_PIN(68, "UTXD4"), + "V22", "mt8135", + MT_FUNCTION(0, "GPIO68"), + MT_FUNCTION(1, "UTXD4"), + MT_FUNCTION_IRQ(2, "EINT88", 88), + MT_FUNCTION(3, "UTXD1"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "URXD4"), + MT_FUNCTION(7, "TESTB_OUT11") + ), + MT_PIN( + PINCTRL_PIN(69, "URXD1"), + "W22", "mt8135", + MT_FUNCTION(0, "GPIO69"), + MT_FUNCTION(1, "URXD1"), + MT_FUNCTION_IRQ(2, "EINT79", 79), + MT_FUNCTION(3, "URXD4"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "UTXD1"), + MT_FUNCTION(7, "TESTB_OUT24") + ), + MT_PIN( + PINCTRL_PIN(70, "UTXD1"), + "V21", "mt8135", + MT_FUNCTION(0, "GPIO70"), + MT_FUNCTION(1, "UTXD1"), + MT_FUNCTION_IRQ(2, "EINT78", 78), + MT_FUNCTION(3, "UTXD4"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "URXD1"), + MT_FUNCTION(7, "TESTB_OUT25") + ), + MT_PIN( + PINCTRL_PIN(71, "UCTS1"), + "V19", "mt8135", + MT_FUNCTION(0, "GPIO71"), + MT_FUNCTION(1, "UCTS1"), + MT_FUNCTION_IRQ(2, "EINT80", 80), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "CLKM0"), + MT_FUNCTION(6, "URTS1"), + MT_FUNCTION(7, "TESTB_OUT31") + ), + MT_PIN( + PINCTRL_PIN(72, "URTS1"), + "V20", "mt8135", + MT_FUNCTION(0, "GPIO72"), + MT_FUNCTION(1, "URTS1"), + MT_FUNCTION_IRQ(2, "EINT81", 81), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "CLKM1"), + MT_FUNCTION(6, "UCTS1"), + MT_FUNCTION(7, "TESTB_OUT21") + ), + MT_PIN( + PINCTRL_PIN(73, "PWM1"), + "W17", "mt8135", + MT_FUNCTION(0, "GPIO73"), + MT_FUNCTION(1, "PWM1"), + MT_FUNCTION_IRQ(2, "EINT73", 73), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_DRVVBUS"), + MT_FUNCTION(6, "DISP_PWM"), + MT_FUNCTION(7, "TESTB_OUT8") + ), + MT_PIN( + PINCTRL_PIN(74, "PWM2"), + "Y17", "mt8135", + MT_FUNCTION(0, "GPIO74"), + MT_FUNCTION(1, "PWM2"), + MT_FUNCTION_IRQ(2, "EINT74", 74), + MT_FUNCTION(3, "DPI33_CK"), + MT_FUNCTION(4, "PWM5"), + MT_FUNCTION(5, "URXD2"), + MT_FUNCTION(6, "DISP_PWM"), + MT_FUNCTION(7, "TESTB_OUT9") + ), + MT_PIN( + PINCTRL_PIN(75, "PWM3"), + "Y19", "mt8135", + MT_FUNCTION(0, "GPIO75"), + MT_FUNCTION(1, "PWM3"), + MT_FUNCTION_IRQ(2, "EINT75", 75), + MT_FUNCTION(3, "DPI33_D0"), + MT_FUNCTION(4, "PWM6"), + MT_FUNCTION(5, "UTXD2"), + MT_FUNCTION(6, "DISP_PWM"), + MT_FUNCTION(7, "TESTB_OUT12") + ), + MT_PIN( + PINCTRL_PIN(76, "PWM4"), + "W19", "mt8135", + MT_FUNCTION(0, "GPIO76"), + MT_FUNCTION(1, "PWM4"), + MT_FUNCTION_IRQ(2, "EINT76", 76), + MT_FUNCTION(3, "DPI33_D1"), + MT_FUNCTION(4, "PWM7"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "DISP_PWM"), + MT_FUNCTION(7, "TESTB_OUT13") + ), + MT_PIN( + PINCTRL_PIN(77, "MSDC2_DAT2"), + "W21", "mt8135", + MT_FUNCTION(0, "GPIO77"), + MT_FUNCTION(1, "MSDC2_DAT2"), + MT_FUNCTION_IRQ(2, "EINT63", 63), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "DSP2_IMS"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "DPI33_D6"), + MT_FUNCTION(7, "TESTA_OUT25") + ), + MT_PIN( + PINCTRL_PIN(78, "MSDC2_DAT3"), + "AA23", "mt8135", + MT_FUNCTION(0, "GPIO78"), + MT_FUNCTION(1, "MSDC2_DAT3"), + MT_FUNCTION_IRQ(2, "EINT64", 64), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "DSP2_ID"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "DPI33_D7"), + MT_FUNCTION(7, "TESTA_OUT26") + ), + MT_PIN( + PINCTRL_PIN(79, "MSDC2_CMD"), + "Y22", "mt8135", + MT_FUNCTION(0, "GPIO79"), + MT_FUNCTION(1, "MSDC2_CMD"), + MT_FUNCTION_IRQ(2, "EINT60", 60), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "DSP1_IMS"), + MT_FUNCTION(5, "PCM1_WS"), + MT_FUNCTION(6, "DPI33_D3"), + MT_FUNCTION(7, "TESTA_OUT0") + ), + MT_PIN( + PINCTRL_PIN(80, "MSDC2_CLK"), + "AA22", "mt8135", + MT_FUNCTION(0, "GPIO80"), + MT_FUNCTION(1, "MSDC2_CLK"), + MT_FUNCTION_IRQ(2, "EINT59", 59), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "DSP1_ICK"), + MT_FUNCTION(5, "PCM1_CK"), + MT_FUNCTION(6, "DPI33_D2"), + MT_FUNCTION(7, "TESTA_OUT1") + ), + MT_PIN( + PINCTRL_PIN(81, "MSDC2_DAT1"), + "Y21", "mt8135", + MT_FUNCTION(0, "GPIO81"), + MT_FUNCTION(1, "MSDC2_DAT1"), + MT_FUNCTION_IRQ(2, "EINT62", 62), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "DSP2_ICK"), + MT_FUNCTION(5, "PCM1_DO"), + MT_FUNCTION(6, "DPI33_D5"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(82, "MSDC2_DAT0"), + "AB22", "mt8135", + MT_FUNCTION(0, "GPIO82"), + MT_FUNCTION(1, "MSDC2_DAT0"), + MT_FUNCTION_IRQ(2, "EINT61", 61), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "DSP1_ID"), + MT_FUNCTION(5, "PCM1_DI"), + MT_FUNCTION(6, "DPI33_D4"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(83, "MSDC1_DAT0"), + "AC19", "mt8135", + MT_FUNCTION(0, "GPIO83"), + MT_FUNCTION(1, "MSDC1_DAT0"), + MT_FUNCTION_IRQ(2, "EINT53", 53), + MT_FUNCTION(3, "SCL1"), + MT_FUNCTION(4, "PWM2"), + MT_FUNCTION(5, "CLKM1"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTB_OUT2") + ), + MT_PIN( + PINCTRL_PIN(84, "MSDC1_DAT1"), + "AA19", "mt8135", + MT_FUNCTION(0, "GPIO84"), + MT_FUNCTION(1, "MSDC1_DAT1"), + MT_FUNCTION_IRQ(2, "EINT54", 54), + MT_FUNCTION(3, "SDA1"), + MT_FUNCTION(4, "PWM3"), + MT_FUNCTION(5, "CLKM2"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTB_OUT3") + ), + MT_PIN( + PINCTRL_PIN(85, "MSDC1_CMD"), + "AA20", "mt8135", + MT_FUNCTION(0, "GPIO85"), + MT_FUNCTION(1, "MSDC1_CMD"), + MT_FUNCTION_IRQ(2, "EINT52", 52), + MT_FUNCTION(3, "SDA0"), + MT_FUNCTION(4, "PWM1"), + MT_FUNCTION(5, "CLKM0"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTB_OUT1") + ), + MT_PIN( + PINCTRL_PIN(86, "MSDC1_CLK"), + "AB19", "mt8135", + MT_FUNCTION(0, "GPIO86"), + MT_FUNCTION(1, "MSDC1_CLK"), + MT_FUNCTION_IRQ(2, "EINT51", 51), + MT_FUNCTION(3, "SCL0"), + MT_FUNCTION(4, "DISP_PWM"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTB_OUT0") + ), + MT_PIN( + PINCTRL_PIN(87, "MSDC1_DAT2"), + "AA21", "mt8135", + MT_FUNCTION(0, "GPIO87"), + MT_FUNCTION(1, "MSDC1_DAT2"), + MT_FUNCTION_IRQ(2, "EINT55", 55), + MT_FUNCTION(3, "SCL4"), + MT_FUNCTION(4, "PWM4"), + MT_FUNCTION(5, "CLKM3"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTB_OUT4") + ), + MT_PIN( + PINCTRL_PIN(88, "MSDC1_DAT3"), + "AB20", "mt8135", + MT_FUNCTION(0, "GPIO88"), + MT_FUNCTION(1, "MSDC1_DAT3"), + MT_FUNCTION_IRQ(2, "EINT56", 56), + MT_FUNCTION(3, "SDA4"), + MT_FUNCTION(4, "PWM5"), + MT_FUNCTION(5, "CLKM4"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTB_OUT5") + ), + MT_PIN( + PINCTRL_PIN(89, "MSDC4_DAT0"), + "AB8", "mt8135", + MT_FUNCTION(0, "GPIO89"), + MT_FUNCTION(1, "MSDC4_DAT0"), + MT_FUNCTION_IRQ(2, "EINT133", 133), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "EXT_FRAME_SYNC"), + MT_FUNCTION(5, "USB_DRVVBUS"), + MT_FUNCTION(6, "A_FUNC_DIN[9]"), + MT_FUNCTION(7, "LPTE") + ), + MT_PIN( + PINCTRL_PIN(90, "MSDC4_DAT1"), + "AB7", "mt8135", + MT_FUNCTION(0, "GPIO90"), + MT_FUNCTION(1, "MSDC4_DAT1"), + MT_FUNCTION_IRQ(2, "EINT134", 134), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "A_FUNC_DIN[10]"), + MT_FUNCTION(7, "LRSTB_1X") + ), + MT_PIN( + PINCTRL_PIN(91, "MSDC4_DAT5"), + "AA8", "mt8135", + MT_FUNCTION(0, "GPIO91"), + MT_FUNCTION(1, "MSDC4_DAT5"), + MT_FUNCTION_IRQ(2, "EINT136", 136), + MT_FUNCTION(3, "I2SIN_WS"), + MT_FUNCTION(4, "DAC_WS"), + MT_FUNCTION(5, "PCM1_WS"), + MT_FUNCTION(6, "A_FUNC_DIN[11]"), + MT_FUNCTION(7, "SPI1_CSN") + ), + MT_PIN( + PINCTRL_PIN(92, "MSDC4_DAT6"), + "AC4", "mt8135", + MT_FUNCTION(0, "GPIO92"), + MT_FUNCTION(1, "MSDC4_DAT6"), + MT_FUNCTION_IRQ(2, "EINT137", 137), + MT_FUNCTION(3, "I2SOUT_DAT"), + MT_FUNCTION(4, "DAC_DAT_OUT"), + MT_FUNCTION(5, "PCM1_DO"), + MT_FUNCTION(6, "A_FUNC_DIN[12]"), + MT_FUNCTION(7, "SPI1_MO") + ), + MT_PIN( + PINCTRL_PIN(93, "MSDC4_DAT7"), + "AC6", "mt8135", + MT_FUNCTION(0, "GPIO93"), + MT_FUNCTION(1, "MSDC4_DAT7"), + MT_FUNCTION_IRQ(2, "EINT138", 138), + MT_FUNCTION(3, "I2SIN_DAT"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "PCM1_DI"), + MT_FUNCTION(6, "A_FUNC_DIN[13]"), + MT_FUNCTION(7, "SPI1_MI") + ), + MT_PIN( + PINCTRL_PIN(94, "MSDC4_DAT4"), + "AA7", "mt8135", + MT_FUNCTION(0, "GPIO94"), + MT_FUNCTION(1, "MSDC4_DAT4"), + MT_FUNCTION_IRQ(2, "EINT135", 135), + MT_FUNCTION(3, "I2SIN_CK"), + MT_FUNCTION(4, "DAC_CK"), + MT_FUNCTION(5, "PCM1_CK"), + MT_FUNCTION(6, "A_FUNC_DIN[14]"), + MT_FUNCTION(7, "SPI1_CLK") + ), + MT_PIN( + PINCTRL_PIN(95, "MSDC4_DAT2"), + "AB6", "mt8135", + MT_FUNCTION(0, "GPIO95"), + MT_FUNCTION(1, "MSDC4_DAT2"), + MT_FUNCTION_IRQ(2, "EINT131", 131), + MT_FUNCTION(3, "I2SIN_WS"), + MT_FUNCTION(4, "CM2PDN_2X"), + MT_FUNCTION(5, "DAC_WS"), + MT_FUNCTION(6, "PCM1_WS"), + MT_FUNCTION(7, "LSCE0B_1X") + ), + MT_PIN( + PINCTRL_PIN(96, "MSDC4_CLK"), + "AB5", "mt8135", + MT_FUNCTION(0, "GPIO96"), + MT_FUNCTION(1, "MSDC4_CLK"), + MT_FUNCTION_IRQ(2, "EINT129", 129), + MT_FUNCTION(3, "DPI1_CK_2X"), + MT_FUNCTION(4, "CM2PCLK_2X"), + MT_FUNCTION(5, "PWM4"), + MT_FUNCTION(6, "PCM1_DI"), + MT_FUNCTION(7, "LSCK_1X") + ), + MT_PIN( + PINCTRL_PIN(97, "MSDC4_DAT3"), + "Y8", "mt8135", + MT_FUNCTION(0, "GPIO97"), + MT_FUNCTION(1, "MSDC4_DAT3"), + MT_FUNCTION_IRQ(2, "EINT132", 132), + MT_FUNCTION(3, "I2SOUT_DAT"), + MT_FUNCTION(4, "CM2RST_2X"), + MT_FUNCTION(5, "DAC_DAT_OUT"), + MT_FUNCTION(6, "PCM1_DO"), + MT_FUNCTION(7, "LSCE1B_1X") + ), + MT_PIN( + PINCTRL_PIN(98, "MSDC4_CMD"), + "AC3", "mt8135", + MT_FUNCTION(0, "GPIO98"), + MT_FUNCTION(1, "MSDC4_CMD"), + MT_FUNCTION_IRQ(2, "EINT128", 128), + MT_FUNCTION(3, "DPI1_DE_2X"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "PWM3"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "LSDA_1X") + ), + MT_PIN( + PINCTRL_PIN(99, "MSDC4_RSTB"), + "AB4", "mt8135", + MT_FUNCTION(0, "GPIO99"), + MT_FUNCTION(1, "MSDC4_RSTB"), + MT_FUNCTION_IRQ(2, "EINT130", 130), + MT_FUNCTION(3, "I2SIN_CK"), + MT_FUNCTION(4, "CM2MCLK_2X"), + MT_FUNCTION(5, "DAC_CK"), + MT_FUNCTION(6, "PCM1_CK"), + MT_FUNCTION(7, "LSA0_1X") + ), + MT_PIN( + PINCTRL_PIN(100, "SDA0"), + "W9", "mt8135", + MT_FUNCTION(0, "GPIO100"), + MT_FUNCTION(1, "SDA0"), + MT_FUNCTION_IRQ(2, "EINT91", 91), + MT_FUNCTION(3, "CLKM1"), + MT_FUNCTION(4, "PWM1"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "A_FUNC_DIN[15]") + ), + MT_PIN( + PINCTRL_PIN(101, "SCL0"), + "W11", "mt8135", + MT_FUNCTION(0, "GPIO101"), + MT_FUNCTION(1, "SCL0"), + MT_FUNCTION_IRQ(2, "EINT90", 90), + MT_FUNCTION(3, "CLKM0"), + MT_FUNCTION(4, "DISP_PWM"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "A_FUNC_DIN[16]") + ), + MT_PIN( + PINCTRL_PIN(102, "EINT10_AUXIN2"), + "AA3", "mt8135", + MT_FUNCTION(0, "GPIO102"), + MT_FUNCTION_IRQ(1, "EINT10", 10), + MT_FUNCTION(2, NULL), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[16]"), + MT_FUNCTION(6, "TESTB_OUT16"), + MT_FUNCTION(7, "A_FUNC_DIN[17]") + ), + MT_PIN( + PINCTRL_PIN(103, "EINT11_AUXIN3"), + "AB2", "mt8135", + MT_FUNCTION(0, "GPIO103"), + MT_FUNCTION_IRQ(1, "EINT11", 11), + MT_FUNCTION(2, NULL), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[17]"), + MT_FUNCTION(6, "TESTB_OUT17"), + MT_FUNCTION(7, "A_FUNC_DIN[18]") + ), + MT_PIN( + PINCTRL_PIN(104, "EINT16_AUXIN4"), + "AB3", "mt8135", + MT_FUNCTION(0, "GPIO104"), + MT_FUNCTION_IRQ(1, "EINT16", 16), + MT_FUNCTION(2, NULL), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[18]"), + MT_FUNCTION(6, "TESTB_OUT18"), + MT_FUNCTION(7, "A_FUNC_DIN[19]") + ), + MT_PIN( + PINCTRL_PIN(105, "I2S_CLK"), + "W6", "mt8135", + MT_FUNCTION(0, "GPIO105"), + MT_FUNCTION(1, "I2SIN_CK"), + MT_FUNCTION_IRQ(2, "EINT10", 10), + MT_FUNCTION(3, "DAC_CK"), + MT_FUNCTION(4, "PCM1_CK"), + MT_FUNCTION(5, "USB_TEST_IO[19]"), + MT_FUNCTION(6, "TESTB_OUT19"), + MT_FUNCTION(7, "A_FUNC_DIN[20]") + ), + MT_PIN( + PINCTRL_PIN(106, "I2S_WS"), + "AA6", "mt8135", + MT_FUNCTION(0, "GPIO106"), + MT_FUNCTION(1, "I2SIN_WS"), + MT_FUNCTION_IRQ(2, "EINT13", 13), + MT_FUNCTION(3, "DAC_WS"), + MT_FUNCTION(4, "PCM1_WS"), + MT_FUNCTION(5, "USB_TEST_IO[20]"), + MT_FUNCTION(6, "TESTB_OUT20"), + MT_FUNCTION(7, "A_FUNC_DIN[21]") + ), + MT_PIN( + PINCTRL_PIN(107, "I2S_DATA_IN"), + "AA5", "mt8135", + MT_FUNCTION(0, "GPIO107"), + MT_FUNCTION(1, "I2SIN_DAT"), + MT_FUNCTION_IRQ(2, "EINT11", 11), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "PCM1_DI"), + MT_FUNCTION(5, "USB_TEST_IO[21]"), + MT_FUNCTION(6, "TESTB_OUT22"), + MT_FUNCTION(7, "A_FUNC_DIN[22]") + ), + MT_PIN( + PINCTRL_PIN(108, "I2S_DATA_OUT"), + "AA4", "mt8135", + MT_FUNCTION(0, "GPIO108"), + MT_FUNCTION(1, "I2SOUT_DAT"), + MT_FUNCTION_IRQ(2, "EINT12", 12), + MT_FUNCTION(3, "DAC_DAT_OUT"), + MT_FUNCTION(4, "PCM1_DO"), + MT_FUNCTION(5, "USB_TEST_IO[22]"), + MT_FUNCTION(6, "TESTB_OUT23"), + MT_FUNCTION(7, "A_FUNC_DIN[23]") + ), + MT_PIN( + PINCTRL_PIN(109, "EINT5"), + "W5", "mt8135", + MT_FUNCTION(0, "GPIO109"), + MT_FUNCTION_IRQ(1, "EINT5", 5), + MT_FUNCTION(2, "PWM5"), + MT_FUNCTION(3, "CLKM3"), + MT_FUNCTION(4, "GPU_JTRSTB"), + MT_FUNCTION(5, "USB_TEST_IO[23]"), + MT_FUNCTION(6, "TESTB_OUT26"), + MT_FUNCTION(7, "A_FUNC_DIN[24]") + ), + MT_PIN( + PINCTRL_PIN(110, "EINT6"), + "V5", "mt8135", + MT_FUNCTION(0, "GPIO110"), + MT_FUNCTION_IRQ(1, "EINT6", 6), + MT_FUNCTION(2, "PWM6"), + MT_FUNCTION(3, "CLKM4"), + MT_FUNCTION(4, "GPU_JTMS"), + MT_FUNCTION(5, "USB_TEST_IO[24]"), + MT_FUNCTION(6, "TESTB_OUT27"), + MT_FUNCTION(7, "A_FUNC_DIN[25]") + ), + MT_PIN( + PINCTRL_PIN(111, "EINT7"), + "W3", "mt8135", + MT_FUNCTION(0, "GPIO111"), + MT_FUNCTION_IRQ(1, "EINT7", 7), + MT_FUNCTION(2, "PWM7"), + MT_FUNCTION(3, "CLKM5"), + MT_FUNCTION(4, "GPU_JTDO"), + MT_FUNCTION(5, "USB_TEST_IO[25]"), + MT_FUNCTION(6, "TESTB_OUT28"), + MT_FUNCTION(7, "A_FUNC_DIN[26]") + ), + MT_PIN( + PINCTRL_PIN(112, "EINT8"), + "V6", "mt8135", + MT_FUNCTION(0, "GPIO112"), + MT_FUNCTION_IRQ(1, "EINT8", 8), + MT_FUNCTION(2, "DISP_PWM"), + MT_FUNCTION(3, "CLKM6"), + MT_FUNCTION(4, "GPU_JTDI"), + MT_FUNCTION(5, "USB_TEST_IO[26]"), + MT_FUNCTION(6, "TESTB_OUT29"), + MT_FUNCTION(7, "EXT_FRAME_SYNC") + ), + MT_PIN( + PINCTRL_PIN(113, "EINT9"), + "W8", "mt8135", + MT_FUNCTION(0, "GPIO113"), + MT_FUNCTION_IRQ(1, "EINT9", 9), + MT_FUNCTION(2, NULL), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "GPU_JTCK"), + MT_FUNCTION(5, "USB_DRVVBUS"), + MT_FUNCTION(6, "TESTB_OUT30"), + MT_FUNCTION(7, "A_FUNC_DIN[27]") + ), + MT_PIN( + PINCTRL_PIN(114, "LPCE1B"), + "W4", "mt8135", + MT_FUNCTION(0, "GPIO114"), + MT_FUNCTION(1, "LPCE1B"), + MT_FUNCTION_IRQ(2, "EINT127", 127), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "PWM2"), + MT_FUNCTION(6, "TESTB_OUT14"), + MT_FUNCTION(7, "A_FUNC_DIN[28]") + ), + MT_PIN( + PINCTRL_PIN(115, "LPCE0B"), + "T5", "mt8135", + MT_FUNCTION(0, "GPIO115"), + MT_FUNCTION(1, "LPCE0B"), + MT_FUNCTION_IRQ(2, "EINT126", 126), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "PWM1"), + MT_FUNCTION(6, "TESTB_OUT15"), + MT_FUNCTION(7, "A_FUNC_DIN[29]") + ), + MT_PIN( + PINCTRL_PIN(116, "DISP_PWM"), + "V4", "mt8135", + MT_FUNCTION(0, "GPIO116"), + MT_FUNCTION(1, "DISP_PWM"), + MT_FUNCTION_IRQ(2, "EINT77", 77), + MT_FUNCTION(3, "LSDI"), + MT_FUNCTION(4, "PWM1"), + MT_FUNCTION(5, "PWM2"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "PWM3") + ), + MT_PIN( + PINCTRL_PIN(117, "EINT1"), + "T6", "mt8135", + MT_FUNCTION(0, "GPIO117"), + MT_FUNCTION_IRQ(1, "EINT1", 1), + MT_FUNCTION(2, "PWM2"), + MT_FUNCTION(3, "CLKM1"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[13]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "USB_SDA") + ), + MT_PIN( + PINCTRL_PIN(118, "EINT2"), + "T4", "mt8135", + MT_FUNCTION(0, "GPIO118"), + MT_FUNCTION_IRQ(1, "EINT2", 2), + MT_FUNCTION(2, "PWM3"), + MT_FUNCTION(3, "CLKM2"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[14]"), + MT_FUNCTION(6, "SRCLKENAI2"), + MT_FUNCTION(7, "A_FUNC_DIN[30]") + ), + MT_PIN( + PINCTRL_PIN(119, "EINT3"), + "R4", "mt8135", + MT_FUNCTION(0, "GPIO119"), + MT_FUNCTION_IRQ(1, "EINT3", 3), + MT_FUNCTION(2, NULL), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_TEST_IO[15]"), + MT_FUNCTION(6, "SRCLKENAI1"), + MT_FUNCTION(7, "EXT_26M_CK") + ), + MT_PIN( + PINCTRL_PIN(120, "EINT4"), + "R5", "mt8135", + MT_FUNCTION(0, "GPIO120"), + MT_FUNCTION_IRQ(1, "EINT4", 4), + MT_FUNCTION(2, "PWM4"), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "USB_DRVVBUS"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "A_FUNC_DIN[31]") + ), + MT_PIN( + PINCTRL_PIN(121, "DPIDE"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO121"), + MT_FUNCTION(1, "DPI0_DE"), + MT_FUNCTION_IRQ(2, "EINT100", 100), + MT_FUNCTION(3, "I2SOUT_DAT"), + MT_FUNCTION(4, "DAC_DAT_OUT"), + MT_FUNCTION(5, "PCM1_DO"), + MT_FUNCTION(6, "IRDA_TXD"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(122, "DPICK"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO122"), + MT_FUNCTION(1, "DPI0_CK"), + MT_FUNCTION_IRQ(2, "EINT101", 101), + MT_FUNCTION(3, "I2SIN_DAT"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "PCM1_DI"), + MT_FUNCTION(6, "IRDA_PDN"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(123, "DPIG4"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO123"), + MT_FUNCTION(1, "DPI0_G4"), + MT_FUNCTION_IRQ(2, "EINT114", 114), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2DAT_2X[0]"), + MT_FUNCTION(5, "DSP2_ID"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(124, "DPIG5"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO124"), + MT_FUNCTION(1, "DPI0_G5"), + MT_FUNCTION_IRQ(2, "EINT115", 115), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2DAT_2X[1]"), + MT_FUNCTION(5, "DSP2_ICK"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(125, "DPIR3"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO125"), + MT_FUNCTION(1, "DPI0_R3"), + MT_FUNCTION_IRQ(2, "EINT121", 121), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2DAT_2X[7]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(126, "DPIG1"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO126"), + MT_FUNCTION(1, "DPI0_G1"), + MT_FUNCTION_IRQ(2, "EINT111", 111), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "DSP1_ICK"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(127, "DPIVSYNC"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO127"), + MT_FUNCTION(1, "DPI0_VSYNC"), + MT_FUNCTION_IRQ(2, "EINT98", 98), + MT_FUNCTION(3, "I2SIN_CK"), + MT_FUNCTION(4, "DAC_CK"), + MT_FUNCTION(5, "PCM1_CK"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(128, "DPIHSYNC"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO128"), + MT_FUNCTION(1, "DPI0_HSYNC"), + MT_FUNCTION_IRQ(2, "EINT99", 99), + MT_FUNCTION(3, "I2SIN_WS"), + MT_FUNCTION(4, "DAC_WS"), + MT_FUNCTION(5, "PCM1_WS"), + MT_FUNCTION(6, "IRDA_RXD"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(129, "DPIB0"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO129"), + MT_FUNCTION(1, "DPI0_B0"), + MT_FUNCTION_IRQ(2, "EINT102", 102), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "SCL0"), + MT_FUNCTION(5, "DISP_PWM"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(130, "DPIB1"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO130"), + MT_FUNCTION(1, "DPI0_B1"), + MT_FUNCTION_IRQ(2, "EINT103", 103), + MT_FUNCTION(3, "CLKM0"), + MT_FUNCTION(4, "SDA0"), + MT_FUNCTION(5, "PWM1"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(131, "DPIB2"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO131"), + MT_FUNCTION(1, "DPI0_B2"), + MT_FUNCTION_IRQ(2, "EINT104", 104), + MT_FUNCTION(3, "CLKM1"), + MT_FUNCTION(4, "SCL1"), + MT_FUNCTION(5, "PWM2"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(132, "DPIB3"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO132"), + MT_FUNCTION(1, "DPI0_B3"), + MT_FUNCTION_IRQ(2, "EINT105", 105), + MT_FUNCTION(3, "CLKM2"), + MT_FUNCTION(4, "SDA1"), + MT_FUNCTION(5, "PWM3"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(133, "DPIB4"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO133"), + MT_FUNCTION(1, "DPI0_B4"), + MT_FUNCTION_IRQ(2, "EINT106", 106), + MT_FUNCTION(3, "CLKM3"), + MT_FUNCTION(4, "SCL2"), + MT_FUNCTION(5, "PWM4"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(134, "DPIB5"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO134"), + MT_FUNCTION(1, "DPI0_B5"), + MT_FUNCTION_IRQ(2, "EINT107", 107), + MT_FUNCTION(3, "CLKM4"), + MT_FUNCTION(4, "SDA2"), + MT_FUNCTION(5, "PWM5"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(135, "DPIB6"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO135"), + MT_FUNCTION(1, "DPI0_B6"), + MT_FUNCTION_IRQ(2, "EINT108", 108), + MT_FUNCTION(3, "CLKM5"), + MT_FUNCTION(4, "SCL3"), + MT_FUNCTION(5, "PWM6"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(136, "DPIB7"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO136"), + MT_FUNCTION(1, "DPI0_B7"), + MT_FUNCTION_IRQ(2, "EINT109", 109), + MT_FUNCTION(3, "CLKM6"), + MT_FUNCTION(4, "SDA3"), + MT_FUNCTION(5, "PWM7"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(137, "DPIG0"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO137"), + MT_FUNCTION(1, "DPI0_G0"), + MT_FUNCTION_IRQ(2, "EINT110", 110), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "DSP1_ID"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(138, "DPIG2"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO138"), + MT_FUNCTION(1, "DPI0_G2"), + MT_FUNCTION_IRQ(2, "EINT112", 112), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "DSP1_IMS"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(139, "DPIG3"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO139"), + MT_FUNCTION(1, "DPI0_G3"), + MT_FUNCTION_IRQ(2, "EINT113", 113), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "DSP2_IMS"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(140, "DPIG6"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO140"), + MT_FUNCTION(1, "DPI0_G6"), + MT_FUNCTION_IRQ(2, "EINT116", 116), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2DAT_2X[2]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(141, "DPIG7"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO141"), + MT_FUNCTION(1, "DPI0_G7"), + MT_FUNCTION_IRQ(2, "EINT117", 117), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2DAT_2X[3]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(142, "DPIR0"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO142"), + MT_FUNCTION(1, "DPI0_R0"), + MT_FUNCTION_IRQ(2, "EINT118", 118), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2DAT_2X[4]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(143, "DPIR1"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO143"), + MT_FUNCTION(1, "DPI0_R1"), + MT_FUNCTION_IRQ(2, "EINT119", 119), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2DAT_2X[5]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(144, "DPIR2"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO144"), + MT_FUNCTION(1, "DPI0_R2"), + MT_FUNCTION_IRQ(2, "EINT120", 120), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2DAT_2X[6]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(145, "DPIR4"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO145"), + MT_FUNCTION(1, "DPI0_R4"), + MT_FUNCTION_IRQ(2, "EINT122", 122), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2DAT_2X[8]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(146, "DPIR5"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO146"), + MT_FUNCTION(1, "DPI0_R5"), + MT_FUNCTION_IRQ(2, "EINT123", 123), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2DAT_2X[9]"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(147, "DPIR6"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO147"), + MT_FUNCTION(1, "DPI0_R6"), + MT_FUNCTION_IRQ(2, "EINT124", 124), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2VSYNC_2X"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(148, "DPIR7"), + NULL, "mt8135", + MT_FUNCTION(0, "GPIO148"), + MT_FUNCTION(1, "DPI0_R7"), + MT_FUNCTION_IRQ(2, "EINT125", 125), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, "CM2HSYNC_2X"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(149, "TDN3/LVDS(TDN3)"), + "AA2", "mt8135", + MT_FUNCTION(0, "GPIO149"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT36", 36), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(150, "TDP3/LVDS(TDP3)"), + "AA1", "mt8135", + MT_FUNCTION(0, "GPIO150"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT35", 35), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(151, "TDN2/LVDS(TCN)"), + "Y2", "mt8135", + MT_FUNCTION(0, "GPIO151"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT169", 169), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(152, "TDP2/LVDS(TCP)"), + "Y1", "mt8135", + MT_FUNCTION(0, "GPIO152"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT168", 168), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(153, "TCN/LVDS(TDN2)"), + "W2", "mt8135", + MT_FUNCTION(0, "GPIO153"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT163", 163), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(154, "TCP/LVDS(TDP2)"), + "W1", "mt8135", + MT_FUNCTION(0, "GPIO154"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT162", 162), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(155, "TDN1/LVDS(TDN1)"), + "V3", "mt8135", + MT_FUNCTION(0, "GPIO155"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT167", 167), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(156, "TDP1/LVDS(TDP1)"), + "V2", "mt8135", + MT_FUNCTION(0, "GPIO156"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT166", 166), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(157, "TDN0/LVDS(TDN0)"), + "U3", "mt8135", + MT_FUNCTION(0, "GPIO157"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT165", 165), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(158, "TDP0/LVDS(TDP0)"), + "U2", "mt8135", + MT_FUNCTION(0, "GPIO158"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT164", 164), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(159, "RDN3"), + "N5", "mt8135", + MT_FUNCTION(0, "GPIO159"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT18", 18), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(160, "RDP3"), + "N4", "mt8135", + MT_FUNCTION(0, "GPIO160"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT30", 30), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(161, "RDN2"), + "T2", "mt8135", + MT_FUNCTION(0, "GPIO161"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT31", 31), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(162, "RDP2"), + "T3", "mt8135", + MT_FUNCTION(0, "GPIO162"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT32", 32), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(163, "RCN"), + "P2", "mt8135", + MT_FUNCTION(0, "GPIO163"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT33", 33), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(164, "RCP"), + "P3", "mt8135", + MT_FUNCTION(0, "GPIO164"), + MT_FUNCTION(1, NULL), + MT_FUNCTION_IRQ(2, "EINT39", 39), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(165, "RDN1"), + "R3", "mt8135", + MT_FUNCTION(0, "GPIO165"), + MT_FUNCTION(1, NULL), + MT_FUNCTION(2, NULL), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(166, "RDP1"), + "R2", "mt8135", + MT_FUNCTION(0, "GPIO166"), + MT_FUNCTION(1, NULL), + MT_FUNCTION(2, NULL), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(167, "RDN0"), + "N3", "mt8135", + MT_FUNCTION(0, "GPIO167"), + MT_FUNCTION(1, NULL), + MT_FUNCTION(2, NULL), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(168, "RDP0"), + "N2", "mt8135", + MT_FUNCTION(0, "GPIO168"), + MT_FUNCTION(1, NULL), + MT_FUNCTION(2, NULL), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(169, "RDN1_A"), + "M4", "mt8135", + MT_FUNCTION(0, "GPIO169"), + MT_FUNCTION(1, "CMDAT6"), + MT_FUNCTION_IRQ(2, "EINT175", 175), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(170, "RDP1_A"), + "M3", "mt8135", + MT_FUNCTION(0, "GPIO170"), + MT_FUNCTION(1, "CMDAT7"), + MT_FUNCTION_IRQ(2, "EINT174", 174), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(171, "RCN_A"), + "L3", "mt8135", + MT_FUNCTION(0, "GPIO171"), + MT_FUNCTION(1, "CMDAT8"), + MT_FUNCTION_IRQ(2, "EINT171", 171), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(172, "RCP_A"), + "L2", "mt8135", + MT_FUNCTION(0, "GPIO172"), + MT_FUNCTION(1, "CMDAT9"), + MT_FUNCTION_IRQ(2, "EINT170", 170), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(173, "RDN0_A"), + "M2", "mt8135", + MT_FUNCTION(0, "GPIO173"), + MT_FUNCTION(1, "CMHSYNC"), + MT_FUNCTION_IRQ(2, "EINT173", 173), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(174, "RDP0_A"), + "M1", "mt8135", + MT_FUNCTION(0, "GPIO174"), + MT_FUNCTION(1, "CMVSYNC"), + MT_FUNCTION_IRQ(2, "EINT172", 172), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(175, "RDN1_B"), + "H2", "mt8135", + MT_FUNCTION(0, "GPIO175"), + MT_FUNCTION(1, "CMDAT2"), + MT_FUNCTION_IRQ(2, "EINT181", 181), + MT_FUNCTION(3, "CMCSD2"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(176, "RDP1_B"), + "H1", "mt8135", + MT_FUNCTION(0, "GPIO176"), + MT_FUNCTION(1, "CMDAT3"), + MT_FUNCTION_IRQ(2, "EINT180", 180), + MT_FUNCTION(3, "CMCSD3"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(177, "RCN_B"), + "K3", "mt8135", + MT_FUNCTION(0, "GPIO177"), + MT_FUNCTION(1, "CMDAT4"), + MT_FUNCTION_IRQ(2, "EINT177", 177), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(178, "RCP_B"), + "K2", "mt8135", + MT_FUNCTION(0, "GPIO178"), + MT_FUNCTION(1, "CMDAT5"), + MT_FUNCTION_IRQ(2, "EINT176", 176), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(179, "RDN0_B"), + "J3", "mt8135", + MT_FUNCTION(0, "GPIO179"), + MT_FUNCTION(1, "CMDAT0"), + MT_FUNCTION_IRQ(2, "EINT179", 179), + MT_FUNCTION(3, "CMCSD0"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(180, "RDP0_B"), + "J2", "mt8135", + MT_FUNCTION(0, "GPIO180"), + MT_FUNCTION(1, "CMDAT1"), + MT_FUNCTION_IRQ(2, "EINT178", 178), + MT_FUNCTION(3, "CMCSD1"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(181, "CMPCLK"), + "K4", "mt8135", + MT_FUNCTION(0, "GPIO181"), + MT_FUNCTION(1, "CMPCLK"), + MT_FUNCTION_IRQ(2, "EINT182", 182), + MT_FUNCTION(3, "CMCSK"), + MT_FUNCTION(4, "CM2MCLK_4X"), + MT_FUNCTION(5, "TS_AUXADC_SEL[3]"), + MT_FUNCTION(6, "VENC_TEST_CK"), + MT_FUNCTION(7, "TESTA_OUT27") + ), + MT_PIN( + PINCTRL_PIN(182, "CMMCLK"), + "J5", "mt8135", + MT_FUNCTION(0, "GPIO182"), + MT_FUNCTION(1, "CMMCLK"), + MT_FUNCTION_IRQ(2, "EINT183", 183), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "TS_AUXADC_SEL[2]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT28") + ), + MT_PIN( + PINCTRL_PIN(183, "CMRST"), + "J6", "mt8135", + MT_FUNCTION(0, "GPIO183"), + MT_FUNCTION(1, "CMRST"), + MT_FUNCTION_IRQ(2, "EINT185", 185), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "TS_AUXADC_SEL[1]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT30") + ), + MT_PIN( + PINCTRL_PIN(184, "CMPDN"), + "J4", "mt8135", + MT_FUNCTION(0, "GPIO184"), + MT_FUNCTION(1, "CMPDN"), + MT_FUNCTION_IRQ(2, "EINT184", 184), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "TS_AUXADC_SEL[0]"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, "TESTA_OUT29") + ), + MT_PIN( + PINCTRL_PIN(185, "CMFLASH"), + "G4", "mt8135", + MT_FUNCTION(0, "GPIO185"), + MT_FUNCTION(1, "CMFLASH"), + MT_FUNCTION_IRQ(2, "EINT186", 186), + MT_FUNCTION(3, "CM2MCLK_3X"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "MFG_TEST_CK_1"), + MT_FUNCTION(7, "TESTA_OUT31") + ), + MT_PIN( + PINCTRL_PIN(186, "MRG_I2S_PCM_CLK"), + "F5", "mt8135", + MT_FUNCTION(0, "GPIO186"), + MT_FUNCTION(1, "MRG_I2S_PCM_CLK"), + MT_FUNCTION_IRQ(2, "EINT14", 14), + MT_FUNCTION(3, "I2SIN_CK"), + MT_FUNCTION(4, "PCM0_CK"), + MT_FUNCTION(5, "DSP2_ICK"), + MT_FUNCTION(6, "IMG_TEST_CK"), + MT_FUNCTION(7, "USB_SCL") + ), + MT_PIN( + PINCTRL_PIN(187, "MRG_I2S_PCM_SYNC"), + "G6", "mt8135", + MT_FUNCTION(0, "GPIO187"), + MT_FUNCTION(1, "MRG_I2S_PCM_SYNC"), + MT_FUNCTION_IRQ(2, "EINT16", 16), + MT_FUNCTION(3, "I2SIN_WS"), + MT_FUNCTION(4, "PCM0_WS"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "DISP_TEST_CK"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(188, "MRG_I2S_PCM_RX"), + "G3", "mt8135", + MT_FUNCTION(0, "GPIO188"), + MT_FUNCTION(1, "MRG_I2S_PCM_RX"), + MT_FUNCTION_IRQ(2, "EINT15", 15), + MT_FUNCTION(3, "I2SIN_DAT"), + MT_FUNCTION(4, "PCM0_DI"), + MT_FUNCTION(5, "DSP2_ID"), + MT_FUNCTION(6, "MFG_TEST_CK"), + MT_FUNCTION(7, "USB_SDA") + ), + MT_PIN( + PINCTRL_PIN(189, "MRG_I2S_PCM_TX"), + "G5", "mt8135", + MT_FUNCTION(0, "GPIO189"), + MT_FUNCTION(1, "MRG_I2S_PCM_TX"), + MT_FUNCTION_IRQ(2, "EINT17", 17), + MT_FUNCTION(3, "I2SOUT_DAT"), + MT_FUNCTION(4, "PCM0_DO"), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, "VDEC_TEST_CK"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(190, "SRCLKENAI"), + "K5", "mt8135", + MT_FUNCTION(0, "GPIO190"), + MT_FUNCTION(1, "SRCLKENAI"), + MT_FUNCTION(2, NULL), + MT_FUNCTION(3, NULL), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, NULL), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(191, "URXD3"), + "C3", "mt8135", + MT_FUNCTION(0, "GPIO191"), + MT_FUNCTION(1, "URXD3"), + MT_FUNCTION_IRQ(2, "EINT87", 87), + MT_FUNCTION(3, "UTXD3"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "TS_AUX_ST"), + MT_FUNCTION(6, "PWM4"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(192, "UTXD3"), + "B2", "mt8135", + MT_FUNCTION(0, "GPIO192"), + MT_FUNCTION(1, "UTXD3"), + MT_FUNCTION_IRQ(2, "EINT86", 86), + MT_FUNCTION(3, "URXD3"), + MT_FUNCTION(4, NULL), + MT_FUNCTION(5, "TS_AUX_CS_B"), + MT_FUNCTION(6, "PWM3"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(193, "SDA2"), + "G2", "mt8135", + MT_FUNCTION(0, "GPIO193"), + MT_FUNCTION(1, "SDA2"), + MT_FUNCTION_IRQ(2, "EINT95", 95), + MT_FUNCTION(3, "CLKM5"), + MT_FUNCTION(4, "PWM5"), + MT_FUNCTION(5, "TS_AUX_PWDB"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(194, "SCL2"), + "F4", "mt8135", + MT_FUNCTION(0, "GPIO194"), + MT_FUNCTION(1, "SCL2"), + MT_FUNCTION_IRQ(2, "EINT94", 94), + MT_FUNCTION(3, "CLKM4"), + MT_FUNCTION(4, "PWM4"), + MT_FUNCTION(5, "TS_AUXADC_TEST_CK"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(195, "SDA1"), + "F2", "mt8135", + MT_FUNCTION(0, "GPIO195"), + MT_FUNCTION(1, "SDA1"), + MT_FUNCTION_IRQ(2, "EINT93", 93), + MT_FUNCTION(3, "CLKM3"), + MT_FUNCTION(4, "PWM3"), + MT_FUNCTION(5, "TS_AUX_SCLK_PWDB"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(196, "SCL1"), + "F3", "mt8135", + MT_FUNCTION(0, "GPIO196"), + MT_FUNCTION(1, "SCL1"), + MT_FUNCTION_IRQ(2, "EINT92", 92), + MT_FUNCTION(3, "CLKM2"), + MT_FUNCTION(4, "PWM2"), + MT_FUNCTION(5, "TS_AUX_DIN"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(197, "MSDC3_DAT2"), + "E1", "mt8135", + MT_FUNCTION(0, "GPIO197"), + MT_FUNCTION(1, "MSDC3_DAT2"), + MT_FUNCTION_IRQ(2, "EINT71", 71), + MT_FUNCTION(3, "SCL6"), + MT_FUNCTION(4, "PWM5"), + MT_FUNCTION(5, "CLKM4"), + MT_FUNCTION(6, "MFG_TEST_CK_2"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(198, "MSDC3_DAT3"), + "C2", "mt8135", + MT_FUNCTION(0, "GPIO198"), + MT_FUNCTION(1, "MSDC3_DAT3"), + MT_FUNCTION_IRQ(2, "EINT72", 72), + MT_FUNCTION(3, "SDA6"), + MT_FUNCTION(4, "PWM6"), + MT_FUNCTION(5, "CLKM5"), + MT_FUNCTION(6, "MFG_TEST_CK_3"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(199, "MSDC3_CMD"), + "D2", "mt8135", + MT_FUNCTION(0, "GPIO199"), + MT_FUNCTION(1, "MSDC3_CMD"), + MT_FUNCTION_IRQ(2, "EINT68", 68), + MT_FUNCTION(3, "SDA2"), + MT_FUNCTION(4, "PWM2"), + MT_FUNCTION(5, "CLKM1"), + MT_FUNCTION(6, "MFG_TEST_CK_4"), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(200, "MSDC3_CLK"), + "E2", "mt8135", + MT_FUNCTION(0, "GPIO200"), + MT_FUNCTION(1, "MSDC3_CLK"), + MT_FUNCTION_IRQ(2, "EINT67", 67), + MT_FUNCTION(3, "SCL2"), + MT_FUNCTION(4, "PWM1"), + MT_FUNCTION(5, "CLKM0"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(201, "MSDC3_DAT1"), + "D3", "mt8135", + MT_FUNCTION(0, "GPIO201"), + MT_FUNCTION(1, "MSDC3_DAT1"), + MT_FUNCTION_IRQ(2, "EINT70", 70), + MT_FUNCTION(3, "SDA3"), + MT_FUNCTION(4, "PWM4"), + MT_FUNCTION(5, "CLKM3"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), + MT_PIN( + PINCTRL_PIN(202, "MSDC3_DAT0"), + "E3", "mt8135", + MT_FUNCTION(0, "GPIO202"), + MT_FUNCTION(1, "MSDC3_DAT0"), + MT_FUNCTION_IRQ(2, "EINT69", 69), + MT_FUNCTION(3, "SCL3"), + MT_FUNCTION(4, "PWM3"), + MT_FUNCTION(5, "CLKM2"), + MT_FUNCTION(6, NULL), + MT_FUNCTION(7, NULL) + ), +}; + +#endif /*__PINCTRL_MTK_MT8135_H*/ diff --git a/include/dt-bindings/pinctrl/mt65xx.h b/include/dt-bindings/pinctrl/mt65xx.h new file mode 100644 index 0000000..4c2faff --- /dev/null +++ b/include/dt-bindings/pinctrl/mt65xx.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_MT65XX_H +#define _DT_BINDINGS_PINCTRL_MT65XX_H + +#define MT_PIN_NO(x) ((x) << 8) +#define MT_GET_PIN_NO(x) ((x) >> 8) +#define MT_GET_PIN_FUNC(x) ((x) & 0xf) + + +#endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */ -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v2 2/4] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135. 2014-09-23 3:39 ` [PATCH v2 2/4] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135 Hongzhou.Yang @ 2014-10-02 13:38 ` Linus Walleij 2014-10-06 10:35 ` Joe.C 0 siblings, 1 reply; 27+ messages in thread From: Linus Walleij @ 2014-10-02 13:38 UTC (permalink / raw) To: Hongzhou.Yang Cc: Rob Herring, Matthias Brugger, srv_heupstream, Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely, Hongzhou Yang, Joe.C, Catalin Marinas, Vladimir Murzin, Ashwin Chaugule, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dandan.he On Tue, Sep 23, 2014 at 5:39 AM, Hongzhou.Yang <srv_hongzhou.yang@mediatek.com> wrote: > From: Hongzhou Yang <hongzhou.yang@mediatek.com> > > The mediatek SoCs have GPIO controller that handle both the muxing > and GPIOs. > > The GPIO controller have pinmux, pull enable, pull select, direction > and output high/low control. > > This driver include common and mt8135 part. It implements the pinctrl > part and gpio part. > > Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> (...) > diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig > new file mode 100644 > index 0000000..bae4be6 > --- /dev/null > +++ b/drivers/pinctrl/mediatek/Kconfig > @@ -0,0 +1,12 @@ > +if ARCH_MEDIATEK > + > +config PINCTRL_MTK_COMMON > + bool > + select PINMUX > + select GENERIC_PINCONF This should most certainly select GPIOLIB_IRQCHIP, I'm pretty sure you can use the common chained irqchip handling. > +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c (...) > +postcore_initcall(mtk_pinctrl_init); Why? We prefer to use module_init() these days, and employ deferred probe to order module probe order. Is there some problem with this? > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c (...) > +#include <linux/io.h> > +#include <linux/gpio.h> > +#include <linux/irqdomain.h> > +#include <linux/irqchip/chained_irq.h> These two includes go away with GPIOLIB_IRQCHIP > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_device.h> > +#include <linux/of_irq.h> > +#include <linux/pinctrl/consumer.h> > +#include <linux/pinctrl/machine.h> > +#include <linux/pinctrl/pinctrl.h> > +#include <linux/pinctrl/pinconf.h> > +#include <linux/pinctrl/pinconf-generic.h> > +#include <linux/pinctrl/pinmux.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <dt-bindings/pinctrl/mt65xx.h> > + > +#include "../pinconf.h" > +#include "pinctrl-mtk-common.h" > + > +#define PINMUX_MAX_VAL 8 > +#define MAX_GPIO_MODE_PER_REG 5 > +#define GPIO_MODE_BITS 3 > + > +static const char * const mt_gpio_functions[] = { > + "func0", "func1", "func2", "func3", > + "func4", "func5", "func6", "func7", > +}; > + > +static void __iomem *mt_get_base_addr(struct mt_pinctrl *pctl, > + unsigned long pin) > +{ > + if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) > + return pctl->membase2; > + return pctl->membase1; > +} > + > +static void mt_pctrl_write_reg(struct mt_pinctrl *pctl, > + unsigned long pin, > + u32 reg, u32 d) > +{ > + writel(d, mt_get_base_addr(pctl, pin) + reg); > +} 1) Don't you want to use writel_relaxed() and 2) What does this helper really buy you? I would prefer to inline this everywhere it's used. At the least tag this function as inline. > +static unsigned int mt_get_port(unsigned long pin) > +{ > + return ((pin >> 4) & 0xf) << 4; Isn't that equivalent to return pin & 0xf0; Add a comment explaining what's going on here. > +static int mt_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, > + struct pinctrl_gpio_range *range, > + unsigned offset, > + bool input) > +{ > + unsigned int reg_addr; > + unsigned int bit; > + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); > + > + reg_addr = mt_get_port(offset) + pctl->devdata->dir_offset; > + bit = 1 << (offset & 0xf); #include <linux/bitops.h> bit = BIT(offset & 0xf); > + if (input) > + reg_addr += (4 << 1); What is wrong with reg_add += 8; > + else > + reg_addr += 4; > + > + writel(bit, pctl->membase1 + reg_addr); Note: here you're not using mt_pctrl_write_reg(). And I think you should use writel_relaxed(). > +static void mt_gpio_set(struct gpio_chip *chip, unsigned offset, int value) > +{ > + unsigned int reg_addr; > + unsigned int bit; > + struct mt_pinctrl *pctl = dev_get_drvdata(chip->dev); > + > + reg_addr = mt_get_port(offset) + pctl->devdata->dout_offset; > + bit = 1 << (offset & 0xf); BIT(offset & 0xf) > + if (value) > + writel(bit, pctl->membase1 + reg_addr + 4); > + else > + writel(bit, pctl->membase1 + reg_addr + (4 << 1)); +8 > +static int mt_gpio_set_pull_conf(struct pinctrl_dev *pctldev, > + unsigned long pin, enum pin_config_param param, > + enum pin_config_param argument) > +{ > + unsigned int reg_pullen, reg_pullsel; > + unsigned int bit; > + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); > + int pullen = 0; > + int pullsel = 0; > + > + bit = 1 << (pin & 0xf); BIT > + switch (param) { > + case PIN_CONFIG_BIAS_DISABLE: > + pullen = 0; > + pullsel = 0; > + break; > + case PIN_CONFIG_BIAS_PULL_UP: > + mt_pmx_gpio_set_direction(pctldev, NULL, pin, 1); > + pullen = 1; > + pullsel = 1; > + break; > + case PIN_CONFIG_BIAS_PULL_DOWN: > + mt_pmx_gpio_set_direction(pctldev, NULL, pin, 1); > + pullen = 1; > + pullsel = 0; > + break; > + > + case PIN_CONFIG_INPUT_ENABLE: > + mt_pmx_gpio_set_direction(pctldev, NULL, pin, 1); > + break; > + > + case PIN_CONFIG_OUTPUT: > + mt_pmx_gpio_set_direction(pctldev, NULL, pin, 0); > + mt_gpio_set(pctl->chip, pin, argument); > + return 0; > + > + default: > + return -EINVAL; > + } Cut the whitespace newlines above I think. > + if (pullen) > + reg_pullen = mt_get_port(pin) + > + pctl->devdata->pullen_offset + 4; > + else > + reg_pullen = mt_get_port(pin) + > + pctl->devdata->pullen_offset + (4 << 1); +8 > + > + if (pullsel) > + reg_pullsel = mt_get_port(pin) + > + pctl->devdata->pullsel_offset + 4; > + else > + reg_pullsel = mt_get_port(pin) + > + pctl->devdata->pullsel_offset + (4 << 1); +8 > + mt_pctrl_write_reg(pctl, pin, reg_pullen, bit); > + mt_pctrl_write_reg(pctl, pin, reg_pullsel, bit); > + return 0; > +} (...) > +static int mt_pctrl_is_function_valid(struct mt_pinctrl *pctl, > + u32 pin_num, u32 fnum) Return type should be bool. > +{ > + int i; > + > + for (i = 0; i < pctl->devdata->npins; i++) { > + const struct mt_desc_pin *pin = pctl->devdata->pins + i; > + > + if (pin->pin.number == pin_num) { > + struct mt_desc_function *func = pin->functions + fnum; > + > + if (func->name) > + return 1; > + else > + return 0; > + } > + } > + > + return 0; > +} return true/false; > +static int mt_pctrl_dt_node_to_map_func(struct mt_pinctrl *pctl, u32 pin, > + u32 fnum, struct pinctrl_map **maps) > +static int mt_pctrl_dt_node_to_map_config(struct mt_pinctrl *pctl, u32 pin, > + unsigned long *configs, unsigned num_configs, > + struct pinctrl_map **maps) > +static void mt_pctrl_dt_free_map(struct pinctrl_dev *pctldev, > + struct pinctrl_map *map, > + unsigned num_maps) > +static int mt_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, > + struct device_node *node, > + struct pinctrl_map **map, > + unsigned *num_maps) I'm worried about the escalating number of custom function->group and pin config bindings, so I have submitted patches to fix this up and allow for all-generic bindings to be used. See: http://marc.info/?l=devicetree&m=141223584006648&w=2 http://marc.info/?l=devicetree&m=141223586106655&w=2 > + pins = of_find_property(node, "mediatek,pinfunc", NULL); So I want to get rid of "mediatek,pinfunc" and just use "function" for this. > + err = pinconf_generic_parse_dt_config(node, &configs, &num_configs); > + if (num_configs) > + has_config = 1; This implicitly uses "pins", which is nice. > +static int mt_gpio_set_mode(struct pinctrl_dev *pctldev, > + unsigned long pin, unsigned long mode) > +{ > + unsigned int reg_addr; > + unsigned char bit; > + unsigned int val; > + unsigned long flags; > + unsigned int mask = (1L << GPIO_MODE_BITS) - 1; > + struct mt_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); > + > + reg_addr = ((pin / 5) << 4) + pctl->devdata->pinmux_offset; That 5 and 4 needs some explanation, or atleast being #defined for readability. > + spin_lock_irqsave(&pctl->lock, flags); > + val = readl(pctl->membase1 + reg_addr); readl_relaxed()? > +static struct mt_desc_function * > +mt_pctrl_desc_find_irq_by_name(struct mt_pinctrl *pctl, > + const char *pin_name) Why is it called *find_irq_by_name if it returns a function? Seems more like find_function_from_pin_name really. And I don't know if that is such a good idea. > +{ > + int i, j; > + > + for (i = 0; i < pctl->devdata->npins; i++) { > + const struct mt_desc_pin *pin = pctl->devdata->pins + i; > + > + if (!strcmp(pin->pin.name, pin_name)) { > + struct mt_desc_function *func = pin->functions; > + > + for (j = 0; j < PINMUX_MAX_VAL; j++) { > + if (func->irqnum != 255) So why does it end at 255? Seems pretty arbitrary. > + return func; > + > + func++; > + } > + } > + } > + > + return NULL; > +} > +static int mt_pmx_enable(struct pinctrl_dev *pctldev, > + unsigned function, > + unsigned group) This is typically named pmx_set_mux() nowadays, please use the pin control development tree at this point, the change will be upstream in v3.18. > +static const struct pinmux_ops mt_pmx_ops = { > + .get_functions_count = mt_pmx_get_funcs_cnt, > + .get_function_name = mt_pmx_get_func_name, > + .get_function_groups = mt_pmx_get_func_groups, > + .enable = mt_pmx_enable, .set_mux =... > +static int mt_gpio_request(struct gpio_chip *chip, unsigned offset) > +{ > + return pinctrl_request_gpio(chip->base + offset); > +} > + > +static void mt_gpio_free(struct gpio_chip *chip, unsigned offset) > +{ > + pinctrl_free_gpio(chip->base + offset); > +} > > +static int mt_gpio_direction_input(struct gpio_chip *chip, > + unsigned offset) > +{ > + return pinctrl_gpio_direction_input(chip->base + offset); > +} > + > +static int mt_gpio_direction_output(struct gpio_chip *chip, > + unsigned offset, int value) > +{ > + return pinctrl_gpio_direction_output(chip->base + offset); > +} This is nice. > +static int mt_gpio_get_direction(struct gpio_chip *chip, unsigned offset) > +{ > + unsigned int reg_addr; > + unsigned int bit; > + unsigned int read_val = 0; > + > + struct mt_pinctrl *pctl = dev_get_drvdata(chip->dev); > + > + reg_addr = mt_get_port(offset) + pctl->devdata->dir_offset; > + bit = 1 << (offset & 0xf); bit = BIT(offset & 0xf); > + read_val = readl(pctl->membase1 + reg_addr); > + return ((read_val & bit) != 0) ? 1 : 0; No do it like this: return !!(read_val & bit); > +static int mt_gpio_get(struct gpio_chip *chip, unsigned offset) > +{ > + unsigned int reg_addr; > + unsigned int bit; > + unsigned int read_val = 0; > + struct mt_pinctrl *pctl = dev_get_drvdata(chip->dev); > + > + if (mt_gpio_get_direction(chip, offset)) > + reg_addr = mt_get_port(offset) + pctl->devdata->dout_offset; > + else > + reg_addr = mt_get_port(offset) + pctl->devdata->din_offset; > + > + bit = 1 << (offset & 0xf); > + read_val = readl(pctl->membase1 + reg_addr); > + return ((read_val & bit) != 0) ? 1 : 0; > +} Same comments on this function. > +static int mt_gpio_of_xlate(struct gpio_chip *gc, > + const struct of_phandle_args *gpiospec, > + u32 *flags) > +{ > + int pin; > + > + pin = gpiospec->args[0]; > + > + if (pin > (gc->base + gc->ngpio)) > + return -EINVAL; > + > + if (flags) > + *flags = gpiospec->args[1]; > + > + return pin; > +} Why do you need your own xlate function to do this? What is wrong with of_gpio_simple_xlate() which seems to do the same thing? Incidentally that is what you will get if you just leave this pointer in the vtable as unassigned. > +static int mt_gpio_to_irq(struct gpio_chip *chip, unsigned offset) > +{ > + struct mt_pinctrl *pctl = dev_get_drvdata(chip->dev); > + struct mt_pinctrl_group *g = pctl->groups + offset; > + struct mt_desc_function *desc = mt_pctrl_desc_find_irq_by_name( > + pctl, g->name); > + if (!desc) > + return -EINVAL; > + > + mt_gpio_set_mode(pctl->pctl_dev, g->pin, desc->muxval); No mode setting in the .to_irq() function, that makes the irqchip not orthogonal to the gpio_chip. > + return desc->irqnum; > +} By the way use GPIOLIB_IRQCHIP for this and get rid of .to_irq altogether. (...) > +static int mt_pctrl_build_state(struct platform_device *pdev) > +{ > + struct mt_pinctrl *pctl = platform_get_drvdata(pdev); > + int i; > + > + pctl->ngroups = pctl->devdata->npins; > + > + pctl->groups = devm_kzalloc(&pdev->dev, > + pctl->ngroups * sizeof(*pctl->groups), > + GFP_KERNEL); > + if (!pctl->groups) > + return -ENOMEM; > + > + pctl->grp_names = devm_kzalloc(&pdev->dev, > + pctl->ngroups * sizeof(*pctl->grp_names), > + GFP_KERNEL); > + if (!pctl->grp_names) > + return -ENOMEM; > + > + for (i = 0; i < pctl->devdata->npins; i++) { > + const struct mt_desc_pin *pin = pctl->devdata->pins + i; > + struct mt_pinctrl_group *group = pctl->groups + i; > + const char **func_grp; > + > + group->name = pin->pin.name; > + group->pin = pin->pin.number; > + > + func_grp = pctl->grp_names; > + while (*func_grp) > + func_grp++; > + > + *func_grp = pin->pin.name; > + } > + > + return 0; > +} I don't understand what this function is doing so atleast it need and explanation in kerneldoc above it. (...) > + ret = gpiochip_add(pctl->chip); > + if (ret) { > + ret = -EINVAL; > + goto pctrl_error; > + } Here you should be using gpiochip_irqchip_add() followed by gpiochip_set_chained_irqchip(). > + for (i = 0; i < pctl->devdata->npins; i++) { > + const struct mt_desc_pin *pin = pctl->devdata->pins + i; > + > + ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), > + pin->pin.number, > + pin->pin.number, 1); > + if (ret) { > + ret = -EINVAL; > + goto chip_error; > + } Seems complicated but I don't know how complicated your GPIO ranges are indeed. > +chip_error: > + if (gpiochip_remove(pctl->chip)) We have removed the return value from gpiochip_remove() so rebase to upstream here. No if(..) > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h (...) > +struct mt_desc_pin { > + struct pinctrl_pin_desc pin; > + const char *chip; > + struct mt_desc_function *functions; Why does a pin need to know about functions... > +}; Don't invent custom pin container structures. Look: /** * struct pinctrl_pin_desc - boards/machines provide information on their * pins, pads or other muxable units in this struct * @number: unique pin number from the global pin number space * @name: a name for this pin * @drv_data: driver-defined per-pin data. pinctrl core does not touch this */ struct pinctrl_pin_desc { unsigned number; const char *name; void *drv_data; }; You add your stuff to drv_data() rather than including this struct into your own struct. > +#define MT_PIN(_pin, _pad, _chip, ...) \ > + { \ > + .pin = _pin, \ > + .chip = _chip, \ > + .functions = (struct mt_desc_function[]){ \ > + __VA_ARGS__, { } }, \ > + } > + > +#define MT_FUNCTION(_val, _name) \ > + { \ > + .name = _name, \ > + .muxval = _val, \ > + .irqnum = 255, \ 255 eh? > + } > + > +#define MT_FUNCTION_IRQ(_val, _name, _irq) \ > + { \ > + .name = _name, \ > + .muxval = _val, \ > + .irqnum = _irq, \ > + } > + > +struct mt_pinctrl_group { > + const char *name; > + unsigned long config; > + unsigned pin; > +}; > + > +struct mt_gpio_devdata { > + const struct mt_desc_pin *pins; > + int npins; > + unsigned int dir_offset; > + unsigned int ies_offset; > + unsigned int pullen_offset; > + unsigned int pullsel_offset; > + unsigned int drv_offset; > + unsigned int invser_offset; > + unsigned int dout_offset; > + unsigned int din_offset; > + unsigned int pinmux_offset; > + unsigned short type1_start; > + unsigned short type1_end; > +}; Add some kerneldoc for this struct as it't not apparently self-evident. > +static const struct mt_desc_pin mt_pins_mt8135[] = { > + MT_PIN( > + PINCTRL_PIN(0, "MSDC0_DAT7"), > + "D21", "mt8135", > + MT_FUNCTION(0, "GPIO0"), > + MT_FUNCTION(1, "MSDC0_DAT7"), > + MT_FUNCTION_IRQ(2, "EINT49", 49), > + MT_FUNCTION(3, "I2SOUT_DAT"), > + MT_FUNCTION(4, "DAC_DAT_OUT"), > + MT_FUNCTION(5, "PCM1_DO"), > + MT_FUNCTION(6, "SPI1_MO"), > + MT_FUNCTION(7, "NALE") > + ), I don't think this is a good idea and to encode all functions in a pin, rather the revers is custom: define all functions and collect arrays of pin numbers in the definitions of pin groups, then map the functions and groups of pins together. Look at other drivers for examples.. I don't like the device tree bindings for the very same reason: it moves all this numeric encoding of pin-functions into the device tree instead of combining group+function strings like most drivers do. Is there some special reason to why you're turning this on its head? Yours, Linus Walleij ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 2/4] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135. 2014-10-02 13:38 ` Linus Walleij @ 2014-10-06 10:35 ` Joe.C 2014-10-21 9:08 ` Linus Walleij 0 siblings, 1 reply; 27+ messages in thread From: Joe.C @ 2014-10-06 10:35 UTC (permalink / raw) To: Linus Walleij Cc: Mark Rutland, Ashwin Chaugule, Hongzhou.Yang, Vladimir Murzin, Russell King, srv_heupstream, Pawel Moll, Ian Campbell Hi Linus, Thanks for your detail review. We'll fix the driver according to your suggestion in next version. Please see the inline comments below for thing that I feel deserve discussion: On Thu, 2014-10-02 at 15:38 +0200, Linus Walleij wrote: (...) > > +static struct mt_desc_function * > > +mt_pctrl_desc_find_irq_by_name(struct mt_pinctrl *pctl, > > + const char *pin_name) > > Why is it called *find_irq_by_name if it returns a > function? Seems more like find_function_from_pin_name > really. > > And I don't know if that is such a good idea. In 8135 & 6589, not every gpio pin support interrupt function. For those support interrupt, it will have a EINT function and use a different EINT offset number. In 8127, EINT support is merged into gpio function, but they still use a different EINT offset number. For example, mt8135 pin 0 use function 2 for interrupt support, EINT number for this pin is 49. MT_PIN( PINCTRL_PIN(0, "MSDC0_DAT7"), "D21", "mt8135", MT_FUNCTION(0, "GPIO0"), MT_FUNCTION(1, "MSDC0_DAT7"), MT_FUNCTION_IRQ(2, "EINT49", 49), MT_FUNCTION(3, "I2SOUT_DAT"), MT_FUNCTION(4, "DAC_DAT_OUT"), MT_FUNCTION(5, "PCM1_DO"), MT_FUNCTION(6, "SPI1_MO"), MT_FUNCTION(7, "NALE") ), This function is used to find EINT function for the pin. Maybe we should name this mt_pctrl_desc_find_irq_function_from_name to make it more clear. > > +{ > > + int i, j; > > + > > + for (i = 0; i < pctl->devdata->npins; i++) { > > + const struct mt_desc_pin *pin = pctl->devdata->pins + i; > > + > > + if (!strcmp(pin->pin.name, pin_name)) { > > + struct mt_desc_function *func = pin->functions; > > + > > + for (j = 0; j < PINMUX_MAX_VAL; j++) { > > + if (func->irqnum != 255) > > So why does it end at 255? Seems pretty arbitrary. If a function support interrupt, we put its interrupt number in irqnum, otherwise it will be 255. Does it make it more clear if we use macro name MT_NO_EINT_SUPPORT? > > +static int mt_gpio_to_irq(struct gpio_chip *chip, unsigned offset) > > +{ > > + struct mt_pinctrl *pctl = dev_get_drvdata(chip->dev); > > + struct mt_pinctrl_group *g = pctl->groups + offset; > > + struct mt_desc_function *desc = mt_pctrl_desc_find_irq_by_name( > > + pctl, g->name); > > + if (!desc) > > + return -EINVAL; > > + > > + mt_gpio_set_mode(pctl->pctl_dev, g->pin, desc->muxval); > > No mode setting in the .to_irq() function, that makes the irqchip > not orthogonal to the gpio_chip. I see, we should do this in irq_request_resources instead. > > > + return desc->irqnum; > > +} > > By the way use GPIOLIB_IRQCHIP for this and get rid > of .to_irq altogether. > (...) > > + ret = gpiochip_add(pctl->chip); > > + if (ret) { > > + ret = -EINVAL; > > + goto pctrl_error; > > + } > > Here you should be using gpiochip_irqchip_add() > followed by gpiochip_set_chained_irqchip(). We use a different interrupt number than gpio pin number. I think it more nature to use EINT interrupt number as the hw_number, so I think we can't use gpiochip_irqchip_add and we still need to provide our own .to_irq mapping function. > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h > (...) > > +static const struct mt_desc_pin mt_pins_mt8135[] = { > > + MT_PIN( > > + PINCTRL_PIN(0, "MSDC0_DAT7"), > > + "D21", "mt8135", > > + MT_FUNCTION(0, "GPIO0"), > > + MT_FUNCTION(1, "MSDC0_DAT7"), > > + MT_FUNCTION_IRQ(2, "EINT49", 49), > > + MT_FUNCTION(3, "I2SOUT_DAT"), > > + MT_FUNCTION(4, "DAC_DAT_OUT"), > > + MT_FUNCTION(5, "PCM1_DO"), > > + MT_FUNCTION(6, "SPI1_MO"), > > + MT_FUNCTION(7, "NALE") > > + ), > > I don't think this is a good idea and to encode all functions in a pin, > rather the revers is custom: define all functions and collect arrays > of pin numbers in the definitions of pin groups, then map the functions > and groups of pins together. > > Look at other drivers for examples.. > > I don't like the device tree bindings for the very same reason: it moves > all this numeric encoding of pin-functions into the device tree instead > of combining group+function strings like most drivers do. > > Is there some special reason to why you're turning this on its head? > > Yours, > Linus Walleij Our driver code is based on sunxi driver. We got base source structure and this pin descriptor array from sunxi. We follow imx's use of device tree macros. Our pinctrl can set mux for each individual pins, so I think this pin_desc array fully describe the capability of pinctrl HW. It is generated from datasheet, which can easily prove it correctness. With the help of device tree header file, pinctrl users can describe pins used by their components easily in device tree. The change could be fully tested with their driver to make sure it is correct. Also, we don't need to change pinctrl driver just to add or correct a group for the component. While it might still be possible to generate group+function array based on datasheet, IMHO the structure will be more complicate and harder to prove the correctness. So we choose to use descriptor array + macros in device tree because it is quite simple to generate the pin descriptors and easier to notice if there's error in device tree pin groups description. Even if we change to use group+function strings as you said, we probably will still use this array to find out which function we should set for each pin in a group. Regards, Joe.C ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 2/4] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135. 2014-10-06 10:35 ` Joe.C @ 2014-10-21 9:08 ` Linus Walleij 0 siblings, 0 replies; 27+ messages in thread From: Linus Walleij @ 2014-10-21 9:08 UTC (permalink / raw) To: Joe.C Cc: Hongzhou.Yang, Rob Herring, Matthias Brugger, srv_heupstream, Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely On Mon, Oct 6, 2014 at 12:35 PM, Joe.C <yingjoe.chen@mediatek.com> wrote: > On Thu, 2014-10-02 at 15:38 +0200, Linus Walleij wrote: > (...) >> > +static struct mt_desc_function * >> > +mt_pctrl_desc_find_irq_by_name(struct mt_pinctrl *pctl, >> > + const char *pin_name) >> >> Why is it called *find_irq_by_name if it returns a >> function? Seems more like find_function_from_pin_name >> really. >> >> And I don't know if that is such a good idea. > > In 8135 & 6589, not every gpio pin support interrupt function. For those > support interrupt, it will have a EINT function and use a different EINT > offset number. > In 8127, EINT support is merged into gpio function, but they still use a > different EINT offset number. (...) > This function is used to find EINT function for the pin. Maybe we should > name this mt_pctrl_desc_find_irq_function_from_name to make it more > clear. OK such translation is usually the work of the irqdomain. Is there some reason why it is not used in this driver then? >> > + for (j = 0; j < PINMUX_MAX_VAL; j++) { >> > + if (func->irqnum != 255) >> >> So why does it end at 255? Seems pretty arbitrary. > > If a function support interrupt, we put its interrupt number in irqnum, > otherwise it will be 255. Does it make it more clear if we use macro > name MT_NO_EINT_SUPPORT? Yes. > We use a different interrupt number than gpio pin number. I think it > more nature to use EINT interrupt number as the hw_number, so I think we > can't use gpiochip_irqchip_add and we still need to provide our > own .to_irq mapping function. You should be able to use irqdomain to translate I think. > While it might still be possible to generate group+function array based > on datasheet, IMHO the structure will be more complicate and harder to > prove the correctness. > > So we choose to use descriptor array + macros in device tree because it > is quite simple to generate the pin descriptors and easier to notice if > there's error in device tree pin groups description. There is a parallel discussion on this, or two maybe. The number of pin control bindings is exploding and I need to push back. Please help out defining generic pin control bindings for this use case and we can move forward. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 3/4] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx. 2014-09-23 3:39 [PATCH v2 0/4] Add Mediatek SoC Pinctrl/GPIO driver for MT8135 Hongzhou.Yang 2014-09-23 3:39 ` [PATCH v2 1/4] arm: mediatek: Add config option for mediatek SoCs Hongzhou.Yang 2014-09-23 3:39 ` [PATCH v2 2/4] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135 Hongzhou.Yang @ 2014-09-23 3:39 ` Hongzhou.Yang [not found] ` <1411443545-24951-4-git-send-email-srv_hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> 2014-09-23 3:39 ` [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135 Hongzhou.Yang [not found] ` <1411443545-24951-1-git-send-email-srv_hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> 4 siblings, 1 reply; 27+ messages in thread From: Hongzhou.Yang @ 2014-09-23 3:39 UTC (permalink / raw) To: Rob Herring, Linus Walleij, Matthias Brugger Cc: Mark Rutland, devicetree, Vladimir Murzin, Russell King, srv_heupstream, Pawel Moll, Ian Campbell, Hongzhou Yang, Catalin Marinas, linux-kernel, Ashwin Chaugule, Sascha Hauer, Kumar Gala, Grant Likely, Joe.C, dandan.he, linux-arm-kernel From: Hongzhou Yang <hongzhou.yang@mediatek.com> Add devicetree bindings for Mediatek SoC pinctrl driver. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> --- .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 98 ++++++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt new file mode 100644 index 0000000..ee028cb --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -0,0 +1,98 @@ +* Mediatek MT65XX Pin Controller + +The Mediatek's Pin controller is used to control GPIO pins. + +Required properties: +- compatible: value should be either of the following. + (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. +- reg: Should contain the register physical address and length for the + pin controller. +- gpio-controller : Marks the device node as a gpio controller. +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + Eg: <&pio 6 0> + <[phandle of the gpio controller node] + [pin number within the gpio controller] + [flags]> + + Values for gpio specifier: + - Pin number: is a value between 0 to 202. + - Flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>. + Only the following flags are supported: + 0 - GPIO_ACTIVE_HIGH + 1 - GPIO_ACTIVE_LOW + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices. + +A pinctrl node should contain at least one subnodes representing the +pinctrl groups available on the machine. Each subnode will list the +pins it needs, and how they should be configured, with regard to muxer +configuration and pullups. If one of these options is +not set, its actual value will be unspecified. + +Required subnode-properties: + +- mediatek,pinfunc: List of gpio number and function to mux. + +The mediatek,pinfunc can use defines directly, +which are already defind in boot/dts/mt8135-pinfunc.h. + +Optional subnode-properties: +- generic pin configuration option to use, bias-disable, bias-pull-down, + bias-pull,up, output-low and output-high are valid. + Example : + i2c0_pins_a { + mediatek,pinfunc = <MT8135_PIN_195_SDA1__FUNC_SDA1>; + bias-disable; + }; + +The mediatek,pinfunc can be either a single value or an array. +If it is an array, that means all pins use same config in this node. + + +Examples: + +pinctrl@01c20800 { + compatible = "mediatek,mt8135-pinctrl"; + reg = <0x01c20800 0x400>; + gpio-controller; + #gpio-cells = <2>; + + i2c0_pins_a: i2c0@0 { + mediatek,pinfunc = <MT8135_PIN_100_SDA0__FUNC_SDA0 MT8135_PIN_101_SCL0__FUNC_SCL0>; + bias-disable; + }; + + i2c1_pins_a: i2c1@0 { + mediatek,pinfunc = <MT8135_PIN_195_SDA1__FUNC_SDA1 MT8135_PIN_196_SCL1__FUNC_SCL1>; + bias-pull-up; + }; + + i2c2_pins_a: i2c2@0 { + mediatek,pinfunc = <MT8135_PIN_193_SDA2__FUNC_SDA2 MT8135_PIN_194_SCL2__FUNC_SCL2>; + bias-pull-down; + }; + + i2c3_pins_a: i2c3@0 { + mediatek,pinfunc = <MT8135_PIN_35_SCL3__FUNC_SCL3 MT8135_PIN_36_SDA3__FUNC_SDA3>; + bias-disable; + output-high; + }; + + uart2_pins_a: uart2@0 { + mediatek,pinfunc = <MT8135_PIN_53_URXD2__FUNC_URXD2 MT8135_PIN_54_UTXD2__FUNC_UTXD2>; + bias-disable; + output-low; + }; + + uart3_pins_a: uart3@0 { + mediatek,pinfunc = <MT8135_PIN_191_URXD3__FUNC_URXD3 MT8135_PIN_192_UTXD3__FUNC_UTXD3>; + bias-disable; + output-low; + }; + ... + +}; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 27+ messages in thread
[parent not found: <1411443545-24951-4-git-send-email-srv_hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH v2 3/4] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx. [not found] ` <1411443545-24951-4-git-send-email-srv_hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> @ 2014-10-02 14:00 ` Linus Walleij 2014-10-02 14:41 ` Lucas Stach 0 siblings, 1 reply; 27+ messages in thread From: Linus Walleij @ 2014-10-02 14:00 UTC (permalink / raw) To: Hongzhou.Yang Cc: Rob Herring, Matthias Brugger, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely, Hongzhou Yang, Joe.C, Catalin Marinas, Vladimir Murzin, Ashwin Chaugule, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, dandan.he-NuS5LvNUpcJWk0Htik3J/w On Tue, Sep 23, 2014 at 5:39 AM, Hongzhou.Yang <srv_hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote: > From: Hongzhou Yang <hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> > > Add devicetree bindings for Mediatek SoC pinctrl driver. > > Signed-off-by: Hongzhou Yang <hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> I have worked on generic pin control bindings a bit because it is getting out of hand with all these custom bindings. See: http://marc.info/?l=devicetree&m=141223584006648&w=2 Especially. > +- mediatek,pinfunc: List of gpio number and function to mux. A "GPIO number" and a "pin number" is not the same thing at all, this is very confusing. Those are two separate number spaces. This is likely about the pin numbers. > +The mediatek,pinfunc can use defines directly, > +which are already defind in boot/dts/mt8135-pinfunc.h. > + > +Optional subnode-properties: > +- generic pin configuration option to use, bias-disable, bias-pull-down, > + bias-pull,up, output-low and output-high are valid. > + Example : > + i2c0_pins_a { > + mediatek,pinfunc = <MT8135_PIN_195_SDA1__FUNC_SDA1>; > + bias-disable; > + }; I don't like this approach at all. I prefer that pins are put into groups named by strings, like "i2c0-pos0" inside the driver and then connected to function with a certain device-related name, such as "i2c0". Then put the pin configuration (bias etc) in a separate node in the same state definition like that: i2c0_pins_a { function = "i2c0"; groups = "i2c0-pos0"; }; i2c0_pins_b { bias-disable; }; Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 3/4] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx. 2014-10-02 14:00 ` Linus Walleij @ 2014-10-02 14:41 ` Lucas Stach 2014-10-21 8:45 ` Linus Walleij 0 siblings, 1 reply; 27+ messages in thread From: Lucas Stach @ 2014-10-02 14:41 UTC (permalink / raw) To: Linus Walleij Cc: Hongzhou.Yang, Mark Rutland, Ashwin Chaugule, Vladimir Murzin, Russell King, srv_heupstream, Pawel Moll, Ian Campbell Am Donnerstag, den 02.10.2014, 16:00 +0200 schrieb Linus Walleij: > On Tue, Sep 23, 2014 at 5:39 AM, Hongzhou.Yang > <srv_hongzhou.yang@mediatek.com> wrote: > > > From: Hongzhou Yang <hongzhou.yang@mediatek.com> > > > > Add devicetree bindings for Mediatek SoC pinctrl driver. > > > > Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> > > I have worked on generic pin control bindings a bit because it > is getting out of hand with all these custom bindings. > > See: > http://marc.info/?l=devicetree&m=141223584006648&w=2 > > Especially. > > > +- mediatek,pinfunc: List of gpio number and function to mux. > > A "GPIO number" and a "pin number" is not the same thing at all, > this is very confusing. Those are two separate number spaces. > This is likely about the pin numbers. > > > +The mediatek,pinfunc can use defines directly, > > +which are already defind in boot/dts/mt8135-pinfunc.h. > > + > > +Optional subnode-properties: > > +- generic pin configuration option to use, bias-disable, bias-pull-down, > > + bias-pull,up, output-low and output-high are valid. > > + Example : > > + i2c0_pins_a { > > + mediatek,pinfunc = <MT8135_PIN_195_SDA1__FUNC_SDA1>; > > + bias-disable; > > + }; > > I don't like this approach at all. > > I prefer that pins are put into groups named by strings, like "i2c0-pos0" > inside the driver and then connected to function with a certain > device-related name, such as "i2c0". > So we should create artificial software groups where there are none in hardware? This sounds really backward to me. Almost every new SoC out there has the ability to mux every pin on it's own. By defining artificial software groups in the driver we are pushing constraints in the binding that don't really exist in hardware. So if someone comes up with a pin usage that isn't covered by the existing groups we need to change the binding. Experience from working with lots of hardware engineers tells us that if something can be done (if there are no constraints in HW) it will be done sooner or later. If the hardware allows this much freedom we should also allow it in the pinctrl binding. > Then put the pin configuration (bias etc) in a separate node in the same > state definition like that: > > i2c0_pins_a { > function = "i2c0"; > groups = "i2c0-pos0"; > }; > i2c0_pins_b { > bias-disable; > }; The problem with that is that different pins might need different configuration for the same muxed function. To properly reflect this we would need to duplicate the pin definitions. One popular example is the MMC interface where part of the pins need to have a pull-up, while others don't. How would you reflect this with the DT description above? Regards, Lucas -- Pengutronix e.K. | Lucas Stach | Industrial Linux Solutions | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 3/4] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx. 2014-10-02 14:41 ` Lucas Stach @ 2014-10-21 8:45 ` Linus Walleij 0 siblings, 0 replies; 27+ messages in thread From: Linus Walleij @ 2014-10-21 8:45 UTC (permalink / raw) To: Lucas Stach Cc: Hongzhou.Yang, Mark Rutland, Ashwin Chaugule, Vladimir Murzin, Russell King, srv_heupstream, Pawel Moll, Ian Campbell On Thu, Oct 2, 2014 at 4:41 PM, Lucas Stach <l.stach@pengutronix.de> wrote: > Am Donnerstag, den 02.10.2014, 16:00 +0200 schrieb Linus Walleij: >> > +The mediatek,pinfunc can use defines directly, >> > +which are already defind in boot/dts/mt8135-pinfunc.h. >> > + >> > +Optional subnode-properties: >> > +- generic pin configuration option to use, bias-disable, bias-pull-down, >> > + bias-pull,up, output-low and output-high are valid. >> > + Example : >> > + i2c0_pins_a { >> > + mediatek,pinfunc = <MT8135_PIN_195_SDA1__FUNC_SDA1>; >> > + bias-disable; >> > + }; >> >> I don't like this approach at all. >> >> I prefer that pins are put into groups named by strings, like "i2c0-pos0" >> inside the driver and then connected to function with a certain >> device-related name, such as "i2c0". >> > > So we should create artificial software groups where there are none in > hardware? This sounds really backward to me. Almost every new SoC out > there has the ability to mux every pin on it's own. This discussion has been had again and again and again in the past, please consult the mail archives before repeating history. Usually the number of function to group mappings look like they are arbitrary but in electronic practice they are not. In practice there is one or two places where e.g. the MMC card will be connected, you will not use every second pin of the MMC connector for half an SPI port, even if it is possible in theory. > By defining artificial software groups in the driver we are pushing > constraints in the binding that don't really exist in hardware. The binding is supposed to be helpful when configuring the system, so for a person setting up a new device tree that may be helpful. It gives them some info on what is electronically reasonable. > So if > someone comes up with a pin usage that isn't covered by the existing > groups we need to change the binding. In my experience people don't change bindings very much, because the life cycle of an SoC is so short. They get it right the first time or not at all. > If the hardware allows this much freedom we should also allow it in the > pinctrl binding. I have to push back on this, because the pin control bindings are exploding, and it is irresponsible of me as subsystem maintainer to just allow anything. Can you think of something that is both generic and helpful when working with other systems than this? What we need to do is get away from all "necessarily different" bindings. >> Then put the pin configuration (bias etc) in a separate node in the same >> state definition like that: >> >> i2c0_pins_a { >> function = "i2c0"; >> groups = "i2c0-pos0"; >> }; >> i2c0_pins_b { >> bias-disable; >> }; > > The problem with that is that different pins might need different > configuration for the same muxed function. To properly reflect this we > would need to duplicate the pin definitions. One popular example is the > MMC interface where part of the pins need to have a pull-up, while > others don't. How would you reflect this with the DT description above? That's no problem. Muxing is group+function and configuration is per-pin. See this example: uart2 { uart2_default_mode: uart2_default { default_mux { function = "u2"; groups = "u2rxtx_c_1"; }; default_cfg1 { pins = "GPIO29_W2"; /* RXD */ bias-pull-up; low-power-disable; }; default_cfg2 { pins = "GPIO30_W3"; /* TXD */ output-high; low-power-disable; }; }; uart2_sleep_mode: uart2_sleep { sleep_cfg1 { pins = "GPIO29_W2"; /* RXD */ low-power-enable; }; sleep_cfg2 { pins = "GPIO30_W3"; /* TXD */ low-power-enable; }; }; }; Yours, Linus Walleij ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. 2014-09-23 3:39 [PATCH v2 0/4] Add Mediatek SoC Pinctrl/GPIO driver for MT8135 Hongzhou.Yang ` (2 preceding siblings ...) 2014-09-23 3:39 ` [PATCH v2 3/4] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx Hongzhou.Yang @ 2014-09-23 3:39 ` Hongzhou.Yang 2014-09-23 13:03 ` Arnd Bergmann 2014-09-24 11:23 ` Linus Walleij [not found] ` <1411443545-24951-1-git-send-email-srv_hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> 4 siblings, 2 replies; 27+ messages in thread From: Hongzhou.Yang @ 2014-09-23 3:39 UTC (permalink / raw) To: Rob Herring, Linus Walleij, Matthias Brugger Cc: Mark Rutland, devicetree, Vladimir Murzin, Russell King, srv_heupstream, Pawel Moll, Ian Campbell, Hongzhou Yang, Catalin Marinas, linux-kernel, Ashwin Chaugule, Sascha Hauer, Kumar Gala, Grant Likely, Joe.C, dandan.he, linux-arm-kernel From: Hongzhou Yang <hongzhou.yang@mediatek.com> Add pinctrl node to mt8135.dtsi. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> --- arch/arm/boot/dts/mt8135-pinfunc.h | 1304 ++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/mt8135.dtsi | 11 + 2 files changed, 1315 insertions(+) create mode 100644 arch/arm/boot/dts/mt8135-pinfunc.h diff --git a/arch/arm/boot/dts/mt8135-pinfunc.h b/arch/arm/boot/dts/mt8135-pinfunc.h new file mode 100644 index 0000000..975012e --- /dev/null +++ b/arch/arm/boot/dts/mt8135-pinfunc.h @@ -0,0 +1,1304 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DTS_MT8135_PINFUNC_H +#define __DTS_MT8135_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MT_PIN_NO(0) | 0) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MT_PIN_NO(0) | 1) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MT_PIN_NO(0) | 2) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MT_PIN_NO(0) | 3) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MT_PIN_NO(0) | 4) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MT_PIN_NO(0) | 5) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MT_PIN_NO(0) | 6) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MT_PIN_NO(0) | 7) + +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_GPIO1 (MT_PIN_NO(1) | 0) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MT_PIN_NO(1) | 1) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_EINT48 (MT_PIN_NO(1) | 2) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_I2SIN_WS (MT_PIN_NO(1) | 3) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_DAC_WS (MT_PIN_NO(1) | 4) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_PCM1_WS (MT_PIN_NO(1) | 5) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_SPI1_CSN (MT_PIN_NO(1) | 6) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_NCLE (MT_PIN_NO(1) | 7) + +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_GPIO2 (MT_PIN_NO(2) | 0) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MT_PIN_NO(2) | 1) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_EINT47 (MT_PIN_NO(2) | 2) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_I2SIN_CK (MT_PIN_NO(2) | 3) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_DAC_CK (MT_PIN_NO(2) | 4) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_PCM1_CK (MT_PIN_NO(2) | 5) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_SPI1_CLK (MT_PIN_NO(2) | 6) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_NLD4 (MT_PIN_NO(2) | 7) + +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_GPIO3 (MT_PIN_NO(3) | 0) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MT_PIN_NO(3) | 1) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_EINT46 (MT_PIN_NO(3) | 2) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_A_FUNC_CK (MT_PIN_NO(3) | 3) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_LSCE1B_2X (MT_PIN_NO(3) | 6) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_NLD5 (MT_PIN_NO(3) | 7) + +#define MT8135_PIN_4_MSDC0_CMD__FUNC_GPIO4 (MT_PIN_NO(4) | 0) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD (MT_PIN_NO(4) | 1) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_EINT41 (MT_PIN_NO(4) | 2) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_A_FUNC_DOUT_0 (MT_PIN_NO(4) | 3) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_USB_TEST_IO_0 (MT_PIN_NO(4) | 5) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_LRSTB_2X (MT_PIN_NO(4) | 6) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_NRNB (MT_PIN_NO(4) | 7) + +#define MT8135_PIN_5_MSDC0_CLK__FUNC_GPIO5 (MT_PIN_NO(5) | 0) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK (MT_PIN_NO(5) | 1) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_EINT40 (MT_PIN_NO(5) | 2) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_A_FUNC_DOUT_1 (MT_PIN_NO(5) | 3) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_USB_TEST_IO_1 (MT_PIN_NO(5) | 5) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_LPTE (MT_PIN_NO(5) | 6) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_NREB (MT_PIN_NO(5) | 7) + +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_GPIO6 (MT_PIN_NO(6) | 0) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MT_PIN_NO(6) | 1) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_EINT45 (MT_PIN_NO(6) | 2) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_A_FUNC_DOUT_2 (MT_PIN_NO(6) | 3) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_USB_TEST_IO_2 (MT_PIN_NO(6) | 5) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_LSCE0B_2X (MT_PIN_NO(6) | 6) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_NLD7 (MT_PIN_NO(6) | 7) + +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_GPIO7 (MT_PIN_NO(7) | 0) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MT_PIN_NO(7) | 1) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_EINT44 (MT_PIN_NO(7) | 2) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_A_FUNC_DOUT_3 (MT_PIN_NO(7) | 3) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_USB_TEST_IO_3 (MT_PIN_NO(7) | 5) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_LSA0_2X (MT_PIN_NO(7) | 6) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_NLD14 (MT_PIN_NO(7) | 7) + +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_GPIO8 (MT_PIN_NO(8) | 0) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MT_PIN_NO(8) | 1) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_EINT43 (MT_PIN_NO(8) | 2) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_USB_TEST_IO_4 (MT_PIN_NO(8) | 5) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_LSCK_2X (MT_PIN_NO(8) | 6) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_NLD11 (MT_PIN_NO(8) | 7) + +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_GPIO9 (MT_PIN_NO(9) | 0) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MT_PIN_NO(9) | 1) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_EINT42 (MT_PIN_NO(9) | 2) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_USB_TEST_IO_5 (MT_PIN_NO(9) | 5) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_LSDA_2X (MT_PIN_NO(9) | 6) + +#define MT8135_PIN_10_NCEB0__FUNC_GPIO10 (MT_PIN_NO(10) | 0) +#define MT8135_PIN_10_NCEB0__FUNC_NCEB0 (MT_PIN_NO(10) | 1) +#define MT8135_PIN_10_NCEB0__FUNC_EINT139 (MT_PIN_NO(10) | 2) +#define MT8135_PIN_10_NCEB0__FUNC_TESTA_OUT4 (MT_PIN_NO(10) | 7) + +#define MT8135_PIN_11_NCEB1__FUNC_GPIO11 (MT_PIN_NO(11) | 0) +#define MT8135_PIN_11_NCEB1__FUNC_NCEB1 (MT_PIN_NO(11) | 1) +#define MT8135_PIN_11_NCEB1__FUNC_EINT140 (MT_PIN_NO(11) | 2) +#define MT8135_PIN_11_NCEB1__FUNC_USB_DRVVBUS (MT_PIN_NO(11) | 6) +#define MT8135_PIN_11_NCEB1__FUNC_TESTA_OUT5 (MT_PIN_NO(11) | 7) + +#define MT8135_PIN_12_NRNB__FUNC_GPIO12 (MT_PIN_NO(12) | 0) +#define MT8135_PIN_12_NRNB__FUNC_NRNB (MT_PIN_NO(12) | 1) +#define MT8135_PIN_12_NRNB__FUNC_EINT141 (MT_PIN_NO(12) | 2) +#define MT8135_PIN_12_NRNB__FUNC_A_FUNC_DOUT_4 (MT_PIN_NO(12) | 3) +#define MT8135_PIN_12_NRNB__FUNC_TESTA_OUT6 (MT_PIN_NO(12) | 7) + +#define MT8135_PIN_13_NCLE__FUNC_GPIO13 (MT_PIN_NO(13) | 0) +#define MT8135_PIN_13_NCLE__FUNC_NCLE (MT_PIN_NO(13) | 1) +#define MT8135_PIN_13_NCLE__FUNC_EINT142 (MT_PIN_NO(13) | 2) +#define MT8135_PIN_13_NCLE__FUNC_A_FUNC_DOUT_5 (MT_PIN_NO(13) | 3) +#define MT8135_PIN_13_NCLE__FUNC_CM2PDN_1X (MT_PIN_NO(13) | 4) +#define MT8135_PIN_13_NCLE__FUNC_NALE (MT_PIN_NO(13) | 6) +#define MT8135_PIN_13_NCLE__FUNC_TESTA_OUT7 (MT_PIN_NO(13) | 7) + +#define MT8135_PIN_14_NALE__FUNC_GPIO14 (MT_PIN_NO(14) | 0) +#define MT8135_PIN_14_NALE__FUNC_NALE (MT_PIN_NO(14) | 1) +#define MT8135_PIN_14_NALE__FUNC_EINT143 (MT_PIN_NO(14) | 2) +#define MT8135_PIN_14_NALE__FUNC_A_FUNC_DOUT_6 (MT_PIN_NO(14) | 3) +#define MT8135_PIN_14_NALE__FUNC_CM2MCLK_1X (MT_PIN_NO(14) | 4) +#define MT8135_PIN_14_NALE__FUNC_IRDA_RXD (MT_PIN_NO(14) | 5) +#define MT8135_PIN_14_NALE__FUNC_NCLE (MT_PIN_NO(14) | 6) +#define MT8135_PIN_14_NALE__FUNC_TESTA_OUT8 (MT_PIN_NO(14) | 7) + +#define MT8135_PIN_15_NREB__FUNC_GPIO15 (MT_PIN_NO(15) | 0) +#define MT8135_PIN_15_NREB__FUNC_NREB (MT_PIN_NO(15) | 1) +#define MT8135_PIN_15_NREB__FUNC_EINT144 (MT_PIN_NO(15) | 2) +#define MT8135_PIN_15_NREB__FUNC_A_FUNC_DOUT_7 (MT_PIN_NO(15) | 3) +#define MT8135_PIN_15_NREB__FUNC_CM2RST_1X (MT_PIN_NO(15) | 4) +#define MT8135_PIN_15_NREB__FUNC_IRDA_TXD (MT_PIN_NO(15) | 5) +#define MT8135_PIN_15_NREB__FUNC_TESTA_OUT9 (MT_PIN_NO(15) | 7) + +#define MT8135_PIN_16_NWEB__FUNC_GPIO16 (MT_PIN_NO(16) | 0) +#define MT8135_PIN_16_NWEB__FUNC_NWEB (MT_PIN_NO(16) | 1) +#define MT8135_PIN_16_NWEB__FUNC_EINT145 (MT_PIN_NO(16) | 2) +#define MT8135_PIN_16_NWEB__FUNC_A_FUNC_DIN_0 (MT_PIN_NO(16) | 3) +#define MT8135_PIN_16_NWEB__FUNC_CM2PCLK_1X (MT_PIN_NO(16) | 4) +#define MT8135_PIN_16_NWEB__FUNC_IRDA_PDN (MT_PIN_NO(16) | 5) +#define MT8135_PIN_16_NWEB__FUNC_TESTA_OUT10 (MT_PIN_NO(16) | 7) + +#define MT8135_PIN_17_NLD0__FUNC_GPIO17 (MT_PIN_NO(17) | 0) +#define MT8135_PIN_17_NLD0__FUNC_NLD0 (MT_PIN_NO(17) | 1) +#define MT8135_PIN_17_NLD0__FUNC_EINT146 (MT_PIN_NO(17) | 2) +#define MT8135_PIN_17_NLD0__FUNC_A_FUNC_DIN_1 (MT_PIN_NO(17) | 3) +#define MT8135_PIN_17_NLD0__FUNC_CM2DAT_1X_0 (MT_PIN_NO(17) | 4) +#define MT8135_PIN_17_NLD0__FUNC_I2SIN_CK (MT_PIN_NO(17) | 5) +#define MT8135_PIN_17_NLD0__FUNC_DAC_CK (MT_PIN_NO(17) | 6) +#define MT8135_PIN_17_NLD0__FUNC_TESTA_OUT11 (MT_PIN_NO(17) | 7) + +#define MT8135_PIN_18_NLD1__FUNC_GPIO18 (MT_PIN_NO(18) | 0) +#define MT8135_PIN_18_NLD1__FUNC_NLD1 (MT_PIN_NO(18) | 1) +#define MT8135_PIN_18_NLD1__FUNC_EINT147 (MT_PIN_NO(18) | 2) +#define MT8135_PIN_18_NLD1__FUNC_A_FUNC_DIN_2 (MT_PIN_NO(18) | 3) +#define MT8135_PIN_18_NLD1__FUNC_CM2DAT_1X_1 (MT_PIN_NO(18) | 4) +#define MT8135_PIN_18_NLD1__FUNC_I2SIN_WS (MT_PIN_NO(18) | 5) +#define MT8135_PIN_18_NLD1__FUNC_DAC_WS (MT_PIN_NO(18) | 6) +#define MT8135_PIN_18_NLD1__FUNC_TESTA_OUT12 (MT_PIN_NO(18) | 7) + +#define MT8135_PIN_19_NLD2__FUNC_GPIO19 (MT_PIN_NO(19) | 0) +#define MT8135_PIN_19_NLD2__FUNC_NLD2 (MT_PIN_NO(19) | 1) +#define MT8135_PIN_19_NLD2__FUNC_EINT148 (MT_PIN_NO(19) | 2) +#define MT8135_PIN_19_NLD2__FUNC_A_FUNC_DIN_3 (MT_PIN_NO(19) | 3) +#define MT8135_PIN_19_NLD2__FUNC_CM2DAT_1X_2 (MT_PIN_NO(19) | 4) +#define MT8135_PIN_19_NLD2__FUNC_I2SOUT_DAT (MT_PIN_NO(19) | 5) +#define MT8135_PIN_19_NLD2__FUNC_DAC_DAT_OUT (MT_PIN_NO(19) | 6) +#define MT8135_PIN_19_NLD2__FUNC_TESTA_OUT13 (MT_PIN_NO(19) | 7) + +#define MT8135_PIN_20_NLD3__FUNC_GPIO20 (MT_PIN_NO(20) | 0) +#define MT8135_PIN_20_NLD3__FUNC_NLD3 (MT_PIN_NO(20) | 1) +#define MT8135_PIN_20_NLD3__FUNC_EINT149 (MT_PIN_NO(20) | 2) +#define MT8135_PIN_20_NLD3__FUNC_A_FUNC_DIN_4 (MT_PIN_NO(20) | 3) +#define MT8135_PIN_20_NLD3__FUNC_CM2DAT_1X_3 (MT_PIN_NO(20) | 4) +#define MT8135_PIN_20_NLD3__FUNC_TESTA_OUT14 (MT_PIN_NO(20) | 7) + +#define MT8135_PIN_21_NLD4__FUNC_GPIO21 (MT_PIN_NO(21) | 0) +#define MT8135_PIN_21_NLD4__FUNC_NLD4 (MT_PIN_NO(21) | 1) +#define MT8135_PIN_21_NLD4__FUNC_EINT150 (MT_PIN_NO(21) | 2) +#define MT8135_PIN_21_NLD4__FUNC_A_FUNC_DIN_5 (MT_PIN_NO(21) | 3) +#define MT8135_PIN_21_NLD4__FUNC_CM2DAT_1X_4 (MT_PIN_NO(21) | 4) +#define MT8135_PIN_21_NLD4__FUNC_TESTA_OUT15 (MT_PIN_NO(21) | 7) + +#define MT8135_PIN_22_NLD5__FUNC_GPIO22 (MT_PIN_NO(22) | 0) +#define MT8135_PIN_22_NLD5__FUNC_NLD5 (MT_PIN_NO(22) | 1) +#define MT8135_PIN_22_NLD5__FUNC_EINT151 (MT_PIN_NO(22) | 2) +#define MT8135_PIN_22_NLD5__FUNC_A_FUNC_DIN_6 (MT_PIN_NO(22) | 3) +#define MT8135_PIN_22_NLD5__FUNC_CM2DAT_1X_5 (MT_PIN_NO(22) | 4) +#define MT8135_PIN_22_NLD5__FUNC_TESTA_OUT16 (MT_PIN_NO(22) | 7) + +#define MT8135_PIN_23_NLD6__FUNC_GPIO23 (MT_PIN_NO(23) | 0) +#define MT8135_PIN_23_NLD6__FUNC_NLD6 (MT_PIN_NO(23) | 1) +#define MT8135_PIN_23_NLD6__FUNC_EINT152 (MT_PIN_NO(23) | 2) +#define MT8135_PIN_23_NLD6__FUNC_A_FUNC_DIN_7 (MT_PIN_NO(23) | 3) +#define MT8135_PIN_23_NLD6__FUNC_CM2DAT_1X_6 (MT_PIN_NO(23) | 4) +#define MT8135_PIN_23_NLD6__FUNC_TESTA_OUT17 (MT_PIN_NO(23) | 7) + +#define MT8135_PIN_24_NLD7__FUNC_GPIO24 (MT_PIN_NO(24) | 0) +#define MT8135_PIN_24_NLD7__FUNC_NLD7 (MT_PIN_NO(24) | 1) +#define MT8135_PIN_24_NLD7__FUNC_EINT153 (MT_PIN_NO(24) | 2) +#define MT8135_PIN_24_NLD7__FUNC_A_FUNC_DIN_8 (MT_PIN_NO(24) | 3) +#define MT8135_PIN_24_NLD7__FUNC_CM2DAT_1X_7 (MT_PIN_NO(24) | 4) +#define MT8135_PIN_24_NLD7__FUNC_TESTA_OUT18 (MT_PIN_NO(24) | 7) + +#define MT8135_PIN_25_NLD8__FUNC_GPIO25 (MT_PIN_NO(25) | 0) +#define MT8135_PIN_25_NLD8__FUNC_NLD8 (MT_PIN_NO(25) | 1) +#define MT8135_PIN_25_NLD8__FUNC_EINT154 (MT_PIN_NO(25) | 2) +#define MT8135_PIN_25_NLD8__FUNC_CM2DAT_1X_8 (MT_PIN_NO(25) | 4) + +#define MT8135_PIN_26_NLD9__FUNC_GPIO26 (MT_PIN_NO(26) | 0) +#define MT8135_PIN_26_NLD9__FUNC_NLD9 (MT_PIN_NO(26) | 1) +#define MT8135_PIN_26_NLD9__FUNC_EINT155 (MT_PIN_NO(26) | 2) +#define MT8135_PIN_26_NLD9__FUNC_CM2DAT_1X_9 (MT_PIN_NO(26) | 4) +#define MT8135_PIN_26_NLD9__FUNC_PWM1 (MT_PIN_NO(26) | 5) + +#define MT8135_PIN_27_NLD10__FUNC_GPIO27 (MT_PIN_NO(27) | 0) +#define MT8135_PIN_27_NLD10__FUNC_NLD10 (MT_PIN_NO(27) | 1) +#define MT8135_PIN_27_NLD10__FUNC_EINT156 (MT_PIN_NO(27) | 2) +#define MT8135_PIN_27_NLD10__FUNC_CM2VSYNC_1X (MT_PIN_NO(27) | 4) +#define MT8135_PIN_27_NLD10__FUNC_PWM2 (MT_PIN_NO(27) | 5) + +#define MT8135_PIN_28_NLD11__FUNC_GPIO28 (MT_PIN_NO(28) | 0) +#define MT8135_PIN_28_NLD11__FUNC_NLD11 (MT_PIN_NO(28) | 1) +#define MT8135_PIN_28_NLD11__FUNC_EINT157 (MT_PIN_NO(28) | 2) +#define MT8135_PIN_28_NLD11__FUNC_CM2HSYNC_1X (MT_PIN_NO(28) | 4) +#define MT8135_PIN_28_NLD11__FUNC_PWM3 (MT_PIN_NO(28) | 5) + +#define MT8135_PIN_29_NLD12__FUNC_GPIO29 (MT_PIN_NO(29) | 0) +#define MT8135_PIN_29_NLD12__FUNC_NLD12 (MT_PIN_NO(29) | 1) +#define MT8135_PIN_29_NLD12__FUNC_EINT158 (MT_PIN_NO(29) | 2) +#define MT8135_PIN_29_NLD12__FUNC_I2SIN_CK (MT_PIN_NO(29) | 3) +#define MT8135_PIN_29_NLD12__FUNC_DAC_CK (MT_PIN_NO(29) | 4) +#define MT8135_PIN_29_NLD12__FUNC_PCM1_CK (MT_PIN_NO(29) | 5) + +#define MT8135_PIN_30_NLD13__FUNC_GPIO30 (MT_PIN_NO(30) | 0) +#define MT8135_PIN_30_NLD13__FUNC_NLD13 (MT_PIN_NO(30) | 1) +#define MT8135_PIN_30_NLD13__FUNC_EINT159 (MT_PIN_NO(30) | 2) +#define MT8135_PIN_30_NLD13__FUNC_I2SIN_WS (MT_PIN_NO(30) | 3) +#define MT8135_PIN_30_NLD13__FUNC_DAC_WS (MT_PIN_NO(30) | 4) +#define MT8135_PIN_30_NLD13__FUNC_PCM1_WS (MT_PIN_NO(30) | 5) + +#define MT8135_PIN_31_NLD14__FUNC_GPIO31 (MT_PIN_NO(31) | 0) +#define MT8135_PIN_31_NLD14__FUNC_NLD14 (MT_PIN_NO(31) | 1) +#define MT8135_PIN_31_NLD14__FUNC_EINT160 (MT_PIN_NO(31) | 2) +#define MT8135_PIN_31_NLD14__FUNC_I2SOUT_DAT (MT_PIN_NO(31) | 3) +#define MT8135_PIN_31_NLD14__FUNC_DAC_DAT_OUT (MT_PIN_NO(31) | 4) +#define MT8135_PIN_31_NLD14__FUNC_PCM1_DO (MT_PIN_NO(31) | 5) + +#define MT8135_PIN_32_NLD15__FUNC_GPIO32 (MT_PIN_NO(32) | 0) +#define MT8135_PIN_32_NLD15__FUNC_NLD15 (MT_PIN_NO(32) | 1) +#define MT8135_PIN_32_NLD15__FUNC_EINT161 (MT_PIN_NO(32) | 2) +#define MT8135_PIN_32_NLD15__FUNC_DISP_PWM (MT_PIN_NO(32) | 3) +#define MT8135_PIN_32_NLD15__FUNC_PWM4 (MT_PIN_NO(32) | 4) +#define MT8135_PIN_32_NLD15__FUNC_PCM1_DI (MT_PIN_NO(32) | 5) + +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_GPIO33 (MT_PIN_NO(33) | 0) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB (MT_PIN_NO(33) | 1) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_EINT50 (MT_PIN_NO(33) | 2) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_I2SIN_DAT (MT_PIN_NO(33) | 3) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_PCM1_DI (MT_PIN_NO(33) | 5) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_SPI1_MI (MT_PIN_NO(33) | 6) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_NLD10 (MT_PIN_NO(33) | 7) + +#define MT8135_PIN_34_IDDIG__FUNC_GPIO34 (MT_PIN_NO(34) | 0) +#define MT8135_PIN_34_IDDIG__FUNC_IDDIG (MT_PIN_NO(34) | 1) +#define MT8135_PIN_34_IDDIG__FUNC_EINT34 (MT_PIN_NO(34) | 2) + +#define MT8135_PIN_35_SCL3__FUNC_GPIO35 (MT_PIN_NO(35) | 0) +#define MT8135_PIN_35_SCL3__FUNC_SCL3 (MT_PIN_NO(35) | 1) +#define MT8135_PIN_35_SCL3__FUNC_EINT96 (MT_PIN_NO(35) | 2) +#define MT8135_PIN_35_SCL3__FUNC_CLKM6 (MT_PIN_NO(35) | 3) +#define MT8135_PIN_35_SCL3__FUNC_PWM6 (MT_PIN_NO(35) | 4) + +#define MT8135_PIN_36_SDA3__FUNC_GPIO36 (MT_PIN_NO(36) | 0) +#define MT8135_PIN_36_SDA3__FUNC_SDA3 (MT_PIN_NO(36) | 1) +#define MT8135_PIN_36_SDA3__FUNC_EINT97 (MT_PIN_NO(36) | 2) + +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_GPIO37 (MT_PIN_NO(37) | 0) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_AUD_CLK (MT_PIN_NO(37) | 1) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_ADC_CK (MT_PIN_NO(37) | 2) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_HDMI_SDATA0 (MT_PIN_NO(37) | 3) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_EINT19 (MT_PIN_NO(37) | 4) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_USB_TEST_IO_6 (MT_PIN_NO(37) | 5) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_TESTA_OUT19 (MT_PIN_NO(37) | 7) + +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_GPIO38 (MT_PIN_NO(38) | 0) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MT_PIN_NO(38) | 1) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_ADC_WS (MT_PIN_NO(38) | 2) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MT_PIN_NO(38) | 3) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_EINT21 (MT_PIN_NO(38) | 4) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_USB_TEST_IO_7 (MT_PIN_NO(38) | 5) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_TESTA_OUT20 (MT_PIN_NO(38) | 7) + +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_GPIO39 (MT_PIN_NO(39) | 0) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MT_PIN_NO(39) | 1) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_ADC_DAT_IN (MT_PIN_NO(39) | 2) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MT_PIN_NO(39) | 3) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_EINT20 (MT_PIN_NO(39) | 4) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_USB_TEST_IO_8 (MT_PIN_NO(39) | 5) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_TESTA_OUT21 (MT_PIN_NO(39) | 7) + +#define MT8135_PIN_40_DAC_CLK__FUNC_GPIO40 (MT_PIN_NO(40) | 0) +#define MT8135_PIN_40_DAC_CLK__FUNC_DAC_CK (MT_PIN_NO(40) | 1) +#define MT8135_PIN_40_DAC_CLK__FUNC_EINT22 (MT_PIN_NO(40) | 2) +#define MT8135_PIN_40_DAC_CLK__FUNC_HDMI_SDATA1 (MT_PIN_NO(40) | 3) +#define MT8135_PIN_40_DAC_CLK__FUNC_USB_TEST_IO_9 (MT_PIN_NO(40) | 5) +#define MT8135_PIN_40_DAC_CLK__FUNC_TESTA_OUT22 (MT_PIN_NO(40) | 7) + +#define MT8135_PIN_41_DAC_WS__FUNC_GPIO41 (MT_PIN_NO(41) | 0) +#define MT8135_PIN_41_DAC_WS__FUNC_DAC_WS (MT_PIN_NO(41) | 1) +#define MT8135_PIN_41_DAC_WS__FUNC_EINT24 (MT_PIN_NO(41) | 2) +#define MT8135_PIN_41_DAC_WS__FUNC_HDMI_SDATA2 (MT_PIN_NO(41) | 3) +#define MT8135_PIN_41_DAC_WS__FUNC_USB_TEST_IO_10 (MT_PIN_NO(41) | 5) +#define MT8135_PIN_41_DAC_WS__FUNC_TESTA_OUT23 (MT_PIN_NO(41) | 7) + +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_GPIO42 (MT_PIN_NO(42) | 0) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_DAC_DAT_OUT (MT_PIN_NO(42) | 1) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_EINT23 (MT_PIN_NO(42) | 2) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_HDMI_SDATA3 (MT_PIN_NO(42) | 3) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_USB_TEST_IO_11 (MT_PIN_NO(42) | 5) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_TESTA_OUT24 (MT_PIN_NO(42) | 7) + +#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_GPIO43 (MT_PIN_NO(43) | 0) +#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MT_PIN_NO(43) | 1) +#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_EINT29 (MT_PIN_NO(43) | 2) + +#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_GPIO44 (MT_PIN_NO(44) | 0) +#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MT_PIN_NO(44) | 1) +#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_EINT28 (MT_PIN_NO(44) | 2) + +#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_GPIO45 (MT_PIN_NO(45) | 0) +#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MT_PIN_NO(45) | 1) +#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_EINT27 (MT_PIN_NO(45) | 2) + +#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_GPIO46 (MT_PIN_NO(46) | 0) +#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_PWRAP_SPICK_I (MT_PIN_NO(46) | 1) +#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_EINT26 (MT_PIN_NO(46) | 2) + +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_GPIO47 (MT_PIN_NO(47) | 0) +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_PWRAP_EVENT_IN (MT_PIN_NO(47) | 1) +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_EINT25 (MT_PIN_NO(47) | 2) +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_TESTA_OUT2 (MT_PIN_NO(47) | 7) + +#define MT8135_PIN_48_RTC32K_CK__FUNC_GPIO48 (MT_PIN_NO(48) | 0) +#define MT8135_PIN_48_RTC32K_CK__FUNC_RTC32K_CK (MT_PIN_NO(48) | 1) + +#define MT8135_PIN_49_WATCHDOG__FUNC_GPIO49 (MT_PIN_NO(49) | 0) +#define MT8135_PIN_49_WATCHDOG__FUNC_WATCHDOG (MT_PIN_NO(49) | 1) +#define MT8135_PIN_49_WATCHDOG__FUNC_EINT36 (MT_PIN_NO(49) | 2) + +#define MT8135_PIN_50_SRCLKENA__FUNC_GPIO50 (MT_PIN_NO(50) | 0) +#define MT8135_PIN_50_SRCLKENA__FUNC_SRCLKENA (MT_PIN_NO(50) | 1) +#define MT8135_PIN_50_SRCLKENA__FUNC_EINT38 (MT_PIN_NO(50) | 2) + +#define MT8135_PIN_51_SRCVOLTEN__FUNC_GPIO51 (MT_PIN_NO(51) | 0) +#define MT8135_PIN_51_SRCVOLTEN__FUNC_SRCVOLTEN (MT_PIN_NO(51) | 1) +#define MT8135_PIN_51_SRCVOLTEN__FUNC_EINT37 (MT_PIN_NO(51) | 2) + +#define MT8135_PIN_52_EINT0__FUNC_GPIO52 (MT_PIN_NO(52) | 0) +#define MT8135_PIN_52_EINT0__FUNC_EINT0 (MT_PIN_NO(52) | 1) +#define MT8135_PIN_52_EINT0__FUNC_PWM1 (MT_PIN_NO(52) | 2) +#define MT8135_PIN_52_EINT0__FUNC_CLKM0 (MT_PIN_NO(52) | 3) +#define MT8135_PIN_52_EINT0__FUNC_SPDIF_OUT (MT_PIN_NO(52) | 4) +#define MT8135_PIN_52_EINT0__FUNC_USB_TEST_IO_12 (MT_PIN_NO(52) | 5) +#define MT8135_PIN_52_EINT0__FUNC_USB_SCL (MT_PIN_NO(52) | 7) + +#define MT8135_PIN_53_URXD2__FUNC_GPIO53 (MT_PIN_NO(53) | 0) +#define MT8135_PIN_53_URXD2__FUNC_URXD2 (MT_PIN_NO(53) | 1) +#define MT8135_PIN_53_URXD2__FUNC_EINT83 (MT_PIN_NO(53) | 2) +#define MT8135_PIN_53_URXD2__FUNC_HDMI_LRCK (MT_PIN_NO(53) | 4) +#define MT8135_PIN_53_URXD2__FUNC_CLKM3 (MT_PIN_NO(53) | 5) +#define MT8135_PIN_53_URXD2__FUNC_UTXD2 (MT_PIN_NO(53) | 7) + +#define MT8135_PIN_54_UTXD2__FUNC_GPIO54 (MT_PIN_NO(54) | 0) +#define MT8135_PIN_54_UTXD2__FUNC_UTXD2 (MT_PIN_NO(54) | 1) +#define MT8135_PIN_54_UTXD2__FUNC_EINT82 (MT_PIN_NO(54) | 2) +#define MT8135_PIN_54_UTXD2__FUNC_HDMI_BCK_OUT (MT_PIN_NO(54) | 4) +#define MT8135_PIN_54_UTXD2__FUNC_CLKM2 (MT_PIN_NO(54) | 5) +#define MT8135_PIN_54_UTXD2__FUNC_URXD2 (MT_PIN_NO(54) | 7) + +#define MT8135_PIN_55_UCTS2__FUNC_GPIO55 (MT_PIN_NO(55) | 0) +#define MT8135_PIN_55_UCTS2__FUNC_UCTS2 (MT_PIN_NO(55) | 1) +#define MT8135_PIN_55_UCTS2__FUNC_EINT84 (MT_PIN_NO(55) | 2) +#define MT8135_PIN_55_UCTS2__FUNC_PWM1 (MT_PIN_NO(55) | 5) +#define MT8135_PIN_55_UCTS2__FUNC_URTS2 (MT_PIN_NO(55) | 7) + +#define MT8135_PIN_56_URTS2__FUNC_GPIO56 (MT_PIN_NO(56) | 0) +#define MT8135_PIN_56_URTS2__FUNC_URTS2 (MT_PIN_NO(56) | 1) +#define MT8135_PIN_56_URTS2__FUNC_EINT85 (MT_PIN_NO(56) | 2) +#define MT8135_PIN_56_URTS2__FUNC_PWM2 (MT_PIN_NO(56) | 5) +#define MT8135_PIN_56_URTS2__FUNC_UCTS2 (MT_PIN_NO(56) | 7) + +#define MT8135_PIN_57_JTCK__FUNC_GPIO57 (MT_PIN_NO(57) | 0) +#define MT8135_PIN_57_JTCK__FUNC_JTCK (MT_PIN_NO(57) | 1) +#define MT8135_PIN_57_JTCK__FUNC_EINT188 (MT_PIN_NO(57) | 2) +#define MT8135_PIN_57_JTCK__FUNC_DSP1_ICK (MT_PIN_NO(57) | 3) + +#define MT8135_PIN_58_JTDO__FUNC_GPIO58 (MT_PIN_NO(58) | 0) +#define MT8135_PIN_58_JTDO__FUNC_JTDO (MT_PIN_NO(58) | 1) +#define MT8135_PIN_58_JTDO__FUNC_EINT190 (MT_PIN_NO(58) | 2) +#define MT8135_PIN_58_JTDO__FUNC_DSP2_IMS (MT_PIN_NO(58) | 3) + +#define MT8135_PIN_59_JTRST_B__FUNC_GPIO59 (MT_PIN_NO(59) | 0) +#define MT8135_PIN_59_JTRST_B__FUNC_JTRST_B (MT_PIN_NO(59) | 1) +#define MT8135_PIN_59_JTRST_B__FUNC_EINT0 (MT_PIN_NO(59) | 2) +#define MT8135_PIN_59_JTRST_B__FUNC_DSP2_ICK (MT_PIN_NO(59) | 3) + +#define MT8135_PIN_60_JTDI__FUNC_GPIO60 (MT_PIN_NO(60) | 0) +#define MT8135_PIN_60_JTDI__FUNC_JTDI (MT_PIN_NO(60) | 1) +#define MT8135_PIN_60_JTDI__FUNC_EINT189 (MT_PIN_NO(60) | 2) +#define MT8135_PIN_60_JTDI__FUNC_DSP1_IMS (MT_PIN_NO(60) | 3) + +#define MT8135_PIN_61_JRTCK__FUNC_GPIO61 (MT_PIN_NO(61) | 0) +#define MT8135_PIN_61_JRTCK__FUNC_JRTCK (MT_PIN_NO(61) | 1) +#define MT8135_PIN_61_JRTCK__FUNC_EINT187 (MT_PIN_NO(61) | 2) +#define MT8135_PIN_61_JRTCK__FUNC_DSP1_ID (MT_PIN_NO(61) | 3) + +#define MT8135_PIN_62_JTMS__FUNC_GPIO62 (MT_PIN_NO(62) | 0) +#define MT8135_PIN_62_JTMS__FUNC_JTMS (MT_PIN_NO(62) | 1) +#define MT8135_PIN_62_JTMS__FUNC_EINT191 (MT_PIN_NO(62) | 2) +#define MT8135_PIN_62_JTMS__FUNC_DSP2_ID (MT_PIN_NO(62) | 3) + +#define MT8135_PIN_63_MSDC1_INSI__FUNC_GPIO63 (MT_PIN_NO(63) | 0) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_MSDC1_INSI (MT_PIN_NO(63) | 1) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_EINT57 (MT_PIN_NO(63) | 2) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_SCL5 (MT_PIN_NO(63) | 3) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_PWM6 (MT_PIN_NO(63) | 4) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_CLKM5 (MT_PIN_NO(63) | 5) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_TESTB_OUT6 (MT_PIN_NO(63) | 7) + +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_GPIO64 (MT_PIN_NO(64) | 0) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_MSDC1_SDWPI (MT_PIN_NO(64) | 1) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_EINT58 (MT_PIN_NO(64) | 2) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_SDA5 (MT_PIN_NO(64) | 3) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_PWM7 (MT_PIN_NO(64) | 4) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_CLKM6 (MT_PIN_NO(64) | 5) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_TESTB_OUT7 (MT_PIN_NO(64) | 7) + +#define MT8135_PIN_65_MSDC2_INSI__FUNC_GPIO65 (MT_PIN_NO(65) | 0) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_MSDC2_INSI (MT_PIN_NO(65) | 1) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_EINT65 (MT_PIN_NO(65) | 2) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_USB_TEST_IO_27 (MT_PIN_NO(65) | 5) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_TESTA_OUT3 (MT_PIN_NO(65) | 7) + +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_GPIO66 (MT_PIN_NO(66) | 0) +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_MSDC2_SDWPI (MT_PIN_NO(66) | 1) +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_EINT66 (MT_PIN_NO(66) | 2) +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_USB_TEST_IO_28 (MT_PIN_NO(66) | 5) + +#define MT8135_PIN_67_URXD4__FUNC_GPIO67 (MT_PIN_NO(67) | 0) +#define MT8135_PIN_67_URXD4__FUNC_URXD4 (MT_PIN_NO(67) | 1) +#define MT8135_PIN_67_URXD4__FUNC_EINT89 (MT_PIN_NO(67) | 2) +#define MT8135_PIN_67_URXD4__FUNC_URXD1 (MT_PIN_NO(67) | 3) +#define MT8135_PIN_67_URXD4__FUNC_UTXD4 (MT_PIN_NO(67) | 6) +#define MT8135_PIN_67_URXD4__FUNC_TESTB_OUT10 (MT_PIN_NO(67) | 7) + +#define MT8135_PIN_68_UTXD4__FUNC_GPIO68 (MT_PIN_NO(68) | 0) +#define MT8135_PIN_68_UTXD4__FUNC_UTXD4 (MT_PIN_NO(68) | 1) +#define MT8135_PIN_68_UTXD4__FUNC_EINT88 (MT_PIN_NO(68) | 2) +#define MT8135_PIN_68_UTXD4__FUNC_UTXD1 (MT_PIN_NO(68) | 3) +#define MT8135_PIN_68_UTXD4__FUNC_URXD4 (MT_PIN_NO(68) | 6) +#define MT8135_PIN_68_UTXD4__FUNC_TESTB_OUT11 (MT_PIN_NO(68) | 7) + +#define MT8135_PIN_69_URXD1__FUNC_GPIO69 (MT_PIN_NO(69) | 0) +#define MT8135_PIN_69_URXD1__FUNC_URXD1 (MT_PIN_NO(69) | 1) +#define MT8135_PIN_69_URXD1__FUNC_EINT79 (MT_PIN_NO(69) | 2) +#define MT8135_PIN_69_URXD1__FUNC_URXD4 (MT_PIN_NO(69) | 3) +#define MT8135_PIN_69_URXD1__FUNC_UTXD1 (MT_PIN_NO(69) | 6) +#define MT8135_PIN_69_URXD1__FUNC_TESTB_OUT24 (MT_PIN_NO(69) | 7) + +#define MT8135_PIN_70_UTXD1__FUNC_GPIO70 (MT_PIN_NO(70) | 0) +#define MT8135_PIN_70_UTXD1__FUNC_UTXD1 (MT_PIN_NO(70) | 1) +#define MT8135_PIN_70_UTXD1__FUNC_EINT78 (MT_PIN_NO(70) | 2) +#define MT8135_PIN_70_UTXD1__FUNC_UTXD4 (MT_PIN_NO(70) | 3) +#define MT8135_PIN_70_UTXD1__FUNC_URXD1 (MT_PIN_NO(70) | 6) +#define MT8135_PIN_70_UTXD1__FUNC_TESTB_OUT25 (MT_PIN_NO(70) | 7) + +#define MT8135_PIN_71_UCTS1__FUNC_GPIO71 (MT_PIN_NO(71) | 0) +#define MT8135_PIN_71_UCTS1__FUNC_UCTS1 (MT_PIN_NO(71) | 1) +#define MT8135_PIN_71_UCTS1__FUNC_EINT80 (MT_PIN_NO(71) | 2) +#define MT8135_PIN_71_UCTS1__FUNC_CLKM0 (MT_PIN_NO(71) | 5) +#define MT8135_PIN_71_UCTS1__FUNC_URTS1 (MT_PIN_NO(71) | 6) +#define MT8135_PIN_71_UCTS1__FUNC_TESTB_OUT31 (MT_PIN_NO(71) | 7) + +#define MT8135_PIN_72_URTS1__FUNC_GPIO72 (MT_PIN_NO(72) | 0) +#define MT8135_PIN_72_URTS1__FUNC_URTS1 (MT_PIN_NO(72) | 1) +#define MT8135_PIN_72_URTS1__FUNC_EINT81 (MT_PIN_NO(72) | 2) +#define MT8135_PIN_72_URTS1__FUNC_CLKM1 (MT_PIN_NO(72) | 5) +#define MT8135_PIN_72_URTS1__FUNC_UCTS1 (MT_PIN_NO(72) | 6) +#define MT8135_PIN_72_URTS1__FUNC_TESTB_OUT21 (MT_PIN_NO(72) | 7) + +#define MT8135_PIN_73_PWM1__FUNC_GPIO73 (MT_PIN_NO(73) | 0) +#define MT8135_PIN_73_PWM1__FUNC_PWM1 (MT_PIN_NO(73) | 1) +#define MT8135_PIN_73_PWM1__FUNC_EINT73 (MT_PIN_NO(73) | 2) +#define MT8135_PIN_73_PWM1__FUNC_USB_DRVVBUS (MT_PIN_NO(73) | 5) +#define MT8135_PIN_73_PWM1__FUNC_DISP_PWM (MT_PIN_NO(73) | 6) +#define MT8135_PIN_73_PWM1__FUNC_TESTB_OUT8 (MT_PIN_NO(73) | 7) + +#define MT8135_PIN_74_PWM2__FUNC_GPIO74 (MT_PIN_NO(74) | 0) +#define MT8135_PIN_74_PWM2__FUNC_PWM2 (MT_PIN_NO(74) | 1) +#define MT8135_PIN_74_PWM2__FUNC_EINT74 (MT_PIN_NO(74) | 2) +#define MT8135_PIN_74_PWM2__FUNC_DPI33_CK (MT_PIN_NO(74) | 3) +#define MT8135_PIN_74_PWM2__FUNC_PWM5 (MT_PIN_NO(74) | 4) +#define MT8135_PIN_74_PWM2__FUNC_URXD2 (MT_PIN_NO(74) | 5) +#define MT8135_PIN_74_PWM2__FUNC_DISP_PWM (MT_PIN_NO(74) | 6) +#define MT8135_PIN_74_PWM2__FUNC_TESTB_OUT9 (MT_PIN_NO(74) | 7) + +#define MT8135_PIN_75_PWM3__FUNC_GPIO75 (MT_PIN_NO(75) | 0) +#define MT8135_PIN_75_PWM3__FUNC_PWM3 (MT_PIN_NO(75) | 1) +#define MT8135_PIN_75_PWM3__FUNC_EINT75 (MT_PIN_NO(75) | 2) +#define MT8135_PIN_75_PWM3__FUNC_DPI33_D0 (MT_PIN_NO(75) | 3) +#define MT8135_PIN_75_PWM3__FUNC_PWM6 (MT_PIN_NO(75) | 4) +#define MT8135_PIN_75_PWM3__FUNC_UTXD2 (MT_PIN_NO(75) | 5) +#define MT8135_PIN_75_PWM3__FUNC_DISP_PWM (MT_PIN_NO(75) | 6) +#define MT8135_PIN_75_PWM3__FUNC_TESTB_OUT12 (MT_PIN_NO(75) | 7) + +#define MT8135_PIN_76_PWM4__FUNC_GPIO76 (MT_PIN_NO(76) | 0) +#define MT8135_PIN_76_PWM4__FUNC_PWM4 (MT_PIN_NO(76) | 1) +#define MT8135_PIN_76_PWM4__FUNC_EINT76 (MT_PIN_NO(76) | 2) +#define MT8135_PIN_76_PWM4__FUNC_DPI33_D1 (MT_PIN_NO(76) | 3) +#define MT8135_PIN_76_PWM4__FUNC_PWM7 (MT_PIN_NO(76) | 4) +#define MT8135_PIN_76_PWM4__FUNC_DISP_PWM (MT_PIN_NO(76) | 6) +#define MT8135_PIN_76_PWM4__FUNC_TESTB_OUT13 (MT_PIN_NO(76) | 7) + +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_GPIO77 (MT_PIN_NO(77) | 0) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MT_PIN_NO(77) | 1) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_EINT63 (MT_PIN_NO(77) | 2) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DSP2_IMS (MT_PIN_NO(77) | 4) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DPI33_D6 (MT_PIN_NO(77) | 6) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_TESTA_OUT25 (MT_PIN_NO(77) | 7) + +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_GPIO78 (MT_PIN_NO(78) | 0) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MT_PIN_NO(78) | 1) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_EINT64 (MT_PIN_NO(78) | 2) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DSP2_ID (MT_PIN_NO(78) | 4) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DPI33_D7 (MT_PIN_NO(78) | 6) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_TESTA_OUT26 (MT_PIN_NO(78) | 7) + +#define MT8135_PIN_79_MSDC2_CMD__FUNC_GPIO79 (MT_PIN_NO(79) | 0) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD (MT_PIN_NO(79) | 1) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_EINT60 (MT_PIN_NO(79) | 2) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_DSP1_IMS (MT_PIN_NO(79) | 4) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_PCM1_WS (MT_PIN_NO(79) | 5) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_DPI33_D3 (MT_PIN_NO(79) | 6) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_TESTA_OUT0 (MT_PIN_NO(79) | 7) + +#define MT8135_PIN_80_MSDC2_CLK__FUNC_GPIO80 (MT_PIN_NO(80) | 0) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK (MT_PIN_NO(80) | 1) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_EINT59 (MT_PIN_NO(80) | 2) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_DSP1_ICK (MT_PIN_NO(80) | 4) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_PCM1_CK (MT_PIN_NO(80) | 5) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_DPI33_D2 (MT_PIN_NO(80) | 6) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_TESTA_OUT1 (MT_PIN_NO(80) | 7) + +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_GPIO81 (MT_PIN_NO(81) | 0) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MT_PIN_NO(81) | 1) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_EINT62 (MT_PIN_NO(81) | 2) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DSP2_ICK (MT_PIN_NO(81) | 4) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_PCM1_DO (MT_PIN_NO(81) | 5) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DPI33_D5 (MT_PIN_NO(81) | 6) + +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MT_PIN_NO(82) | 0) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MT_PIN_NO(82) | 1) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_EINT61 (MT_PIN_NO(82) | 2) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DSP1_ID (MT_PIN_NO(82) | 4) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_PCM1_DI (MT_PIN_NO(82) | 5) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DPI33_D4 (MT_PIN_NO(82) | 6) + +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_GPIO83 (MT_PIN_NO(83) | 0) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MT_PIN_NO(83) | 1) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_EINT53 (MT_PIN_NO(83) | 2) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_SCL1 (MT_PIN_NO(83) | 3) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_PWM2 (MT_PIN_NO(83) | 4) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_CLKM1 (MT_PIN_NO(83) | 5) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_TESTB_OUT2 (MT_PIN_NO(83) | 7) + +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_GPIO84 (MT_PIN_NO(84) | 0) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MT_PIN_NO(84) | 1) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_EINT54 (MT_PIN_NO(84) | 2) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_SDA1 (MT_PIN_NO(84) | 3) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_PWM3 (MT_PIN_NO(84) | 4) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_CLKM2 (MT_PIN_NO(84) | 5) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_TESTB_OUT3 (MT_PIN_NO(84) | 7) + +#define MT8135_PIN_85_MSDC1_CMD__FUNC_GPIO85 (MT_PIN_NO(85) | 0) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD (MT_PIN_NO(85) | 1) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_EINT52 (MT_PIN_NO(85) | 2) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_SDA0 (MT_PIN_NO(85) | 3) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_PWM1 (MT_PIN_NO(85) | 4) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_CLKM0 (MT_PIN_NO(85) | 5) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_TESTB_OUT1 (MT_PIN_NO(85) | 7) + +#define MT8135_PIN_86_MSDC1_CLK__FUNC_GPIO86 (MT_PIN_NO(86) | 0) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK (MT_PIN_NO(86) | 1) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_EINT51 (MT_PIN_NO(86) | 2) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_SCL0 (MT_PIN_NO(86) | 3) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_DISP_PWM (MT_PIN_NO(86) | 4) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_TESTB_OUT0 (MT_PIN_NO(86) | 7) + +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_GPIO87 (MT_PIN_NO(87) | 0) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MT_PIN_NO(87) | 1) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_EINT55 (MT_PIN_NO(87) | 2) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_SCL4 (MT_PIN_NO(87) | 3) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_PWM4 (MT_PIN_NO(87) | 4) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_CLKM3 (MT_PIN_NO(87) | 5) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_TESTB_OUT4 (MT_PIN_NO(87) | 7) + +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_GPIO88 (MT_PIN_NO(88) | 0) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MT_PIN_NO(88) | 1) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_EINT56 (MT_PIN_NO(88) | 2) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_SDA4 (MT_PIN_NO(88) | 3) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_PWM5 (MT_PIN_NO(88) | 4) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_CLKM4 (MT_PIN_NO(88) | 5) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_TESTB_OUT5 (MT_PIN_NO(88) | 7) + +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_GPIO89 (MT_PIN_NO(89) | 0) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_MSDC4_DAT0 (MT_PIN_NO(89) | 1) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EINT133 (MT_PIN_NO(89) | 2) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EXT_FRAME_SYNC (MT_PIN_NO(89) | 4) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_USB_DRVVBUS (MT_PIN_NO(89) | 5) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_A_FUNC_DIN_9 (MT_PIN_NO(89) | 6) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_LPTE (MT_PIN_NO(89) | 7) + +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_GPIO90 (MT_PIN_NO(90) | 0) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_MSDC4_DAT1 (MT_PIN_NO(90) | 1) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_EINT134 (MT_PIN_NO(90) | 2) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_A_FUNC_DIN_10 (MT_PIN_NO(90) | 6) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_LRSTB_1X (MT_PIN_NO(90) | 7) + +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_GPIO91 (MT_PIN_NO(91) | 0) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_MSDC4_DAT5 (MT_PIN_NO(91) | 1) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_EINT136 (MT_PIN_NO(91) | 2) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_I2SIN_WS (MT_PIN_NO(91) | 3) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_DAC_WS (MT_PIN_NO(91) | 4) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_PCM1_WS (MT_PIN_NO(91) | 5) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_A_FUNC_DIN_11 (MT_PIN_NO(91) | 6) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_SPI1_CSN (MT_PIN_NO(91) | 7) + +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_GPIO92 (MT_PIN_NO(92) | 0) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_MSDC4_DAT6 (MT_PIN_NO(92) | 1) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_EINT137 (MT_PIN_NO(92) | 2) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_I2SOUT_DAT (MT_PIN_NO(92) | 3) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_DAC_DAT_OUT (MT_PIN_NO(92) | 4) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_PCM1_DO (MT_PIN_NO(92) | 5) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_A_FUNC_DIN_12 (MT_PIN_NO(92) | 6) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_SPI1_MO (MT_PIN_NO(92) | 7) + +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_GPIO93 (MT_PIN_NO(93) | 0) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_MSDC4_DAT7 (MT_PIN_NO(93) | 1) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_EINT138 (MT_PIN_NO(93) | 2) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_I2SIN_DAT (MT_PIN_NO(93) | 3) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_PCM1_DI (MT_PIN_NO(93) | 5) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_A_FUNC_DIN_13 (MT_PIN_NO(93) | 6) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_SPI1_MI (MT_PIN_NO(93) | 7) + +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_GPIO94 (MT_PIN_NO(94) | 0) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_MSDC4_DAT4 (MT_PIN_NO(94) | 1) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_EINT135 (MT_PIN_NO(94) | 2) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_I2SIN_CK (MT_PIN_NO(94) | 3) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_DAC_CK (MT_PIN_NO(94) | 4) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_PCM1_CK (MT_PIN_NO(94) | 5) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_A_FUNC_DIN_14 (MT_PIN_NO(94) | 6) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_SPI1_CLK (MT_PIN_NO(94) | 7) + +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_GPIO95 (MT_PIN_NO(95) | 0) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_MSDC4_DAT2 (MT_PIN_NO(95) | 1) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_EINT131 (MT_PIN_NO(95) | 2) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_I2SIN_WS (MT_PIN_NO(95) | 3) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_CM2PDN_2X (MT_PIN_NO(95) | 4) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_DAC_WS (MT_PIN_NO(95) | 5) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_PCM1_WS (MT_PIN_NO(95) | 6) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_LSCE0B_1X (MT_PIN_NO(95) | 7) + +#define MT8135_PIN_96_MSDC4_CLK__FUNC_GPIO96 (MT_PIN_NO(96) | 0) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_MSDC4_CLK (MT_PIN_NO(96) | 1) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_EINT129 (MT_PIN_NO(96) | 2) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_DPI1_CK_2X (MT_PIN_NO(96) | 3) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_CM2PCLK_2X (MT_PIN_NO(96) | 4) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_PWM4 (MT_PIN_NO(96) | 5) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_PCM1_DI (MT_PIN_NO(96) | 6) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_LSCK_1X (MT_PIN_NO(96) | 7) + +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_GPIO97 (MT_PIN_NO(97) | 0) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_MSDC4_DAT3 (MT_PIN_NO(97) | 1) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_EINT132 (MT_PIN_NO(97) | 2) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_I2SOUT_DAT (MT_PIN_NO(97) | 3) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_CM2RST_2X (MT_PIN_NO(97) | 4) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_DAC_DAT_OUT (MT_PIN_NO(97) | 5) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_PCM1_DO (MT_PIN_NO(97) | 6) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_LSCE1B_1X (MT_PIN_NO(97) | 7) + +#define MT8135_PIN_98_MSDC4_CMD__FUNC_GPIO98 (MT_PIN_NO(98) | 0) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_MSDC4_CMD (MT_PIN_NO(98) | 1) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_EINT128 (MT_PIN_NO(98) | 2) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_DPI1_DE_2X (MT_PIN_NO(98) | 3) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_PWM3 (MT_PIN_NO(98) | 5) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_LSDA_1X (MT_PIN_NO(98) | 7) + +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_GPIO99 (MT_PIN_NO(99) | 0) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_MSDC4_RSTB (MT_PIN_NO(99) | 1) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_EINT130 (MT_PIN_NO(99) | 2) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_I2SIN_CK (MT_PIN_NO(99) | 3) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_CM2MCLK_2X (MT_PIN_NO(99) | 4) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_DAC_CK (MT_PIN_NO(99) | 5) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_PCM1_CK (MT_PIN_NO(99) | 6) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_LSA0_1X (MT_PIN_NO(99) | 7) + +#define MT8135_PIN_100_SDA0__FUNC_GPIO100 (MT_PIN_NO(100) | 0) +#define MT8135_PIN_100_SDA0__FUNC_SDA0 (MT_PIN_NO(100) | 1) +#define MT8135_PIN_100_SDA0__FUNC_EINT91 (MT_PIN_NO(100) | 2) +#define MT8135_PIN_100_SDA0__FUNC_CLKM1 (MT_PIN_NO(100) | 3) +#define MT8135_PIN_100_SDA0__FUNC_PWM1 (MT_PIN_NO(100) | 4) +#define MT8135_PIN_100_SDA0__FUNC_A_FUNC_DIN_15 (MT_PIN_NO(100) | 7) + +#define MT8135_PIN_101_SCL0__FUNC_GPIO101 (MT_PIN_NO(101) | 0) +#define MT8135_PIN_101_SCL0__FUNC_SCL0 (MT_PIN_NO(101) | 1) +#define MT8135_PIN_101_SCL0__FUNC_EINT90 (MT_PIN_NO(101) | 2) +#define MT8135_PIN_101_SCL0__FUNC_CLKM0 (MT_PIN_NO(101) | 3) +#define MT8135_PIN_101_SCL0__FUNC_DISP_PWM (MT_PIN_NO(101) | 4) +#define MT8135_PIN_101_SCL0__FUNC_A_FUNC_DIN_16 (MT_PIN_NO(101) | 7) + +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_GPIO102 (MT_PIN_NO(102) | 0) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_EINT10 (MT_PIN_NO(102) | 1) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_USB_TEST_IO_16 (MT_PIN_NO(102) | 5) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_TESTB_OUT16 (MT_PIN_NO(102) | 6) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_A_FUNC_DIN_17 (MT_PIN_NO(102) | 7) + +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_GPIO103 (MT_PIN_NO(103) | 0) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_EINT11 (MT_PIN_NO(103) | 1) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_USB_TEST_IO_17 (MT_PIN_NO(103) | 5) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_TESTB_OUT17 (MT_PIN_NO(103) | 6) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_A_FUNC_DIN_18 (MT_PIN_NO(103) | 7) + +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_GPIO104 (MT_PIN_NO(104) | 0) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_EINT16 (MT_PIN_NO(104) | 1) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_USB_TEST_IO_18 (MT_PIN_NO(104) | 5) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_TESTB_OUT18 (MT_PIN_NO(104) | 6) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_A_FUNC_DIN_19 (MT_PIN_NO(104) | 7) + +#define MT8135_PIN_105_I2S_CLK__FUNC_GPIO105 (MT_PIN_NO(105) | 0) +#define MT8135_PIN_105_I2S_CLK__FUNC_I2SIN_CK (MT_PIN_NO(105) | 1) +#define MT8135_PIN_105_I2S_CLK__FUNC_EINT10 (MT_PIN_NO(105) | 2) +#define MT8135_PIN_105_I2S_CLK__FUNC_DAC_CK (MT_PIN_NO(105) | 3) +#define MT8135_PIN_105_I2S_CLK__FUNC_PCM1_CK (MT_PIN_NO(105) | 4) +#define MT8135_PIN_105_I2S_CLK__FUNC_USB_TEST_IO_19 (MT_PIN_NO(105) | 5) +#define MT8135_PIN_105_I2S_CLK__FUNC_TESTB_OUT19 (MT_PIN_NO(105) | 6) +#define MT8135_PIN_105_I2S_CLK__FUNC_A_FUNC_DIN_20 (MT_PIN_NO(105) | 7) + +#define MT8135_PIN_106_I2S_WS__FUNC_GPIO106 (MT_PIN_NO(106) | 0) +#define MT8135_PIN_106_I2S_WS__FUNC_I2SIN_WS (MT_PIN_NO(106) | 1) +#define MT8135_PIN_106_I2S_WS__FUNC_EINT13 (MT_PIN_NO(106) | 2) +#define MT8135_PIN_106_I2S_WS__FUNC_DAC_WS (MT_PIN_NO(106) | 3) +#define MT8135_PIN_106_I2S_WS__FUNC_PCM1_WS (MT_PIN_NO(106) | 4) +#define MT8135_PIN_106_I2S_WS__FUNC_USB_TEST_IO_20 (MT_PIN_NO(106) | 5) +#define MT8135_PIN_106_I2S_WS__FUNC_TESTB_OUT20 (MT_PIN_NO(106) | 6) +#define MT8135_PIN_106_I2S_WS__FUNC_A_FUNC_DIN_21 (MT_PIN_NO(106) | 7) + +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_GPIO107 (MT_PIN_NO(107) | 0) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_I2SIN_DAT (MT_PIN_NO(107) | 1) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_EINT11 (MT_PIN_NO(107) | 2) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_PCM1_DI (MT_PIN_NO(107) | 4) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_USB_TEST_IO_21 (MT_PIN_NO(107) | 5) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_TESTB_OUT22 (MT_PIN_NO(107) | 6) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_A_FUNC_DIN_22 (MT_PIN_NO(107) | 7) + +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_GPIO108 (MT_PIN_NO(108) | 0) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_I2SOUT_DAT (MT_PIN_NO(108) | 1) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_EINT12 (MT_PIN_NO(108) | 2) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_DAC_DAT_OUT (MT_PIN_NO(108) | 3) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_PCM1_DO (MT_PIN_NO(108) | 4) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_USB_TEST_IO_22 (MT_PIN_NO(108) | 5) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_TESTB_OUT23 (MT_PIN_NO(108) | 6) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_A_FUNC_DIN_23 (MT_PIN_NO(108) | 7) + +#define MT8135_PIN_109_EINT5__FUNC_GPIO109 (MT_PIN_NO(109) | 0) +#define MT8135_PIN_109_EINT5__FUNC_EINT5 (MT_PIN_NO(109) | 1) +#define MT8135_PIN_109_EINT5__FUNC_PWM5 (MT_PIN_NO(109) | 2) +#define MT8135_PIN_109_EINT5__FUNC_CLKM3 (MT_PIN_NO(109) | 3) +#define MT8135_PIN_109_EINT5__FUNC_GPU_JTRSTB (MT_PIN_NO(109) | 4) +#define MT8135_PIN_109_EINT5__FUNC_USB_TEST_IO_23 (MT_PIN_NO(109) | 5) +#define MT8135_PIN_109_EINT5__FUNC_TESTB_OUT26 (MT_PIN_NO(109) | 6) +#define MT8135_PIN_109_EINT5__FUNC_A_FUNC_DIN_24 (MT_PIN_NO(109) | 7) + +#define MT8135_PIN_110_EINT6__FUNC_GPIO110 (MT_PIN_NO(110) | 0) +#define MT8135_PIN_110_EINT6__FUNC_EINT6 (MT_PIN_NO(110) | 1) +#define MT8135_PIN_110_EINT6__FUNC_PWM6 (MT_PIN_NO(110) | 2) +#define MT8135_PIN_110_EINT6__FUNC_CLKM4 (MT_PIN_NO(110) | 3) +#define MT8135_PIN_110_EINT6__FUNC_GPU_JTMS (MT_PIN_NO(110) | 4) +#define MT8135_PIN_110_EINT6__FUNC_USB_TEST_IO_24 (MT_PIN_NO(110) | 5) +#define MT8135_PIN_110_EINT6__FUNC_TESTB_OUT27 (MT_PIN_NO(110) | 6) +#define MT8135_PIN_110_EINT6__FUNC_A_FUNC_DIN_25 (MT_PIN_NO(110) | 7) + +#define MT8135_PIN_111_EINT7__FUNC_GPIO111 (MT_PIN_NO(111) | 0) +#define MT8135_PIN_111_EINT7__FUNC_EINT7 (MT_PIN_NO(111) | 1) +#define MT8135_PIN_111_EINT7__FUNC_PWM7 (MT_PIN_NO(111) | 2) +#define MT8135_PIN_111_EINT7__FUNC_CLKM5 (MT_PIN_NO(111) | 3) +#define MT8135_PIN_111_EINT7__FUNC_GPU_JTDO (MT_PIN_NO(111) | 4) +#define MT8135_PIN_111_EINT7__FUNC_USB_TEST_IO_25 (MT_PIN_NO(111) | 5) +#define MT8135_PIN_111_EINT7__FUNC_TESTB_OUT28 (MT_PIN_NO(111) | 6) +#define MT8135_PIN_111_EINT7__FUNC_A_FUNC_DIN_26 (MT_PIN_NO(111) | 7) + +#define MT8135_PIN_112_EINT8__FUNC_GPIO112 (MT_PIN_NO(112) | 0) +#define MT8135_PIN_112_EINT8__FUNC_EINT8 (MT_PIN_NO(112) | 1) +#define MT8135_PIN_112_EINT8__FUNC_DISP_PWM (MT_PIN_NO(112) | 2) +#define MT8135_PIN_112_EINT8__FUNC_CLKM6 (MT_PIN_NO(112) | 3) +#define MT8135_PIN_112_EINT8__FUNC_GPU_JTDI (MT_PIN_NO(112) | 4) +#define MT8135_PIN_112_EINT8__FUNC_USB_TEST_IO_26 (MT_PIN_NO(112) | 5) +#define MT8135_PIN_112_EINT8__FUNC_TESTB_OUT29 (MT_PIN_NO(112) | 6) +#define MT8135_PIN_112_EINT8__FUNC_EXT_FRAME_SYNC (MT_PIN_NO(112) | 7) + +#define MT8135_PIN_113_EINT9__FUNC_GPIO113 (MT_PIN_NO(113) | 0) +#define MT8135_PIN_113_EINT9__FUNC_EINT9 (MT_PIN_NO(113) | 1) +#define MT8135_PIN_113_EINT9__FUNC_GPU_JTCK (MT_PIN_NO(113) | 4) +#define MT8135_PIN_113_EINT9__FUNC_USB_DRVVBUS (MT_PIN_NO(113) | 5) +#define MT8135_PIN_113_EINT9__FUNC_TESTB_OUT30 (MT_PIN_NO(113) | 6) +#define MT8135_PIN_113_EINT9__FUNC_A_FUNC_DIN_27 (MT_PIN_NO(113) | 7) + +#define MT8135_PIN_114_LPCE1B__FUNC_GPIO114 (MT_PIN_NO(114) | 0) +#define MT8135_PIN_114_LPCE1B__FUNC_LPCE1B (MT_PIN_NO(114) | 1) +#define MT8135_PIN_114_LPCE1B__FUNC_EINT127 (MT_PIN_NO(114) | 2) +#define MT8135_PIN_114_LPCE1B__FUNC_PWM2 (MT_PIN_NO(114) | 5) +#define MT8135_PIN_114_LPCE1B__FUNC_TESTB_OUT14 (MT_PIN_NO(114) | 6) +#define MT8135_PIN_114_LPCE1B__FUNC_A_FUNC_DIN_28 (MT_PIN_NO(114) | 7) + +#define MT8135_PIN_115_LPCE0B__FUNC_GPIO115 (MT_PIN_NO(115) | 0) +#define MT8135_PIN_115_LPCE0B__FUNC_LPCE0B (MT_PIN_NO(115) | 1) +#define MT8135_PIN_115_LPCE0B__FUNC_EINT126 (MT_PIN_NO(115) | 2) +#define MT8135_PIN_115_LPCE0B__FUNC_PWM1 (MT_PIN_NO(115) | 5) +#define MT8135_PIN_115_LPCE0B__FUNC_TESTB_OUT15 (MT_PIN_NO(115) | 6) +#define MT8135_PIN_115_LPCE0B__FUNC_A_FUNC_DIN_29 (MT_PIN_NO(115) | 7) + +#define MT8135_PIN_116_DISP_PWM__FUNC_GPIO116 (MT_PIN_NO(116) | 0) +#define MT8135_PIN_116_DISP_PWM__FUNC_DISP_PWM (MT_PIN_NO(116) | 1) +#define MT8135_PIN_116_DISP_PWM__FUNC_EINT77 (MT_PIN_NO(116) | 2) +#define MT8135_PIN_116_DISP_PWM__FUNC_LSDI (MT_PIN_NO(116) | 3) +#define MT8135_PIN_116_DISP_PWM__FUNC_PWM1 (MT_PIN_NO(116) | 4) +#define MT8135_PIN_116_DISP_PWM__FUNC_PWM2 (MT_PIN_NO(116) | 5) +#define MT8135_PIN_116_DISP_PWM__FUNC_PWM3 (MT_PIN_NO(116) | 7) + +#define MT8135_PIN_117_EINT1__FUNC_GPIO117 (MT_PIN_NO(117) | 0) +#define MT8135_PIN_117_EINT1__FUNC_EINT1 (MT_PIN_NO(117) | 1) +#define MT8135_PIN_117_EINT1__FUNC_PWM2 (MT_PIN_NO(117) | 2) +#define MT8135_PIN_117_EINT1__FUNC_CLKM1 (MT_PIN_NO(117) | 3) +#define MT8135_PIN_117_EINT1__FUNC_USB_TEST_IO_13 (MT_PIN_NO(117) | 5) +#define MT8135_PIN_117_EINT1__FUNC_USB_SDA (MT_PIN_NO(117) | 7) + +#define MT8135_PIN_118_EINT2__FUNC_GPIO118 (MT_PIN_NO(118) | 0) +#define MT8135_PIN_118_EINT2__FUNC_EINT2 (MT_PIN_NO(118) | 1) +#define MT8135_PIN_118_EINT2__FUNC_PWM3 (MT_PIN_NO(118) | 2) +#define MT8135_PIN_118_EINT2__FUNC_CLKM2 (MT_PIN_NO(118) | 3) +#define MT8135_PIN_118_EINT2__FUNC_USB_TEST_IO_14 (MT_PIN_NO(118) | 5) +#define MT8135_PIN_118_EINT2__FUNC_SRCLKENAI2 (MT_PIN_NO(118) | 6) +#define MT8135_PIN_118_EINT2__FUNC_A_FUNC_DIN_30 (MT_PIN_NO(118) | 7) + +#define MT8135_PIN_119_EINT3__FUNC_GPIO119 (MT_PIN_NO(119) | 0) +#define MT8135_PIN_119_EINT3__FUNC_EINT3 (MT_PIN_NO(119) | 1) +#define MT8135_PIN_119_EINT3__FUNC_USB_TEST_IO_15 (MT_PIN_NO(119) | 5) +#define MT8135_PIN_119_EINT3__FUNC_SRCLKENAI1 (MT_PIN_NO(119) | 6) +#define MT8135_PIN_119_EINT3__FUNC_EXT_26M_CK (MT_PIN_NO(119) | 7) + +#define MT8135_PIN_120_EINT4__FUNC_GPIO120 (MT_PIN_NO(120) | 0) +#define MT8135_PIN_120_EINT4__FUNC_EINT4 (MT_PIN_NO(120) | 1) +#define MT8135_PIN_120_EINT4__FUNC_PWM4 (MT_PIN_NO(120) | 2) +#define MT8135_PIN_120_EINT4__FUNC_USB_DRVVBUS (MT_PIN_NO(120) | 5) +#define MT8135_PIN_120_EINT4__FUNC_A_FUNC_DIN_31 (MT_PIN_NO(120) | 7) + +#define MT8135_PIN_121_DPIDE__FUNC_GPIO121 (MT_PIN_NO(121) | 0) +#define MT8135_PIN_121_DPIDE__FUNC_DPI0_DE (MT_PIN_NO(121) | 1) +#define MT8135_PIN_121_DPIDE__FUNC_EINT100 (MT_PIN_NO(121) | 2) +#define MT8135_PIN_121_DPIDE__FUNC_I2SOUT_DAT (MT_PIN_NO(121) | 3) +#define MT8135_PIN_121_DPIDE__FUNC_DAC_DAT_OUT (MT_PIN_NO(121) | 4) +#define MT8135_PIN_121_DPIDE__FUNC_PCM1_DO (MT_PIN_NO(121) | 5) +#define MT8135_PIN_121_DPIDE__FUNC_IRDA_TXD (MT_PIN_NO(121) | 6) + +#define MT8135_PIN_122_DPICK__FUNC_GPIO122 (MT_PIN_NO(122) | 0) +#define MT8135_PIN_122_DPICK__FUNC_DPI0_CK (MT_PIN_NO(122) | 1) +#define MT8135_PIN_122_DPICK__FUNC_EINT101 (MT_PIN_NO(122) | 2) +#define MT8135_PIN_122_DPICK__FUNC_I2SIN_DAT (MT_PIN_NO(122) | 3) +#define MT8135_PIN_122_DPICK__FUNC_PCM1_DI (MT_PIN_NO(122) | 5) +#define MT8135_PIN_122_DPICK__FUNC_IRDA_PDN (MT_PIN_NO(122) | 6) + +#define MT8135_PIN_123_DPIG4__FUNC_GPIO123 (MT_PIN_NO(123) | 0) +#define MT8135_PIN_123_DPIG4__FUNC_DPI0_G4 (MT_PIN_NO(123) | 1) +#define MT8135_PIN_123_DPIG4__FUNC_EINT114 (MT_PIN_NO(123) | 2) +#define MT8135_PIN_123_DPIG4__FUNC_CM2DAT_2X_0 (MT_PIN_NO(123) | 4) +#define MT8135_PIN_123_DPIG4__FUNC_DSP2_ID (MT_PIN_NO(123) | 5) + +#define MT8135_PIN_124_DPIG5__FUNC_GPIO124 (MT_PIN_NO(124) | 0) +#define MT8135_PIN_124_DPIG5__FUNC_DPI0_G5 (MT_PIN_NO(124) | 1) +#define MT8135_PIN_124_DPIG5__FUNC_EINT115 (MT_PIN_NO(124) | 2) +#define MT8135_PIN_124_DPIG5__FUNC_CM2DAT_2X_1 (MT_PIN_NO(124) | 4) +#define MT8135_PIN_124_DPIG5__FUNC_DSP2_ICK (MT_PIN_NO(124) | 5) + +#define MT8135_PIN_125_DPIR3__FUNC_GPIO125 (MT_PIN_NO(125) | 0) +#define MT8135_PIN_125_DPIR3__FUNC_DPI0_R3 (MT_PIN_NO(125) | 1) +#define MT8135_PIN_125_DPIR3__FUNC_EINT121 (MT_PIN_NO(125) | 2) +#define MT8135_PIN_125_DPIR3__FUNC_CM2DAT_2X_7 (MT_PIN_NO(125) | 4) + +#define MT8135_PIN_126_DPIG1__FUNC_GPIO126 (MT_PIN_NO(126) | 0) +#define MT8135_PIN_126_DPIG1__FUNC_DPI0_G1 (MT_PIN_NO(126) | 1) +#define MT8135_PIN_126_DPIG1__FUNC_EINT111 (MT_PIN_NO(126) | 2) +#define MT8135_PIN_126_DPIG1__FUNC_DSP1_ICK (MT_PIN_NO(126) | 5) + +#define MT8135_PIN_127_DPIVSYNC__FUNC_GPIO127 (MT_PIN_NO(127) | 0) +#define MT8135_PIN_127_DPIVSYNC__FUNC_DPI0_VSYNC (MT_PIN_NO(127) | 1) +#define MT8135_PIN_127_DPIVSYNC__FUNC_EINT98 (MT_PIN_NO(127) | 2) +#define MT8135_PIN_127_DPIVSYNC__FUNC_I2SIN_CK (MT_PIN_NO(127) | 3) +#define MT8135_PIN_127_DPIVSYNC__FUNC_DAC_CK (MT_PIN_NO(127) | 4) +#define MT8135_PIN_127_DPIVSYNC__FUNC_PCM1_CK (MT_PIN_NO(127) | 5) + +#define MT8135_PIN_128_DPIHSYNC__FUNC_GPIO128 (MT_PIN_NO(128) | 0) +#define MT8135_PIN_128_DPIHSYNC__FUNC_DPI0_HSYNC (MT_PIN_NO(128) | 1) +#define MT8135_PIN_128_DPIHSYNC__FUNC_EINT99 (MT_PIN_NO(128) | 2) +#define MT8135_PIN_128_DPIHSYNC__FUNC_I2SIN_WS (MT_PIN_NO(128) | 3) +#define MT8135_PIN_128_DPIHSYNC__FUNC_DAC_WS (MT_PIN_NO(128) | 4) +#define MT8135_PIN_128_DPIHSYNC__FUNC_PCM1_WS (MT_PIN_NO(128) | 5) +#define MT8135_PIN_128_DPIHSYNC__FUNC_IRDA_RXD (MT_PIN_NO(128) | 6) + +#define MT8135_PIN_129_DPIB0__FUNC_GPIO129 (MT_PIN_NO(129) | 0) +#define MT8135_PIN_129_DPIB0__FUNC_DPI0_B0 (MT_PIN_NO(129) | 1) +#define MT8135_PIN_129_DPIB0__FUNC_EINT102 (MT_PIN_NO(129) | 2) +#define MT8135_PIN_129_DPIB0__FUNC_SCL0 (MT_PIN_NO(129) | 4) +#define MT8135_PIN_129_DPIB0__FUNC_DISP_PWM (MT_PIN_NO(129) | 5) + +#define MT8135_PIN_130_DPIB1__FUNC_GPIO130 (MT_PIN_NO(130) | 0) +#define MT8135_PIN_130_DPIB1__FUNC_DPI0_B1 (MT_PIN_NO(130) | 1) +#define MT8135_PIN_130_DPIB1__FUNC_EINT103 (MT_PIN_NO(130) | 2) +#define MT8135_PIN_130_DPIB1__FUNC_CLKM0 (MT_PIN_NO(130) | 3) +#define MT8135_PIN_130_DPIB1__FUNC_SDA0 (MT_PIN_NO(130) | 4) +#define MT8135_PIN_130_DPIB1__FUNC_PWM1 (MT_PIN_NO(130) | 5) + +#define MT8135_PIN_131_DPIB2__FUNC_GPIO131 (MT_PIN_NO(131) | 0) +#define MT8135_PIN_131_DPIB2__FUNC_DPI0_B2 (MT_PIN_NO(131) | 1) +#define MT8135_PIN_131_DPIB2__FUNC_EINT104 (MT_PIN_NO(131) | 2) +#define MT8135_PIN_131_DPIB2__FUNC_CLKM1 (MT_PIN_NO(131) | 3) +#define MT8135_PIN_131_DPIB2__FUNC_SCL1 (MT_PIN_NO(131) | 4) +#define MT8135_PIN_131_DPIB2__FUNC_PWM2 (MT_PIN_NO(131) | 5) + +#define MT8135_PIN_132_DPIB3__FUNC_GPIO132 (MT_PIN_NO(132) | 0) +#define MT8135_PIN_132_DPIB3__FUNC_DPI0_B3 (MT_PIN_NO(132) | 1) +#define MT8135_PIN_132_DPIB3__FUNC_EINT105 (MT_PIN_NO(132) | 2) +#define MT8135_PIN_132_DPIB3__FUNC_CLKM2 (MT_PIN_NO(132) | 3) +#define MT8135_PIN_132_DPIB3__FUNC_SDA1 (MT_PIN_NO(132) | 4) +#define MT8135_PIN_132_DPIB3__FUNC_PWM3 (MT_PIN_NO(132) | 5) + +#define MT8135_PIN_133_DPIB4__FUNC_GPIO133 (MT_PIN_NO(133) | 0) +#define MT8135_PIN_133_DPIB4__FUNC_DPI0_B4 (MT_PIN_NO(133) | 1) +#define MT8135_PIN_133_DPIB4__FUNC_EINT106 (MT_PIN_NO(133) | 2) +#define MT8135_PIN_133_DPIB4__FUNC_CLKM3 (MT_PIN_NO(133) | 3) +#define MT8135_PIN_133_DPIB4__FUNC_SCL2 (MT_PIN_NO(133) | 4) +#define MT8135_PIN_133_DPIB4__FUNC_PWM4 (MT_PIN_NO(133) | 5) + +#define MT8135_PIN_134_DPIB5__FUNC_GPIO134 (MT_PIN_NO(134) | 0) +#define MT8135_PIN_134_DPIB5__FUNC_DPI0_B5 (MT_PIN_NO(134) | 1) +#define MT8135_PIN_134_DPIB5__FUNC_EINT107 (MT_PIN_NO(134) | 2) +#define MT8135_PIN_134_DPIB5__FUNC_CLKM4 (MT_PIN_NO(134) | 3) +#define MT8135_PIN_134_DPIB5__FUNC_SDA2 (MT_PIN_NO(134) | 4) +#define MT8135_PIN_134_DPIB5__FUNC_PWM5 (MT_PIN_NO(134) | 5) + +#define MT8135_PIN_135_DPIB6__FUNC_GPIO135 (MT_PIN_NO(135) | 0) +#define MT8135_PIN_135_DPIB6__FUNC_DPI0_B6 (MT_PIN_NO(135) | 1) +#define MT8135_PIN_135_DPIB6__FUNC_EINT108 (MT_PIN_NO(135) | 2) +#define MT8135_PIN_135_DPIB6__FUNC_CLKM5 (MT_PIN_NO(135) | 3) +#define MT8135_PIN_135_DPIB6__FUNC_SCL3 (MT_PIN_NO(135) | 4) +#define MT8135_PIN_135_DPIB6__FUNC_PWM6 (MT_PIN_NO(135) | 5) + +#define MT8135_PIN_136_DPIB7__FUNC_GPIO136 (MT_PIN_NO(136) | 0) +#define MT8135_PIN_136_DPIB7__FUNC_DPI0_B7 (MT_PIN_NO(136) | 1) +#define MT8135_PIN_136_DPIB7__FUNC_EINT109 (MT_PIN_NO(136) | 2) +#define MT8135_PIN_136_DPIB7__FUNC_CLKM6 (MT_PIN_NO(136) | 3) +#define MT8135_PIN_136_DPIB7__FUNC_SDA3 (MT_PIN_NO(136) | 4) +#define MT8135_PIN_136_DPIB7__FUNC_PWM7 (MT_PIN_NO(136) | 5) + +#define MT8135_PIN_137_DPIG0__FUNC_GPIO137 (MT_PIN_NO(137) | 0) +#define MT8135_PIN_137_DPIG0__FUNC_DPI0_G0 (MT_PIN_NO(137) | 1) +#define MT8135_PIN_137_DPIG0__FUNC_EINT110 (MT_PIN_NO(137) | 2) +#define MT8135_PIN_137_DPIG0__FUNC_DSP1_ID (MT_PIN_NO(137) | 5) + +#define MT8135_PIN_138_DPIG2__FUNC_GPIO138 (MT_PIN_NO(138) | 0) +#define MT8135_PIN_138_DPIG2__FUNC_DPI0_G2 (MT_PIN_NO(138) | 1) +#define MT8135_PIN_138_DPIG2__FUNC_EINT112 (MT_PIN_NO(138) | 2) +#define MT8135_PIN_138_DPIG2__FUNC_DSP1_IMS (MT_PIN_NO(138) | 5) + +#define MT8135_PIN_139_DPIG3__FUNC_GPIO139 (MT_PIN_NO(139) | 0) +#define MT8135_PIN_139_DPIG3__FUNC_DPI0_G3 (MT_PIN_NO(139) | 1) +#define MT8135_PIN_139_DPIG3__FUNC_EINT113 (MT_PIN_NO(139) | 2) +#define MT8135_PIN_139_DPIG3__FUNC_DSP2_IMS (MT_PIN_NO(139) | 5) + +#define MT8135_PIN_140_DPIG6__FUNC_GPIO140 (MT_PIN_NO(140) | 0) +#define MT8135_PIN_140_DPIG6__FUNC_DPI0_G6 (MT_PIN_NO(140) | 1) +#define MT8135_PIN_140_DPIG6__FUNC_EINT116 (MT_PIN_NO(140) | 2) +#define MT8135_PIN_140_DPIG6__FUNC_CM2DAT_2X_2 (MT_PIN_NO(140) | 4) + +#define MT8135_PIN_141_DPIG7__FUNC_GPIO141 (MT_PIN_NO(141) | 0) +#define MT8135_PIN_141_DPIG7__FUNC_DPI0_G7 (MT_PIN_NO(141) | 1) +#define MT8135_PIN_141_DPIG7__FUNC_EINT117 (MT_PIN_NO(141) | 2) +#define MT8135_PIN_141_DPIG7__FUNC_CM2DAT_2X_3 (MT_PIN_NO(141) | 4) + +#define MT8135_PIN_142_DPIR0__FUNC_GPIO142 (MT_PIN_NO(142) | 0) +#define MT8135_PIN_142_DPIR0__FUNC_DPI0_R0 (MT_PIN_NO(142) | 1) +#define MT8135_PIN_142_DPIR0__FUNC_EINT118 (MT_PIN_NO(142) | 2) +#define MT8135_PIN_142_DPIR0__FUNC_CM2DAT_2X_4 (MT_PIN_NO(142) | 4) + +#define MT8135_PIN_143_DPIR1__FUNC_GPIO143 (MT_PIN_NO(143) | 0) +#define MT8135_PIN_143_DPIR1__FUNC_DPI0_R1 (MT_PIN_NO(143) | 1) +#define MT8135_PIN_143_DPIR1__FUNC_EINT119 (MT_PIN_NO(143) | 2) +#define MT8135_PIN_143_DPIR1__FUNC_CM2DAT_2X_5 (MT_PIN_NO(143) | 4) + +#define MT8135_PIN_144_DPIR2__FUNC_GPIO144 (MT_PIN_NO(144) | 0) +#define MT8135_PIN_144_DPIR2__FUNC_DPI0_R2 (MT_PIN_NO(144) | 1) +#define MT8135_PIN_144_DPIR2__FUNC_EINT120 (MT_PIN_NO(144) | 2) +#define MT8135_PIN_144_DPIR2__FUNC_CM2DAT_2X_6 (MT_PIN_NO(144) | 4) + +#define MT8135_PIN_145_DPIR4__FUNC_GPIO145 (MT_PIN_NO(145) | 0) +#define MT8135_PIN_145_DPIR4__FUNC_DPI0_R4 (MT_PIN_NO(145) | 1) +#define MT8135_PIN_145_DPIR4__FUNC_EINT122 (MT_PIN_NO(145) | 2) +#define MT8135_PIN_145_DPIR4__FUNC_CM2DAT_2X_8 (MT_PIN_NO(145) | 4) + +#define MT8135_PIN_146_DPIR5__FUNC_GPIO146 (MT_PIN_NO(146) | 0) +#define MT8135_PIN_146_DPIR5__FUNC_DPI0_R5 (MT_PIN_NO(146) | 1) +#define MT8135_PIN_146_DPIR5__FUNC_EINT123 (MT_PIN_NO(146) | 2) +#define MT8135_PIN_146_DPIR5__FUNC_CM2DAT_2X_9 (MT_PIN_NO(146) | 4) + +#define MT8135_PIN_147_DPIR6__FUNC_GPIO147 (MT_PIN_NO(147) | 0) +#define MT8135_PIN_147_DPIR6__FUNC_DPI0_R6 (MT_PIN_NO(147) | 1) +#define MT8135_PIN_147_DPIR6__FUNC_EINT124 (MT_PIN_NO(147) | 2) +#define MT8135_PIN_147_DPIR6__FUNC_CM2VSYNC_2X (MT_PIN_NO(147) | 4) + +#define MT8135_PIN_148_DPIR7__FUNC_GPIO148 (MT_PIN_NO(148) | 0) +#define MT8135_PIN_148_DPIR7__FUNC_DPI0_R7 (MT_PIN_NO(148) | 1) +#define MT8135_PIN_148_DPIR7__FUNC_EINT125 (MT_PIN_NO(148) | 2) +#define MT8135_PIN_148_DPIR7__FUNC_CM2HSYNC_2X (MT_PIN_NO(148) | 4) + +#define MT8135_PIN_149_TDN3__FUNC_GPIO149 (MT_PIN_NO(149) | 0) +#define MT8135_PIN_149_TDN3__FUNC_EINT36 (MT_PIN_NO(149) | 2) + +#define MT8135_PIN_150_TDP3__FUNC_GPIO150 (MT_PIN_NO(150) | 0) +#define MT8135_PIN_150_TDP3__FUNC_EINT35 (MT_PIN_NO(150) | 2) + +#define MT8135_PIN_151_TDN2__FUNC_GPIO151 (MT_PIN_NO(151) | 0) +#define MT8135_PIN_151_TDN2__FUNC_EINT169 (MT_PIN_NO(151) | 2) + +#define MT8135_PIN_152_TDP2__FUNC_GPIO152 (MT_PIN_NO(152) | 0) +#define MT8135_PIN_152_TDP2__FUNC_EINT168 (MT_PIN_NO(152) | 2) + +#define MT8135_PIN_153_TCN__FUNC_GPIO153 (MT_PIN_NO(153) | 0) +#define MT8135_PIN_153_TCN__FUNC_EINT163 (MT_PIN_NO(153) | 2) + +#define MT8135_PIN_154_TCP__FUNC_GPIO154 (MT_PIN_NO(154) | 0) +#define MT8135_PIN_154_TCP__FUNC_EINT162 (MT_PIN_NO(154) | 2) + +#define MT8135_PIN_155_TDN1__FUNC_GPIO155 (MT_PIN_NO(155) | 0) +#define MT8135_PIN_155_TDN1__FUNC_EINT167 (MT_PIN_NO(155) | 2) + +#define MT8135_PIN_156_TDP1__FUNC_GPIO156 (MT_PIN_NO(156) | 0) +#define MT8135_PIN_156_TDP1__FUNC_EINT166 (MT_PIN_NO(156) | 2) + +#define MT8135_PIN_157_TDN0__FUNC_GPIO157 (MT_PIN_NO(157) | 0) +#define MT8135_PIN_157_TDN0__FUNC_EINT165 (MT_PIN_NO(157) | 2) + +#define MT8135_PIN_158_TDP0__FUNC_GPIO158 (MT_PIN_NO(158) | 0) +#define MT8135_PIN_158_TDP0__FUNC_EINT164 (MT_PIN_NO(158) | 2) + +#define MT8135_PIN_159_RDN3__FUNC_GPIO159 (MT_PIN_NO(159) | 0) +#define MT8135_PIN_159_RDN3__FUNC_EINT18 (MT_PIN_NO(159) | 2) + +#define MT8135_PIN_160_RDP3__FUNC_GPIO160 (MT_PIN_NO(160) | 0) +#define MT8135_PIN_160_RDP3__FUNC_EINT30 (MT_PIN_NO(160) | 2) + +#define MT8135_PIN_161_RDN2__FUNC_GPIO161 (MT_PIN_NO(161) | 0) +#define MT8135_PIN_161_RDN2__FUNC_EINT31 (MT_PIN_NO(161) | 2) + +#define MT8135_PIN_162_RDP2__FUNC_GPIO162 (MT_PIN_NO(162) | 0) +#define MT8135_PIN_162_RDP2__FUNC_EINT32 (MT_PIN_NO(162) | 2) + +#define MT8135_PIN_163_RCN__FUNC_GPIO163 (MT_PIN_NO(163) | 0) +#define MT8135_PIN_163_RCN__FUNC_EINT33 (MT_PIN_NO(163) | 2) + +#define MT8135_PIN_164_RCP__FUNC_GPIO164 (MT_PIN_NO(164) | 0) +#define MT8135_PIN_164_RCP__FUNC_EINT39 (MT_PIN_NO(164) | 2) + +#define MT8135_PIN_165_RDN1__FUNC_GPIO165 (MT_PIN_NO(165) | 0) + +#define MT8135_PIN_166_RDP1__FUNC_GPIO166 (MT_PIN_NO(166) | 0) + +#define MT8135_PIN_167_RDN0__FUNC_GPIO167 (MT_PIN_NO(167) | 0) + +#define MT8135_PIN_168_RDP0__FUNC_GPIO168 (MT_PIN_NO(168) | 0) + +#define MT8135_PIN_169_RDN1_A__FUNC_GPIO169 (MT_PIN_NO(169) | 0) +#define MT8135_PIN_169_RDN1_A__FUNC_CMDAT6 (MT_PIN_NO(169) | 1) +#define MT8135_PIN_169_RDN1_A__FUNC_EINT175 (MT_PIN_NO(169) | 2) + +#define MT8135_PIN_170_RDP1_A__FUNC_GPIO170 (MT_PIN_NO(170) | 0) +#define MT8135_PIN_170_RDP1_A__FUNC_CMDAT7 (MT_PIN_NO(170) | 1) +#define MT8135_PIN_170_RDP1_A__FUNC_EINT174 (MT_PIN_NO(170) | 2) + +#define MT8135_PIN_171_RCN_A__FUNC_GPIO171 (MT_PIN_NO(171) | 0) +#define MT8135_PIN_171_RCN_A__FUNC_CMDAT8 (MT_PIN_NO(171) | 1) +#define MT8135_PIN_171_RCN_A__FUNC_EINT171 (MT_PIN_NO(171) | 2) + +#define MT8135_PIN_172_RCP_A__FUNC_GPIO172 (MT_PIN_NO(172) | 0) +#define MT8135_PIN_172_RCP_A__FUNC_CMDAT9 (MT_PIN_NO(172) | 1) +#define MT8135_PIN_172_RCP_A__FUNC_EINT170 (MT_PIN_NO(172) | 2) + +#define MT8135_PIN_173_RDN0_A__FUNC_GPIO173 (MT_PIN_NO(173) | 0) +#define MT8135_PIN_173_RDN0_A__FUNC_CMHSYNC (MT_PIN_NO(173) | 1) +#define MT8135_PIN_173_RDN0_A__FUNC_EINT173 (MT_PIN_NO(173) | 2) + +#define MT8135_PIN_174_RDP0_A__FUNC_GPIO174 (MT_PIN_NO(174) | 0) +#define MT8135_PIN_174_RDP0_A__FUNC_CMVSYNC (MT_PIN_NO(174) | 1) +#define MT8135_PIN_174_RDP0_A__FUNC_EINT172 (MT_PIN_NO(174) | 2) + +#define MT8135_PIN_175_RDN1_B__FUNC_GPIO175 (MT_PIN_NO(175) | 0) +#define MT8135_PIN_175_RDN1_B__FUNC_CMDAT2 (MT_PIN_NO(175) | 1) +#define MT8135_PIN_175_RDN1_B__FUNC_EINT181 (MT_PIN_NO(175) | 2) +#define MT8135_PIN_175_RDN1_B__FUNC_CMCSD2 (MT_PIN_NO(175) | 3) + +#define MT8135_PIN_176_RDP1_B__FUNC_GPIO176 (MT_PIN_NO(176) | 0) +#define MT8135_PIN_176_RDP1_B__FUNC_CMDAT3 (MT_PIN_NO(176) | 1) +#define MT8135_PIN_176_RDP1_B__FUNC_EINT180 (MT_PIN_NO(176) | 2) +#define MT8135_PIN_176_RDP1_B__FUNC_CMCSD3 (MT_PIN_NO(176) | 3) + +#define MT8135_PIN_177_RCN_B__FUNC_GPIO177 (MT_PIN_NO(177) | 0) +#define MT8135_PIN_177_RCN_B__FUNC_CMDAT4 (MT_PIN_NO(177) | 1) +#define MT8135_PIN_177_RCN_B__FUNC_EINT177 (MT_PIN_NO(177) | 2) + +#define MT8135_PIN_178_RCP_B__FUNC_GPIO178 (MT_PIN_NO(178) | 0) +#define MT8135_PIN_178_RCP_B__FUNC_CMDAT5 (MT_PIN_NO(178) | 1) +#define MT8135_PIN_178_RCP_B__FUNC_EINT176 (MT_PIN_NO(178) | 2) + +#define MT8135_PIN_179_RDN0_B__FUNC_GPIO179 (MT_PIN_NO(179) | 0) +#define MT8135_PIN_179_RDN0_B__FUNC_CMDAT0 (MT_PIN_NO(179) | 1) +#define MT8135_PIN_179_RDN0_B__FUNC_EINT179 (MT_PIN_NO(179) | 2) +#define MT8135_PIN_179_RDN0_B__FUNC_CMCSD0 (MT_PIN_NO(179) | 3) + +#define MT8135_PIN_180_RDP0_B__FUNC_GPIO180 (MT_PIN_NO(180) | 0) +#define MT8135_PIN_180_RDP0_B__FUNC_CMDAT1 (MT_PIN_NO(180) | 1) +#define MT8135_PIN_180_RDP0_B__FUNC_EINT178 (MT_PIN_NO(180) | 2) +#define MT8135_PIN_180_RDP0_B__FUNC_CMCSD1 (MT_PIN_NO(180) | 3) + +#define MT8135_PIN_181_CMPCLK__FUNC_GPIO181 (MT_PIN_NO(181) | 0) +#define MT8135_PIN_181_CMPCLK__FUNC_CMPCLK (MT_PIN_NO(181) | 1) +#define MT8135_PIN_181_CMPCLK__FUNC_EINT182 (MT_PIN_NO(181) | 2) +#define MT8135_PIN_181_CMPCLK__FUNC_CMCSK (MT_PIN_NO(181) | 3) +#define MT8135_PIN_181_CMPCLK__FUNC_CM2MCLK_4X (MT_PIN_NO(181) | 4) +#define MT8135_PIN_181_CMPCLK__FUNC_TS_AUXADC_SEL_3 (MT_PIN_NO(181) | 5) +#define MT8135_PIN_181_CMPCLK__FUNC_VENC_TEST_CK (MT_PIN_NO(181) | 6) +#define MT8135_PIN_181_CMPCLK__FUNC_TESTA_OUT27 (MT_PIN_NO(181) | 7) + +#define MT8135_PIN_182_CMMCLK__FUNC_GPIO182 (MT_PIN_NO(182) | 0) +#define MT8135_PIN_182_CMMCLK__FUNC_CMMCLK (MT_PIN_NO(182) | 1) +#define MT8135_PIN_182_CMMCLK__FUNC_EINT183 (MT_PIN_NO(182) | 2) +#define MT8135_PIN_182_CMMCLK__FUNC_TS_AUXADC_SEL_2 (MT_PIN_NO(182) | 5) +#define MT8135_PIN_182_CMMCLK__FUNC_TESTA_OUT28 (MT_PIN_NO(182) | 7) + +#define MT8135_PIN_183_CMRST__FUNC_GPIO183 (MT_PIN_NO(183) | 0) +#define MT8135_PIN_183_CMRST__FUNC_CMRST (MT_PIN_NO(183) | 1) +#define MT8135_PIN_183_CMRST__FUNC_EINT185 (MT_PIN_NO(183) | 2) +#define MT8135_PIN_183_CMRST__FUNC_TS_AUXADC_SEL_1 (MT_PIN_NO(183) | 5) +#define MT8135_PIN_183_CMRST__FUNC_TESTA_OUT30 (MT_PIN_NO(183) | 7) + +#define MT8135_PIN_184_CMPDN__FUNC_GPIO184 (MT_PIN_NO(184) | 0) +#define MT8135_PIN_184_CMPDN__FUNC_CMPDN (MT_PIN_NO(184) | 1) +#define MT8135_PIN_184_CMPDN__FUNC_EINT184 (MT_PIN_NO(184) | 2) +#define MT8135_PIN_184_CMPDN__FUNC_TS_AUXADC_SEL_0 (MT_PIN_NO(184) | 5) +#define MT8135_PIN_184_CMPDN__FUNC_TESTA_OUT29 (MT_PIN_NO(184) | 7) + +#define MT8135_PIN_185_CMFLASH__FUNC_GPIO185 (MT_PIN_NO(185) | 0) +#define MT8135_PIN_185_CMFLASH__FUNC_CMFLASH (MT_PIN_NO(185) | 1) +#define MT8135_PIN_185_CMFLASH__FUNC_EINT186 (MT_PIN_NO(185) | 2) +#define MT8135_PIN_185_CMFLASH__FUNC_CM2MCLK_3X (MT_PIN_NO(185) | 3) +#define MT8135_PIN_185_CMFLASH__FUNC_MFG_TEST_CK_1 (MT_PIN_NO(185) | 6) +#define MT8135_PIN_185_CMFLASH__FUNC_TESTA_OUT31 (MT_PIN_NO(185) | 7) + +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_GPIO186 (MT_PIN_NO(186) | 0) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_MRG_I2S_CLK (MT_PIN_NO(186) | 1) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_EINT14 (MT_PIN_NO(186) | 2) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_I2SIN_CK (MT_PIN_NO(186) | 3) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_PCM0_CK (MT_PIN_NO(186) | 4) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_DSP2_ICK (MT_PIN_NO(186) | 5) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_IMG_TEST_CK (MT_PIN_NO(186) | 6) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_USB_SCL (MT_PIN_NO(186) | 7) + +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_GPIO187 (MT_PIN_NO(187) | 0) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_MRG_I2S_SYNC (MT_PIN_NO(187) | 1) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_EINT16 (MT_PIN_NO(187) | 2) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_I2SIN_WS (MT_PIN_NO(187) | 3) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_PCM0_WS (MT_PIN_NO(187) | 4) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_DISP_TEST_CK (MT_PIN_NO(187) | 6) + +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_GPIO188 (MT_PIN_NO(188) | 0) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MRG_I2S_PCM_RX (MT_PIN_NO(188) | 1) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_EINT15 (MT_PIN_NO(188) | 2) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_I2SIN_DAT (MT_PIN_NO(188) | 3) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_PCM0_DI (MT_PIN_NO(188) | 4) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_DSP2_ID (MT_PIN_NO(188) | 5) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MFG_TEST_CK (MT_PIN_NO(188) | 6) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_USB_SDA (MT_PIN_NO(188) | 7) + +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_GPIO189 (MT_PIN_NO(189) | 0) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_MRG_I2S_PCM_TX (MT_PIN_NO(189) | 1) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_EINT17 (MT_PIN_NO(189) | 2) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_I2SOUT_DAT (MT_PIN_NO(189) | 3) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_PCM0_DO (MT_PIN_NO(189) | 4) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_VDEC_TEST_CK (MT_PIN_NO(189) | 6) + +#define MT8135_PIN_190_SRCLKENAI__FUNC_GPIO190 (MT_PIN_NO(190) | 0) +#define MT8135_PIN_190_SRCLKENAI__FUNC_SRCLKENAI (MT_PIN_NO(190) | 1) + +#define MT8135_PIN_191_URXD3__FUNC_GPIO191 (MT_PIN_NO(191) | 0) +#define MT8135_PIN_191_URXD3__FUNC_URXD3 (MT_PIN_NO(191) | 1) +#define MT8135_PIN_191_URXD3__FUNC_EINT87 (MT_PIN_NO(191) | 2) +#define MT8135_PIN_191_URXD3__FUNC_UTXD3 (MT_PIN_NO(191) | 3) +#define MT8135_PIN_191_URXD3__FUNC_TS_AUX_ST (MT_PIN_NO(191) | 5) +#define MT8135_PIN_191_URXD3__FUNC_PWM4 (MT_PIN_NO(191) | 6) + +#define MT8135_PIN_192_UTXD3__FUNC_GPIO192 (MT_PIN_NO(192) | 0) +#define MT8135_PIN_192_UTXD3__FUNC_UTXD3 (MT_PIN_NO(192) | 1) +#define MT8135_PIN_192_UTXD3__FUNC_EINT86 (MT_PIN_NO(192) | 2) +#define MT8135_PIN_192_UTXD3__FUNC_URXD3 (MT_PIN_NO(192) | 3) +#define MT8135_PIN_192_UTXD3__FUNC_TS_AUX_CS_B (MT_PIN_NO(192) | 5) +#define MT8135_PIN_192_UTXD3__FUNC_PWM3 (MT_PIN_NO(192) | 6) + +#define MT8135_PIN_193_SDA2__FUNC_GPIO193 (MT_PIN_NO(193) | 0) +#define MT8135_PIN_193_SDA2__FUNC_SDA2 (MT_PIN_NO(193) | 1) +#define MT8135_PIN_193_SDA2__FUNC_EINT95 (MT_PIN_NO(193) | 2) +#define MT8135_PIN_193_SDA2__FUNC_CLKM5 (MT_PIN_NO(193) | 3) +#define MT8135_PIN_193_SDA2__FUNC_PWM5 (MT_PIN_NO(193) | 4) +#define MT8135_PIN_193_SDA2__FUNC_TS_AUX_PWDB (MT_PIN_NO(193) | 5) + +#define MT8135_PIN_194_SCL2__FUNC_GPIO194 (MT_PIN_NO(194) | 0) +#define MT8135_PIN_194_SCL2__FUNC_SCL2 (MT_PIN_NO(194) | 1) +#define MT8135_PIN_194_SCL2__FUNC_EINT94 (MT_PIN_NO(194) | 2) +#define MT8135_PIN_194_SCL2__FUNC_CLKM4 (MT_PIN_NO(194) | 3) +#define MT8135_PIN_194_SCL2__FUNC_PWM4 (MT_PIN_NO(194) | 4) +#define MT8135_PIN_194_SCL2__FUNC_TS_AUXADC_TEST_CK (MT_PIN_NO(194) | 5) + +#define MT8135_PIN_195_SDA1__FUNC_GPIO195 (MT_PIN_NO(195) | 0) +#define MT8135_PIN_195_SDA1__FUNC_SDA1 (MT_PIN_NO(195) | 1) +#define MT8135_PIN_195_SDA1__FUNC_EINT93 (MT_PIN_NO(195) | 2) +#define MT8135_PIN_195_SDA1__FUNC_CLKM3 (MT_PIN_NO(195) | 3) +#define MT8135_PIN_195_SDA1__FUNC_PWM3 (MT_PIN_NO(195) | 4) +#define MT8135_PIN_195_SDA1__FUNC_TS_AUX_SCLK_PWDB (MT_PIN_NO(195) | 5) + +#define MT8135_PIN_196_SCL1__FUNC_GPIO196 (MT_PIN_NO(196) | 0) +#define MT8135_PIN_196_SCL1__FUNC_SCL1 (MT_PIN_NO(196) | 1) +#define MT8135_PIN_196_SCL1__FUNC_EINT92 (MT_PIN_NO(196) | 2) +#define MT8135_PIN_196_SCL1__FUNC_CLKM2 (MT_PIN_NO(196) | 3) +#define MT8135_PIN_196_SCL1__FUNC_PWM2 (MT_PIN_NO(196) | 4) +#define MT8135_PIN_196_SCL1__FUNC_TS_AUX_DIN (MT_PIN_NO(196) | 5) + +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_GPIO197 (MT_PIN_NO(197) | 0) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MT_PIN_NO(197) | 1) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_EINT71 (MT_PIN_NO(197) | 2) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_SCL6 (MT_PIN_NO(197) | 3) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_PWM5 (MT_PIN_NO(197) | 4) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_CLKM4 (MT_PIN_NO(197) | 5) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MFG_TEST_CK_2 (MT_PIN_NO(197) | 6) + +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_GPIO198 (MT_PIN_NO(198) | 0) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MT_PIN_NO(198) | 1) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_EINT72 (MT_PIN_NO(198) | 2) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_SDA6 (MT_PIN_NO(198) | 3) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_PWM6 (MT_PIN_NO(198) | 4) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_CLKM5 (MT_PIN_NO(198) | 5) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MFG_TEST_CK_3 (MT_PIN_NO(198) | 6) + +#define MT8135_PIN_199_MSDC3_CMD__FUNC_GPIO199 (MT_PIN_NO(199) | 0) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_MSDC3_CMD (MT_PIN_NO(199) | 1) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_EINT68 (MT_PIN_NO(199) | 2) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_SDA2 (MT_PIN_NO(199) | 3) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_PWM2 (MT_PIN_NO(199) | 4) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_CLKM1 (MT_PIN_NO(199) | 5) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_MFG_TEST_CK_4 (MT_PIN_NO(199) | 6) + +#define MT8135_PIN_200_MSDC3_CLK__FUNC_GPIO200 (MT_PIN_NO(200) | 0) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_MSDC3_CLK (MT_PIN_NO(200) | 1) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_EINT67 (MT_PIN_NO(200) | 2) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_SCL2 (MT_PIN_NO(200) | 3) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_PWM1 (MT_PIN_NO(200) | 4) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_CLKM0 (MT_PIN_NO(200) | 5) + +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_GPIO201 (MT_PIN_NO(201) | 0) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MT_PIN_NO(201) | 1) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_EINT70 (MT_PIN_NO(201) | 2) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_SDA3 (MT_PIN_NO(201) | 3) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_PWM4 (MT_PIN_NO(201) | 4) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_CLKM3 (MT_PIN_NO(201) | 5) + +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_GPIO202 (MT_PIN_NO(202) | 0) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MT_PIN_NO(202) | 1) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_EINT69 (MT_PIN_NO(202) | 2) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_SCL3 (MT_PIN_NO(202) | 3) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_PWM3 (MT_PIN_NO(202) | 4) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_CLKM2 (MT_PIN_NO(202) | 5) + +#endif /* __DTS_MT8135_PINFUNC_H */ diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi index 90a56ad..1bfd3d0 100644 --- a/arch/arm/boot/dts/mt8135.dtsi +++ b/arch/arm/boot/dts/mt8135.dtsi @@ -15,6 +15,8 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "skeleton64.dtsi" +#include "mt8135-pinfunc.h" +#include <dt-bindings/pinctrl/mt65xx.h> / { compatible = "mediatek,mt8135"; @@ -111,5 +113,14 @@ <0 0x10214000 0 0x2000>, <0 0x10216000 0 0x2000>; }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8135-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x1020C000 0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + }; }; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. 2014-09-23 3:39 ` [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135 Hongzhou.Yang @ 2014-09-23 13:03 ` Arnd Bergmann 2014-09-23 13:58 ` Joe.C 2014-09-24 11:23 ` Linus Walleij 1 sibling, 1 reply; 27+ messages in thread From: Arnd Bergmann @ 2014-09-23 13:03 UTC (permalink / raw) To: linux-arm-kernel Cc: Hongzhou. Yang, Rob Herring, Linus Walleij, Matthias Brugger, Mark Rutland, devicetree, Vladimir Murzin, Russell King, srv_heupstream, Pawel Moll, Ian Campbell On Tuesday 23 September 2014 11:39:05 Hongzhou. Yang wrote: > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MT_PIN_NO(0) | 0) > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MT_PIN_NO(0) | 1) > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MT_PIN_NO(0) | 2) > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MT_PIN_NO(0) | 3) > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MT_PIN_NO(0) | 4) > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MT_PIN_NO(0) | 5) > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MT_PIN_NO(0) | 6) > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MT_PIN_NO(0) | 7) > + This list looks like it just describes the hardware, I think it would be better to put the values directly into the DT, rather than using such macros. Arnd ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. 2014-09-23 13:03 ` Arnd Bergmann @ 2014-09-23 13:58 ` Joe.C 2014-09-23 14:10 ` Arnd Bergmann 2014-09-23 14:16 ` Chen-Yu Tsai 0 siblings, 2 replies; 27+ messages in thread From: Joe.C @ 2014-09-23 13:58 UTC (permalink / raw) To: Arnd Bergmann Cc: Mark Rutland, devicetree, Hongzhou. Yang, Vladimir Murzin, Russell King, srv_heupstream, Pawel Moll, Ian Campbell On Tue, 2014-09-23 at 15:03 +0200, Arnd Bergmann wrote: > On Tuesday 23 September 2014 11:39:05 Hongzhou. Yang wrote: > > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MT_PIN_NO(0) | 0) > > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MT_PIN_NO(0) | 1) > > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MT_PIN_NO(0) | 2) > > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MT_PIN_NO(0) | 3) > > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MT_PIN_NO(0) | 4) > > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MT_PIN_NO(0) | 5) > > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MT_PIN_NO(0) | 6) > > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MT_PIN_NO(0) | 7) > > + > > This list looks like it just describes the hardware, I think it would > be better to put the values directly into the DT, rather than > using such macros. Hi, Thanks for review. The intend for these macros is helpin pinctrl user to write DT node. With these macro, we could write like this for i2c0: mediatek,pinfunc = <MT8135_PIN_100_SDA0__FUNC_SDA0 MT8135_PIN_101_SCL0__FUNC_SCL0>; We feel this is less error prone and easier to write than this: mediatek,pinfunc = <MT_PIN_FUNC(100, 1) MT_PIN_FUNC(101, 1)> Joe.C ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. 2014-09-23 13:58 ` Joe.C @ 2014-09-23 14:10 ` Arnd Bergmann 2014-09-23 14:29 ` Joe.C 2014-09-23 14:55 ` Sascha Hauer 2014-09-23 14:16 ` Chen-Yu Tsai 1 sibling, 2 replies; 27+ messages in thread From: Arnd Bergmann @ 2014-09-23 14:10 UTC (permalink / raw) To: Joe. C Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Hongzhou. Yang, Vladimir Murzin, Russell King, Pawel Moll, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Ian Campbell On Tuesday 23 September 2014 21:58:14 Joe. C wrote: > Thanks for review. > The intend for these macros is helpin pinctrl user to write DT node. > With these macro, we could write like this for i2c0: > > mediatek,pinfunc = <MT8135_PIN_100_SDA0__FUNC_SDA0 > MT8135_PIN_101_SCL0__FUNC_SCL0>; > > We feel this is less error prone and easier to write than this: > > mediatek,pinfunc = <MT_PIN_FUNC(100, 1) MT_PIN_FUNC(101, 1)> But you don't actually use the same macros in the driver, so in effect you just move the definitions from the file they are needed in to another file as a macro. It is no less error prone to define those macros in mt8135-pinfunc.h than in the pinctrl node, just less readable. Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. 2014-09-23 14:10 ` Arnd Bergmann @ 2014-09-23 14:29 ` Joe.C 2014-09-23 14:55 ` Sascha Hauer 1 sibling, 0 replies; 27+ messages in thread From: Joe.C @ 2014-09-23 14:29 UTC (permalink / raw) To: Arnd Bergmann Cc: Mark Rutland, devicetree, Hongzhou. Yang, Vladimir Murzin, Russell King, srv_heupstream, Pawel Moll, Ian Campbell On Tue, 2014-09-23 at 16:10 +0200, Arnd Bergmann wrote: > On Tuesday 23 September 2014 21:58:14 Joe. C wrote: > > Thanks for review. > > The intend for these macros is helpin pinctrl user to write DT node. > > With these macro, we could write like this for i2c0: > > > > mediatek,pinfunc = <MT8135_PIN_100_SDA0__FUNC_SDA0 > > MT8135_PIN_101_SCL0__FUNC_SCL0>; > > > > We feel this is less error prone and easier to write than this: > > > > mediatek,pinfunc = <MT_PIN_FUNC(100, 1) MT_PIN_FUNC(101, 1)> > > But you don't actually use the same macros in the driver, so in effect > you just move the definitions from the file they are needed in to another > file as a macro. > > It is no less error prone to define those macros in mt8135-pinfunc.h > than in the pinctrl node, just less readable. > > Arnd Yes, mt8135-pinfunc.h must be in sync with pinctrl-mtk-mt8135.h in patch 2/4, otherwise it is a bug. We use script to generate macros to make sure they are in sync. Joe.C ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. 2014-09-23 14:10 ` Arnd Bergmann 2014-09-23 14:29 ` Joe.C @ 2014-09-23 14:55 ` Sascha Hauer 1 sibling, 0 replies; 27+ messages in thread From: Sascha Hauer @ 2014-09-23 14:55 UTC (permalink / raw) To: Arnd Bergmann Cc: Joe. C, linux-arm-kernel, Mark Rutland, devicetree, Hongzhou. Yang, Vladimir Murzin, Russell King, Pawel Moll, srv_heupstream, Ian Campbell On Tue, Sep 23, 2014 at 04:10:09PM +0200, Arnd Bergmann wrote: > On Tuesday 23 September 2014 21:58:14 Joe. C wrote: > > Thanks for review. > > The intend for these macros is helpin pinctrl user to write DT node. > > With these macro, we could write like this for i2c0: > > > > mediatek,pinfunc = <MT8135_PIN_100_SDA0__FUNC_SDA0 > > MT8135_PIN_101_SCL0__FUNC_SCL0>; > > > > We feel this is less error prone and easier to write than this: > > > > mediatek,pinfunc = <MT_PIN_FUNC(100, 1) MT_PIN_FUNC(101, 1)> > > But you don't actually use the same macros in the driver, so in effect > you just move the definitions from the file they are needed in to another > file as a macro. > > It is no less error prone to define those macros in mt8135-pinfunc.h > than in the pinctrl node, just less readable. IMO these defines make writing and reviewing dts files much easier. Once the macros are used widely and thus are likely correct you can be sure that every board has sane and non conflicting pin setups. The pin names can often be found in the schematics of a board, so you can verify the pinmux settings without looking in the SoC datasheet. If all you have in the dts files is MT_PIN_FUNC(pinx, funcy) then it can be quite hard to verify pins. First you have to get an idea how the pin numbers match the pins in the datasheet. In the bindings the pins are numbered, in the datasheet they usually only have names. Afterwards you have to find out which functions this pin has and how these match to the function number in the binding. Repeat this for dozens of pins. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. 2014-09-23 13:58 ` Joe.C 2014-09-23 14:10 ` Arnd Bergmann @ 2014-09-23 14:16 ` Chen-Yu Tsai 2014-09-23 15:08 ` Joe.C 1 sibling, 1 reply; 27+ messages in thread From: Chen-Yu Tsai @ 2014-09-23 14:16 UTC (permalink / raw) To: Joe.C Cc: Arnd Bergmann, Mark Rutland, devicetree, Hongzhou. Yang, Vladimir Murzin, Russell King, srv_heupstream, Pawel Moll, Ian Campbell Hi, On Tue, Sep 23, 2014 at 9:58 PM, Joe.C <srv_yingjoe.chen@mediatek.com> wrote: > On Tue, 2014-09-23 at 15:03 +0200, Arnd Bergmann wrote: >> On Tuesday 23 September 2014 11:39:05 Hongzhou. Yang wrote: >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MT_PIN_NO(0) | 0) >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MT_PIN_NO(0) | 1) >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MT_PIN_NO(0) | 2) >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MT_PIN_NO(0) | 3) >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MT_PIN_NO(0) | 4) >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MT_PIN_NO(0) | 5) >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MT_PIN_NO(0) | 6) >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MT_PIN_NO(0) | 7) >> > + >> >> This list looks like it just describes the hardware, I think it would >> be better to put the values directly into the DT, rather than >> using such macros. > > Hi, > > Thanks for review. > The intend for these macros is helpin pinctrl user to write DT node. > With these macro, we could write like this for i2c0: > > mediatek,pinfunc = <MT8135_PIN_100_SDA0__FUNC_SDA0 > MT8135_PIN_101_SCL0__FUNC_SCL0>; > > We feel this is less error prone and easier to write than this: > > mediatek,pinfunc = <MT_PIN_FUNC(100, 1) MT_PIN_FUNC(101, 1)> Since you've already imposed the following limit in the DT bindings: The mediatek,pinfunc can be either a single value or an array. If it is an array, that means all pins use same config in this node. Maybe you could split the bindings into mediatek,pins = <1 2 3 4>; mediatek,func = <1>; (or some macro) Or better yet, since you've already defined all the function names in the pinctrl driver, you could just match by name for the functions. That makes it very verbose and explicit about what you specify. That's how we do it for sunxi anyway. Of course we have all the pin function documentation open, so users and reviewers alike can double check. Just a suggestion. :) Cheers ChenYu ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. 2014-09-23 14:16 ` Chen-Yu Tsai @ 2014-09-23 15:08 ` Joe.C 0 siblings, 0 replies; 27+ messages in thread From: Joe.C @ 2014-09-23 15:08 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Mark Rutland, devicetree, Hongzhou. Yang, Vladimir Murzin, Russell King, srv_heupstream, Arnd Bergmann, Ian Campbell On Tue, 2014-09-23 at 22:16 +0800, Chen-Yu Tsai wrote: > Hi, > > On Tue, Sep 23, 2014 at 9:58 PM, Joe.C <srv_yingjoe.chen@mediatek.com> wrote: > > On Tue, 2014-09-23 at 15:03 +0200, Arnd Bergmann wrote: > >> On Tuesday 23 September 2014 11:39:05 Hongzhou. Yang wrote: > >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MT_PIN_NO(0) | 0) > >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MT_PIN_NO(0) | 1) > >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MT_PIN_NO(0) | 2) > >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MT_PIN_NO(0) | 3) > >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MT_PIN_NO(0) | 4) > >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MT_PIN_NO(0) | 5) > >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MT_PIN_NO(0) | 6) > >> > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MT_PIN_NO(0) | 7) > >> > + > >> > >> This list looks like it just describes the hardware, I think it would > >> be better to put the values directly into the DT, rather than > >> using such macros. > > > > Hi, > > > > Thanks for review. > > The intend for these macros is helpin pinctrl user to write DT node. > > With these macro, we could write like this for i2c0: > > > > mediatek,pinfunc = <MT8135_PIN_100_SDA0__FUNC_SDA0 > > MT8135_PIN_101_SCL0__FUNC_SCL0>; > > > > We feel this is less error prone and easier to write than this: > > > > mediatek,pinfunc = <MT_PIN_FUNC(100, 1) MT_PIN_FUNC(101, 1)> > > > Since you've already imposed the following limit in the DT bindings: > > The mediatek,pinfunc can be either a single value or an array. > If it is an array, that means all pins use same config in this node. > > Maybe you could split the bindings into > > mediatek,pins = <1 2 3 4>; > mediatek,func = <1>; (or some macro) > > Or better yet, since you've already defined all the function names > in the pinctrl driver, you could just match by name for the functions. > That makes it very verbose and explicit about what you specify. > > That's how we do it for sunxi anyway. Of course we have all the pin > function documentation open, so users and reviewers alike can double > check. Just a suggestion. :) > > > Cheers > ChenYu Actually, this is exactly what we do in our first version(matching names and use separate pins/func). That's why the source code and pinctrl-mtk-mt8135.h are very simlar to sunxi one (Thanks :)) But we think it might worth to reduce string mathching at boot time, that's why we changed to use integer + macro in this version. Unfortunately, we still can't release documents openly now. I hope we could change that someday. Joe.C ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. 2014-09-23 3:39 ` [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135 Hongzhou.Yang 2014-09-23 13:03 ` Arnd Bergmann @ 2014-09-24 11:23 ` Linus Walleij 2014-09-24 12:40 ` Sascha Hauer 1 sibling, 1 reply; 27+ messages in thread From: Linus Walleij @ 2014-09-24 11:23 UTC (permalink / raw) To: Hongzhou.Yang Cc: Rob Herring, Matthias Brugger, srv_heupstream, Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely, Hongzhou Yang, Joe.C, Catalin Marinas, Vladimir Murzin, Ashwin Chaugule, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dandan.he On Tue, Sep 23, 2014 at 5:39 AM, Hongzhou.Yang <srv_hongzhou.yang@mediatek.com> wrote: > From: Hongzhou Yang <hongzhou.yang@mediatek.com> > > Add pinctrl node to mt8135.dtsi. > > Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> (...) > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MT_PIN_NO(0) | 0) > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MT_PIN_NO(0) | 1) > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MT_PIN_NO(0) | 2) > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MT_PIN_NO(0) | 3) I haven't got to reviewing the driver, but this looks just wrong. Have the magic numbers in the driver. Use strings to describe functions, not integers. We need to move toward standardized device tree bindings for this stuff, and that means using strings, not magic numbers. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. 2014-09-24 11:23 ` Linus Walleij @ 2014-09-24 12:40 ` Sascha Hauer [not found] ` <20140924124044.GC4992-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> 0 siblings, 1 reply; 27+ messages in thread From: Sascha Hauer @ 2014-09-24 12:40 UTC (permalink / raw) To: Linus Walleij Cc: Hongzhou.Yang, Rob Herring, Matthias Brugger, srv_heupstream, Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely Hi Linus, On Wed, Sep 24, 2014 at 01:23:09PM +0200, Linus Walleij wrote: > On Tue, Sep 23, 2014 at 5:39 AM, Hongzhou.Yang > <srv_hongzhou.yang@mediatek.com> wrote: > > > From: Hongzhou Yang <hongzhou.yang@mediatek.com> > > > > Add pinctrl node to mt8135.dtsi. > > > > Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> > (...) > > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MT_PIN_NO(0) | 0) > > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MT_PIN_NO(0) | 1) > > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MT_PIN_NO(0) | 2) > > +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MT_PIN_NO(0) | 3) > > I haven't got to reviewing the driver, but this looks just wrong. > > Have the magic numbers in the driver. > > Use strings to describe functions, not integers. Interrupts, clocks, gpios, dma channels, nearly everything in the device tree is arbitrarily numbered. Instead of "irq-i2c0" we have <0 36 IRQ_TYPE_LEVEL_HIGH> in the device tree. These numbers can be resolved efficiently in the driver by shifting them to get a bitmask or by adding them as offset to a register base. Why do you want to make pinctrl different? Thanks to the recently introduced defines in the device trees these numbers are not magic at all anymore. > > We need to move toward standardized device tree bindings > for this stuff, and that means using strings, not magic > numbers. Agreed for standardized device tree bindings, but not for using strings. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 27+ messages in thread
[parent not found: <20140924124044.GC4992-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>]
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. [not found] ` <20140924124044.GC4992-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> @ 2014-09-26 5:32 ` Sascha Hauer 2014-10-02 14:02 ` Linus Walleij 1 sibling, 0 replies; 27+ messages in thread From: Sascha Hauer @ 2014-09-26 5:32 UTC (permalink / raw) To: Linus Walleij Cc: Hongzhou.Yang, Rob Herring, Matthias Brugger, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely Linus, On Wed, Sep 24, 2014 at 02:40:44PM +0200, Sascha Hauer wrote: > > I haven't got to reviewing the driver, but this looks just wrong. > > > > Have the magic numbers in the driver. > > > > Use strings to describe functions, not integers. > > Interrupts, clocks, gpios, dma channels, nearly everything in the device tree is > arbitrarily numbered. Instead of "irq-i2c0" we have <0 36 IRQ_TYPE_LEVEL_HIGH> > in the device tree. These numbers can be resolved efficiently in the > driver by shifting them to get a bitmask or by adding them as offset to > a register base. > Why do you want to make pinctrl different? Thanks to the recently > introduced defines in the device trees these numbers are not magic at > all anymore. Any opinions on this? Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. [not found] ` <20140924124044.GC4992-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> 2014-09-26 5:32 ` Sascha Hauer @ 2014-10-02 14:02 ` Linus Walleij [not found] ` <CACRpkdbtN-BDEwpJO2swnOjCe3UJhD5WOXXKBV0hPOe2M2=k7Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 1 sibling, 1 reply; 27+ messages in thread From: Linus Walleij @ 2014-10-02 14:02 UTC (permalink / raw) To: Sascha Hauer Cc: Hongzhou.Yang, Rob Herring, Matthias Brugger, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely On Wed, Sep 24, 2014 at 2:40 PM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote: > On Wed, Sep 24, 2014 at 01:23:09PM +0200, Linus Walleij wrote: >> I haven't got to reviewing the driver, but this looks just wrong. >> >> Have the magic numbers in the driver. >> >> Use strings to describe functions, not integers. > > Interrupts, clocks, gpios, dma channels, nearly everything in the device tree is > arbitrarily numbered. Instead of "irq-i2c0" we have <0 36 IRQ_TYPE_LEVEL_HIGH> > in the device tree. These numbers can be resolved efficiently in the > driver by shifting them to get a bitmask or by adding them as offset to > a register base. > Why do you want to make pinctrl different? Because pin control is about combining groups of pins with certain functions. > Thanks to the recently > introduced defines in the device trees these numbers are not magic at > all anymore. Yeah that is good but not what I'm after here. >> We need to move toward standardized device tree bindings >> for this stuff, and that means using strings, not magic >> numbers. > > Agreed for standardized device tree bindings, but not for using strings. What is the alternative? Device Tree is very much about strings, as is shown by the pin config bindings. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 27+ messages in thread
[parent not found: <CACRpkdbtN-BDEwpJO2swnOjCe3UJhD5WOXXKBV0hPOe2M2=k7Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. [not found] ` <CACRpkdbtN-BDEwpJO2swnOjCe3UJhD5WOXXKBV0hPOe2M2=k7Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2014-10-02 14:28 ` Lucas Stach 2014-10-21 8:58 ` Linus Walleij 2014-10-06 7:18 ` Sascha Hauer 1 sibling, 1 reply; 27+ messages in thread From: Lucas Stach @ 2014-10-02 14:28 UTC (permalink / raw) To: Linus Walleij Cc: Sascha Hauer, Mark Rutland, Ashwin Chaugule, Hongzhou.Yang, Vladimir Murzin, Russell King, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Pawel Moll, Ian Campbell Hi Linus, Am Donnerstag, den 02.10.2014, 16:02 +0200 schrieb Linus Walleij: > On Wed, Sep 24, 2014 at 2:40 PM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote: > > On Wed, Sep 24, 2014 at 01:23:09PM +0200, Linus Walleij wrote: > > >> I haven't got to reviewing the driver, but this looks just wrong. > >> > >> Have the magic numbers in the driver. > >> > >> Use strings to describe functions, not integers. > > > > Interrupts, clocks, gpios, dma channels, nearly everything in the device tree is > > arbitrarily numbered. Instead of "irq-i2c0" we have <0 36 IRQ_TYPE_LEVEL_HIGH> > > in the device tree. These numbers can be resolved efficiently in the > > driver by shifting them to get a bitmask or by adding them as offset to > > a register base. > > Why do you want to make pinctrl different? > > Because pin control is about combining groups of pins with > certain functions. > > > Thanks to the recently > > introduced defines in the device trees these numbers are not magic at > > all anymore. > > Yeah that is good but not what I'm after here. > > >> We need to move toward standardized device tree bindings > >> for this stuff, and that means using strings, not magic > >> numbers. > > > > Agreed for standardized device tree bindings, but not for using strings. > > What is the alternative? Device Tree is very much about strings, > as is shown by the pin config bindings. > Mhm, maybe we are still talking about different things but I just don't get your point. Traditionally DT is more about plain numbers than strings. Look at the early examples of PCI or other bus bindings, defined back in the IEEE 1275 days. Almost everything back then has been mapped to plain numbers. Using strings only bloats the DT, not only in it's source form, but also as a compiled DTB. Having a verbose string based binding is just painful to work with (I can tell from experience here, as I personally built the pinmux setup for two Tegra boards). Working with a condensed number based binding like the one used on i.MX is much easier IMHO. Most importantly I don't see any benefit in writing: pin_state_a { pins = "i2c0_scl", "i2c0_sda"; function = "i2c0"; }; instead of #include <dt-binding/pinctrl/mediatek_foo.h> pin_state_a { pins = <I2C0_SCL>, <I2C0_SDA>; function = <I2C0>; } Using plain integers makes it much easier to index into pinctrl driver specific arrays without doing all this string matching in the kernel. It seems we are eating CPU cycles here for no good reason. Could you please explain where you see the benefit of using strings instead of plain integers with proper binding defines attached to them? Regards, Lucas -- Pengutronix e.K. | Lucas Stach | Industrial Linux Solutions | http://www.pengutronix.de/ | -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. 2014-10-02 14:28 ` Lucas Stach @ 2014-10-21 8:58 ` Linus Walleij 0 siblings, 0 replies; 27+ messages in thread From: Linus Walleij @ 2014-10-21 8:58 UTC (permalink / raw) To: Lucas Stach Cc: Sascha Hauer, Mark Rutland, Ashwin Chaugule, Hongzhou.Yang, Vladimir Murzin, Russell King, srv_heupstream, Pawel Moll, Ian Campbell On Thu, Oct 2, 2014 at 4:28 PM, Lucas Stach <l.stach@pengutronix.de> wrote: > Am Donnerstag, den 02.10.2014, 16:02 +0200 schrieb Linus Walleij: >> > Agreed for standardized device tree bindings, but not for using strings. >> >> What is the alternative? Device Tree is very much about strings, >> as is shown by the pin config bindings. >> > Mhm, maybe we are still talking about different things but I just don't > get your point. Traditionally DT is more about plain numbers than > strings. Look at the early examples of PCI or other bus bindings, > defined back in the IEEE 1275 days. Almost everything back then has > been mapped to plain numbers. > > Using strings only bloats the DT, not only in it's source form, but also > as a compiled DTB. (...) OK I think we have arrived (in this thread and in others) to the old discussion of whether to use groups or per-pin function setting in drivers. Let us move forward like this: I have proposed a general binding of functions+groups (as strings) which will be suitable for some. What would you propose as a general binding for systems using per-pin configuration? My problem as a subsystem maintainer is that there are too many custom bindings. We need to standardize on something. For pin config we have attained some consensus, and that is indeed using strings "bias-pull-up" etc, simply because there is no sane way to enumerate them all, and it is simple to read by humans. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. [not found] ` <CACRpkdbtN-BDEwpJO2swnOjCe3UJhD5WOXXKBV0hPOe2M2=k7Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2014-10-02 14:28 ` Lucas Stach @ 2014-10-06 7:18 ` Sascha Hauer [not found] ` <20141006071841.GN4992-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> 1 sibling, 1 reply; 27+ messages in thread From: Sascha Hauer @ 2014-10-06 7:18 UTC (permalink / raw) To: Linus Walleij Cc: Hongzhou.Yang, Rob Herring, Matthias Brugger, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely On Thu, Oct 02, 2014 at 04:02:58PM +0200, Linus Walleij wrote: > On Wed, Sep 24, 2014 at 2:40 PM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote: > > On Wed, Sep 24, 2014 at 01:23:09PM +0200, Linus Walleij wrote: > > >> I haven't got to reviewing the driver, but this looks just wrong. > >> > >> Have the magic numbers in the driver. > >> > >> Use strings to describe functions, not integers. > > > > Interrupts, clocks, gpios, dma channels, nearly everything in the device tree is > > arbitrarily numbered. Instead of "irq-i2c0" we have <0 36 IRQ_TYPE_LEVEL_HIGH> > > in the device tree. These numbers can be resolved efficiently in the > > driver by shifting them to get a bitmask or by adding them as offset to > > a register base. > > Why do you want to make pinctrl different? > > Because pin control is about combining groups of pins with > certain functions. > > > Thanks to the recently > > introduced defines in the device trees these numbers are not magic at > > all anymore. > > Yeah that is good but not what I'm after here. > > >> We need to move toward standardized device tree bindings > >> for this stuff, and that means using strings, not magic > >> numbers. > > > > Agreed for standardized device tree bindings, but not for using strings. > > What is the alternative? Device Tree is very much about strings, > as is shown by the pin config bindings. The alternative is to use numbers. The majority of SoCs have a bit field per pad which is used for muxing the pad to different functions. The natural way to describe this is a pair of numbers: <pad-number> <function-number>. The pad number can normally be directly translated into a register offset and the function number to a value written to that register. This is true for most SoCs I know of and makes it very easy to generate code for and to prove for correctness of both the code and the device tree. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 27+ messages in thread
[parent not found: <20141006071841.GN4992-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>]
* Re: [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135. [not found] ` <20141006071841.GN4992-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> @ 2014-10-21 9:02 ` Linus Walleij 0 siblings, 0 replies; 27+ messages in thread From: Linus Walleij @ 2014-10-21 9:02 UTC (permalink / raw) To: Sascha Hauer Cc: Hongzhou.Yang, Rob Herring, Matthias Brugger, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely On Mon, Oct 6, 2014 at 9:18 AM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote: > On Thu, Oct 02, 2014 at 04:02:58PM +0200, Linus Walleij wrote: >> What is the alternative? Device Tree is very much about strings, >> as is shown by the pin config bindings. > > The alternative is to use numbers. The majority of SoCs have a bit field > per pad which is used for muxing the pad to different functions. The > natural way to describe this is a pair of numbers: <pad-number> > <function-number>. The pad number can normally be directly translated > into a register offset and the function number to a value written to > that register. This is true for most SoCs I know of and makes it very > easy to generate code for and to prove for correctness of both the code > and the device tree. To me this sounds more like a discussion on how to set up a good firmware (BIOS) that the kernel can call into. We have had many times the discussion whether DT should contain "jam tables" and such things, i.e. stuff that basically translate DT directly to register writes. The one exception we have for this is pinctrl-single.c which uses a single word to configure a pin. I'm even not sure that was a good idea but it was a compromise. If someone wants the above, they should use pinctrl-single.c (OMAP and HiSilicon uses it already), if they need another necessarily different driver I'm very reluctant. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 27+ messages in thread
[parent not found: <1411443545-24951-1-git-send-email-srv_hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH v2 0/4] Add Mediatek SoC Pinctrl/GPIO driver for MT8135. [not found] ` <1411443545-24951-1-git-send-email-srv_hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> @ 2014-09-23 13:28 ` Matthias Brugger 0 siblings, 0 replies; 27+ messages in thread From: Matthias Brugger @ 2014-09-23 13:28 UTC (permalink / raw) To: Hongzhou.Yang, Rob Herring, Linus Walleij Cc: srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King, Grant Likely, Hongzhou Yang, Joe.C, Catalin Marinas, Vladimir Murzin, Ashwin Chaugule, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, dandan.he-NuS5LvNUpcJWk0Htik3J/w On 23/09/14 05:39, Hongzhou.Yang wrote: > This is v2 of add Mediatek SoC Pinctrl/GPIO drvier for MT8135. > It is based on Joe.C' basic device tree support. > See http://lists.infradead.org/pipermail/linux-arm-kernel/2014-September/288582.html > > This driver include common and MT8135 part, other Mediatek SoCs will share the common part, > and MT8135 part only support MT8135. MT8135 has GPIO controller, it includes 203 pins. > > Changes in v2: > - According to Heiko Stubner' suggestion, use generic pinconfig. Please always add people that made comments on your former versions in CC. This way it is easier for them to follow the debate about your patches. Thanks, Matthias > - Remove pinmux_ops.disable implement. > - Due to limit of message body, move mt8135-pinfunc.h to '[PATCH 3/4] add pinctrl node for MT8135'. > > > Hongzhou Yang (3): > ARM: mediatek: Add Pinctrl/GPIO driver for mt8135. > dt-bindings: Add pinctrl bindings for mt65xx/mt81xx. > ARM: dts: mt8135: Add pinctrl node for mt8135. > > Joe.C (1): > arm: mediatek: Add config option for mediatek SoCs. > > .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 98 + > arch/arm/boot/dts/mt8135-pinfunc.h | 1304 +++++++++++ > arch/arm/boot/dts/mt8135.dtsi | 11 + > arch/arm/mach-mediatek/Kconfig | 23 +- > drivers/pinctrl/Kconfig | 1 + > drivers/pinctrl/Makefile | 1 + > drivers/pinctrl/mediatek/Kconfig | 12 + > drivers/pinctrl/mediatek/Makefile | 5 + > drivers/pinctrl/mediatek/pinctrl-mt8135.c | 82 + > drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 792 +++++++ > drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 95 + > drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h | 2460 ++++++++++++++++++++ > include/dt-bindings/pinctrl/mt65xx.h | 23 + > 13 files changed, 4904 insertions(+), 3 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt > create mode 100644 arch/arm/boot/dts/mt8135-pinfunc.h > create mode 100644 drivers/pinctrl/mediatek/Kconfig > create mode 100644 drivers/pinctrl/mediatek/Makefile > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8135.c > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h > create mode 100644 include/dt-bindings/pinctrl/mt65xx.h > > -- > 1.8.1.1.dirty > > > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2014-10-21 9:08 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-09-23 3:39 [PATCH v2 0/4] Add Mediatek SoC Pinctrl/GPIO driver for MT8135 Hongzhou.Yang
2014-09-23 3:39 ` [PATCH v2 1/4] arm: mediatek: Add config option for mediatek SoCs Hongzhou.Yang
2014-09-23 3:39 ` [PATCH v2 2/4] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135 Hongzhou.Yang
2014-10-02 13:38 ` Linus Walleij
2014-10-06 10:35 ` Joe.C
2014-10-21 9:08 ` Linus Walleij
2014-09-23 3:39 ` [PATCH v2 3/4] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx Hongzhou.Yang
[not found] ` <1411443545-24951-4-git-send-email-srv_hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2014-10-02 14:00 ` Linus Walleij
2014-10-02 14:41 ` Lucas Stach
2014-10-21 8:45 ` Linus Walleij
2014-09-23 3:39 ` [PATCH v2 4/4] ARM: dts: mt8135: Add pinctrl node for mt8135 Hongzhou.Yang
2014-09-23 13:03 ` Arnd Bergmann
2014-09-23 13:58 ` Joe.C
2014-09-23 14:10 ` Arnd Bergmann
2014-09-23 14:29 ` Joe.C
2014-09-23 14:55 ` Sascha Hauer
2014-09-23 14:16 ` Chen-Yu Tsai
2014-09-23 15:08 ` Joe.C
2014-09-24 11:23 ` Linus Walleij
2014-09-24 12:40 ` Sascha Hauer
[not found] ` <20140924124044.GC4992-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2014-09-26 5:32 ` Sascha Hauer
2014-10-02 14:02 ` Linus Walleij
[not found] ` <CACRpkdbtN-BDEwpJO2swnOjCe3UJhD5WOXXKBV0hPOe2M2=k7Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-10-02 14:28 ` Lucas Stach
2014-10-21 8:58 ` Linus Walleij
2014-10-06 7:18 ` Sascha Hauer
[not found] ` <20141006071841.GN4992-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2014-10-21 9:02 ` Linus Walleij
[not found] ` <1411443545-24951-1-git-send-email-srv_hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2014-09-23 13:28 ` [PATCH v2 0/4] Add Mediatek SoC Pinctrl/GPIO driver for MT8135 Matthias Brugger
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).