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From: Vinod Koul <vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
To: Andy Gross <agross-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Bjorn Andersson
	<bjorn.andersson-/MT0OVThwyLZJqsBc5GL+g@public.gmane.org>,
	dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 1/2] dmaengine: Add QCOM ADM DMA driver
Date: Wed, 24 Sep 2014 10:07:55 +0530	[thread overview]
Message-ID: <20140924043755.GQ24663@intel.com> (raw)
In-Reply-To: <20140923221002.GC5975-zC7DfRvBq/JWk0Htik3J/w@public.gmane.org>

On Tue, Sep 23, 2014 at 05:10:02PM -0500, Andy Gross wrote:
> <snip>
> 
> > > +			break;
> > > +		default:
> > > +			achan->slave.src_maxburst = 0;
> > > +			achan->slave.dst_maxburst = 0;
> > Why clear these for error cases
> 
> With the return I shouldn't need to.  I'll fix this.
> 
> > > +			ret = -EINVAL;
> > > +			break;
> > > +		}
> > > +
> > > +		if (!ret)
> > > +			writel(achan->blk_size,
> > > +				adev->regs + HI_CRCI_CTL(achan->id, adev->ee));
> > and why do we write to HW on this. Shouldn't this be done when you program
> > the descriptor?
> 
> It could be deferred to later.  The main point is that I don't see the
> slave_config happening every transaction.  I was only modifying it now instead
> of making a register write for every transaction.
Well wouldn't it cause a problem if you write to hardware and a transaction
is already in progress.
So it makese sense to write every time at transaction start with latest
value programmed.

> > 
> > > +static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
> > > +	struct dma_tx_state *txstate)
> > > +{
> > > +	struct adm_chan *achan = to_adm_chan(chan);
> > > +	struct virt_dma_desc *vd;
> > > +	enum dma_status ret;
> > > +	unsigned long flags;
> > > +	size_t residue = 0;
> > > +
> > > +	ret = dma_cookie_status(chan, cookie, txstate);
> > > +
> > Last arg can be null to this, so before you do residue calcluation and block
> > interrupts would make sense to return from here if arg is NULL
> 
> Good catch.  Will fix.
> 
> > 
> > > +	spin_lock_irqsave(&achan->vc.lock, flags);
> > > +
> > > +	vd = vchan_find_desc(&achan->vc, cookie);
> > > +	if (vd)
> > > +		residue = container_of(vd, struct adm_async_desc, vd)->length;
> > > +	else if (achan->curr_txd && achan->curr_txd->vd.tx.cookie == cookie)
> > > +		residue = achan->curr_txd->length;
> > so this is current cookie, so you need to read from HW on current position
> 
> There is no way to get current position unfortunately without relying on
> unreliable debug registers.
In that case would it make sense to return complete txn length?

-- 
~Vinod
--
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  parent reply	other threads:[~2014-09-24  4:37 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-11  2:18 [RESEND PATCH 0/2] Add Qualcomm ADM dmaengine driver Andy Gross
2014-09-11  2:18 ` [PATCH 1/2] dmaengine: Add QCOM ADM DMA driver Andy Gross
2014-09-23 10:28   ` Vinod Koul
2014-09-23 22:10     ` Andy Gross
     [not found]       ` <20140923221002.GC5975-zC7DfRvBq/JWk0Htik3J/w@public.gmane.org>
2014-09-24  4:37         ` Vinod Koul [this message]
2014-09-11  2:18 ` [PATCH 2/2] dmaengine: qcom_adm: Add device tree binding Andy Gross
2014-09-23 10:34   ` Vinod Koul
  -- strict thread matches above, loose matches on Subject: below --
2014-06-26 20:30 [PATCH 0/2] Add Qualcomm ADM dmaengine driver Andy Gross
2014-06-26 20:30 ` [PATCH 1/2] dmaengine: Add QCOM ADM DMA driver Andy Gross

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