From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Cc: Mike Turquette
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Emilio Lopez <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>,
Dan Williams
<dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
Grant Likely
<grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v2 2/7] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output
Date: Tue, 30 Sep 2014 17:39:57 +0200 [thread overview]
Message-ID: <20140930153957.GM4081@lukather> (raw)
In-Reply-To: <1411807795-6575-3-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
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Hi,
On Sat, Sep 27, 2014 at 04:49:50PM +0800, Chen-Yu Tsai wrote:
> Some clock modules on the A31 use PLL6x2 as one of their inputs.
> This patch changes the PLL6 implementation for A31 to a divs clock,
> i.e. clock with multiple outputs that have different dividers.
> The first output will be the normal PLL6 output, and the second
> will be PLL6x2.
>
> This patch fixes the PLL6 N factor in the clock driver, and removes
> any /2 dividers in the PLL6 factors clock part. The N factor counts
> from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual.
>
> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 5 ++--
> drivers/clk/sunxi/clk-sunxi.c | 28 +++++++++++++----------
> 2 files changed, 19 insertions(+), 14 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index d3a5c3c..0d84f4b 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -59,8 +59,9 @@ Required properties for all clocks:
> multiplexed clocks, the list order must match the hardware
> programming order.
> - #clock-cells : from common clock binding; shall be set to 0 except for
> - "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
> - "allwinner,sun4i-pll6-clk" where it shall be set to 1
> + the following compatibles where it shall be set to 1:
> + "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
> + "allwinner,sun4i-pll6-clk", "allwinner, sun6i-a31-pll6-clk"
^ Drop this extra space
And you're still not documenting what outputs you might have on pll6,
and what the extra argument correspond to.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2014-09-30 15:39 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-27 8:49 [PATCH v2 0/6] clk: sun6i: Unify AHB1 clock and fix rate calculation Chen-Yu Tsai
[not found] ` <1411807795-6575-1-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2014-09-27 8:49 ` [PATCH v2 1/7] clk: sunxi: Specify number of child clocks for divs clocks Chen-Yu Tsai
[not found] ` <1411807795-6575-2-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2014-09-30 15:40 ` Maxime Ripard
2014-09-30 15:56 ` Chen-Yu Tsai
[not found] ` <CAGb2v64RPi2J4gpWu7X15xSx89guPSoEs2_7Bxs9ywj023fabA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-10-03 14:05 ` Maxime Ripard
2014-09-27 8:49 ` [PATCH v2 2/7] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output Chen-Yu Tsai
[not found] ` <1411807795-6575-3-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2014-09-30 15:39 ` Maxime Ripard [this message]
2014-09-30 15:50 ` Chen-Yu Tsai
2014-09-27 8:49 ` [PATCH v2 3/7] ARM: sun6i: DT: Add PLL6 multiple outputs Chen-Yu Tsai
2014-09-27 8:49 ` [PATCH v2 4/7] clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider Chen-Yu Tsai
[not found] ` <1411807795-6575-5-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2014-09-30 15:54 ` Maxime Ripard
2014-10-06 12:58 ` Chen-Yu Tsai
[not found] ` <CAGb2v660nCkuY1Co6GsW6VYVguGssF4UpWPR-XQGb0oF+XqaCA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-10-06 13:44 ` Chen-Yu Tsai
2014-09-27 8:49 ` [PATCH v2 5/7] ARM: dts: sun6i: Unify ahb1 clock nodes Chen-Yu Tsai
2014-09-27 8:49 ` [PATCH v2 6/7] ARM: dts: sun8i: " Chen-Yu Tsai
2014-09-27 8:49 ` [PATCH v2 7/7] ARM: dts: sun6i: Add required ahb1 clock parent and rates for dma controller Chen-Yu Tsai
[not found] ` <1411807795-6575-8-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2014-09-30 15:55 ` Maxime Ripard
2014-10-09 3:01 ` Chen-Yu Tsai
[not found] ` <CAGb2v64TE=gzPdFJwfmJfpwWZcsdZQGONh11SawfBXZkWGFKCg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-10-13 10:02 ` Maxime Ripard
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