From: Sascha Hauer <s.hauer@pengutronix.de>
To: Johan Hovold <johan@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Florian Fainelli <f.fainelli@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH 19/22] dt/bindings: add micrel,rmii_ref_clk_sel_25_mhz to eth-phy binding
Date: Wed, 12 Nov 2014 08:01:27 +0100 [thread overview]
Message-ID: <20141112070127.GF30369@pengutronix.de> (raw)
In-Reply-To: <20141111181825.GH29789@localhost>
On Tue, Nov 11, 2014 at 07:18:25PM +0100, Johan Hovold wrote:
> On Tue, Nov 11, 2014 at 05:57:42PM +0000, Mark Rutland wrote:
> > On Tue, Nov 11, 2014 at 05:37:37PM +0000, Johan Hovold wrote:
> > > Add "micrel,rmii_ref_clk_sel_25_mhz" to Micrel ethernet PHY binding
> > > documentation.
> > >
> > > Cc: devicetree@vger.kernel.org
> > > Signed-off-by: Johan Hovold <johan@kernel.org>
> > > ---
> > > Documentation/devicetree/bindings/net/micrel.txt | 5 +++++
> > > 1 file changed, 5 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/net/micrel.txt b/Documentation/devicetree/bindings/net/micrel.txt
> > > index a1bab5eaae02..9b08dd6551dd 100644
> > > --- a/Documentation/devicetree/bindings/net/micrel.txt
> > > +++ b/Documentation/devicetree/bindings/net/micrel.txt
> > > @@ -19,6 +19,11 @@ Optional properties:
> > >
> > > See the respective PHY datasheet for the mode values.
> > >
> > > + - micrel,rmii_ref_clk_sel_25_mhz: rmii_ref_clk_sel bit selects 25 MHz mode
> > > +
> > > + Whether 25 MHz (rather than 50 Mhz) clock mode is selected
> > > + when the rmii_ref_clk_sel bit is set.
> >
> > s/_/-/ in property names please.
>
> Ouch, copied from variable name, sorry.
>
> > That said, I don't follow the meaning. Does this cause the kernel to do
> > something different, or is is simply that a 25MHz ref clock is wired up?
>
> Yes, the driver currently sets this configuration bit based on a common
> clock binding.
>
> However, it turns out the meaning of the bit is reversed on some PHY
> variants. On most PHYs 50 MHz mode is selected by setting this bit,
> whereas on the PHYs that need this new property, setting it selects 25
> MHz mode instead.
Maybe rename the property to something like rmii-ref-clk-25mhz-active-high
then? Also you should probably make it more explicit that this is a
hardware property and not for adjusting the clock.
It's not very nice from Micrel to create Phys with exactly the same
device id but the meaning of this bit reversed.
Sascha
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next prev parent reply other threads:[~2014-11-12 7:01 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1415727460-20417-1-git-send-email-johan@kernel.org>
[not found] ` <1415727460-20417-1-git-send-email-johan-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2014-11-11 17:37 ` [PATCH 01/22] dt/bindings: fix documentation of ethernet-phy compatible property Johan Hovold
2014-11-11 17:37 ` [PATCH 19/22] dt/bindings: add micrel,rmii_ref_clk_sel_25_mhz to eth-phy binding Johan Hovold
2014-11-11 17:57 ` Mark Rutland
2014-11-11 18:18 ` Johan Hovold
2014-11-12 7:01 ` Sascha Hauer [this message]
2014-11-12 9:19 ` Johan Hovold
2014-11-13 8:09 ` Sascha Hauer
2014-11-14 11:21 ` Johan Hovold
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