[PATCH 1/2] arm: dts: imx6q: update cpufreq volt/freq table

[PATCH 1/2] arm: dts: imx6q: update cpufreq volt/freq table

[Anson Huang]

According to latest i.MX6Q datasheet Rev. 3, 02/2014,
the latest cpufreq volt/freq table is as below:

LDO enabled/bypassed(min value):
996MHz: VDDARM: 1.225V, VDDSOC: 1.150V;
792MHz: VDDARM: 1.150V, VDDSOC: 1.150V;
396MHz: VDDARM: 0.925V, VDDSOC: 1.150V;

the 792MHz setpoint's VDDARM min voltage is updated
from 1.125V to 1.150V, adding 25mV to cover board IR
drop, 1.175V is the right voltage we should use.

Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
 arch/arm/boot/dts/imx6q.dtsi |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 85f72e6..37ee4e5 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -31,7 +31,7 @@
 				1200000 1275000
 				996000  1250000
 				852000  1250000
-				792000  1150000
+				792000  1175000
 				396000  975000
 			>;
 			fsl,soc-operating-points = <
-- 
1.7.9.5

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[PATCH 2/2] arm: dts: imx6dl: correct cpufreq volt/freq table

[Anson Huang]

Currently the cpufreq volt/freq table we used is
for LDO enable mode, according to latest datasheet
Rev. 3, 03/2014, the volt/freq table is as below:

LDO enabled(min value):
996MHz: VDDARM: 1.225V, VDDSOC: 1.150V;
792MHz: VDDARM: 1.150V, VDDSOC: 1.150V;
396MHz: VDDARM: 1.050V, VDDSOC: 1.150V;

LDO bypassed(min value):
996MHz: VDDARM: 1.250V, VDDSOC: 1.150V;
792MHz: VDDARM: 1.150V, VDDSOC: 1.150V;
396MHz: VDDARM: 1.050V, VDDSOC: 1.150V;

Adding 25mV to cover board IR drop, for LDO enabled
mode of 996MHz, VDDARM should be 1.250V, so this
patch updates it.

Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
 arch/arm/boot/dts/imx6dl.dtsi |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 1ac2fe7..f94bf72 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -28,7 +28,7 @@
 			next-level-cache = <&L2>;
 			operating-points = <
 				/* kHz    uV */
-				996000  1275000
+				996000  1250000
 				792000  1175000
 				396000  1075000
 			>;
-- 
1.7.9.5

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Re: [PATCH 2/2] arm: dts: imx6dl: correct cpufreq volt/freq table

[Philipp Zabel]

Am Freitag, den 05.12.2014, 16:23 +0800 schrieb Anson Huang:
> Currently the cpufreq volt/freq table we used is
> for LDO enable mode, according to latest datasheet
> Rev. 3, 03/2014, the volt/freq table is as below:
> 
> LDO enabled(min value):
> 996MHz: VDDARM: 1.225V, VDDSOC: 1.150V;
> 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V;
> 396MHz: VDDARM: 1.050V, VDDSOC: 1.150V;

>From which datasheet is this? I find it unlikely that the LDO enabled
values are not larger than the LDO bypassed ones. I just had a look at
the "i.MXSolo/6DualLite Automotive and Infotainment Applications
Processors" Datasheet (IMX6SDLAEC) Rev. 3, 03/2014 and the "i.MX
6Solo/6DualLite Applications Processors for Consumer Products" Datasheet
(IMX6SDLCEC) Rev. 3, 03/2014, and they both have different values in
Table 9 (Operating Ranges) for the LDO enabled case:

LDO enabled(min value):
996MHz: VDDARM: 1.350V, VDDSOC: 1.275V;
792MHz: VDDARM: 1.275V, VDDSOC: 1.275V;
396MHz: VDDARM: 1.175V, VDDSOC: 1.275V;

> LDO bypassed(min value):
> 996MHz: VDDARM: 1.250V, VDDSOC: 1.150V;
> 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V;
> 396MHz: VDDARM: 1.050V, VDDSOC: 1.150V;
> 
> Adding 25mV to cover board IR drop, for LDO enabled
> mode of 996MHz, VDDARM should be 1.250V, so this
> patch updates it.
> 
> Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>

regards
Philipp

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RE: [PATCH 2/2] arm: dts: imx6dl: correct cpufreq volt/freq table

[Anson.Huang-KZfg59tc24xl57MIdRCFDg]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 2258 bytes --]

Hi, Philipp
	The table you listed is VDDARM_IN and VDDSOC_IN which is for external PMIC and we normally do NOT adjust them when cpufreq change, we only adjust the internel LDO output, my table is for VDDARM_CAP and VDDSOC_CAP which are in the comment column, for LDO output.

For LDO enabled mode, VDDARM/SOC_CAP is the output of LDO, we pass this table to kernel opp.
For LDO bypassed mode, VDDARM/SOC_IN = VDDARM/SOC_CAP.
 
Best regards!
Anson Huang


-----Original Message-----
From: Philipp Zabel [mailto:p.zabel@pengutronix.de] 
Sent: 2014-12-05 5:39 PM
To: Huang Yongcai-B20788
Cc: shawn.guo@linaro.org; kernel@pengutronix.de; devicetree@vger.kernel.org
Subject: Re: [PATCH 2/2] arm: dts: imx6dl: correct cpufreq volt/freq table

Am Freitag, den 05.12.2014, 16:23 +0800 schrieb Anson Huang:
> Currently the cpufreq volt/freq table we used is for LDO enable mode, 
> according to latest datasheet Rev. 3, 03/2014, the volt/freq table is 
> as below:
> 
> LDO enabled(min value):
> 996MHz: VDDARM: 1.225V, VDDSOC: 1.150V;
> 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V;
> 396MHz: VDDARM: 1.050V, VDDSOC: 1.150V;

From which datasheet is this? I find it unlikely that the LDO enabled values are not larger than the LDO bypassed ones. I just had a look at the "i.MXSolo/6DualLite Automotive and Infotainment Applications Processors" Datasheet (IMX6SDLAEC) Rev. 3, 03/2014 and the "i.MX 6Solo/6DualLite Applications Processors for Consumer Products" Datasheet
(IMX6SDLCEC) Rev. 3, 03/2014, and they both have different values in Table 9 (Operating Ranges) for the LDO enabled case:

LDO enabled(min value):
996MHz: VDDARM: 1.350V, VDDSOC: 1.275V;
792MHz: VDDARM: 1.275V, VDDSOC: 1.275V;
396MHz: VDDARM: 1.175V, VDDSOC: 1.275V;

> LDO bypassed(min value):
> 996MHz: VDDARM: 1.250V, VDDSOC: 1.150V;
> 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V;
> 396MHz: VDDARM: 1.050V, VDDSOC: 1.150V;
> 
> Adding 25mV to cover board IR drop, for LDO enabled mode of 996MHz, 
> VDDARM should be 1.250V, so this patch updates it.
> 
> Signed-off-by: Anson Huang <b20788@freescale.com>

regards
Philipp

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Re: [PATCH 2/2] arm: dts: imx6dl: correct cpufreq volt/freq table

[Philipp Zabel]

On Fri, Dec 05, 2014 at 09:58:15AM +0000, Anson.Huang-KZfg59tc24xl57MIdRCFDg@public.gmane.org wrote:
> Hi, Philipp
> 	The table you listed is VDDARM_IN and VDDSOC_IN which is for external PMIC and we normally do NOT adjust them when cpufreq change, we only adjust the internel LDO output, my table is for VDDARM_CAP and VDDSOC_CAP which are in the comment column, for LDO output.
> 
> For LDO enabled mode, VDDARM/SOC_CAP is the output of LDO, we pass this table to kernel opp.
> For LDO bypassed mode, VDDARM/SOC_IN = VDDARM/SOC_CAP.

Now I feel stupid. Obviously the operating-points' CPU voltages are at the
LDO output and shouldn't change if the LDO is bypassed. Thank you for the
clarification, and sorry for not thinking this through at first. After
looking at the correct column, feel free to consider this change
Reviewed-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>

regards
Philipp
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Re: [PATCH 1/2] arm: dts: imx6q: update cpufreq volt/freq table

[Shawn Guo]

On Fri, Dec 05, 2014 at 04:23:48PM +0800, Anson Huang wrote:
> According to latest i.MX6Q datasheet Rev. 3, 02/2014,
> the latest cpufreq volt/freq table is as below:
> 
> LDO enabled/bypassed(min value):
> 996MHz: VDDARM: 1.225V, VDDSOC: 1.150V;
> 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V;
> 396MHz: VDDARM: 0.925V, VDDSOC: 1.150V;
> 
> the 792MHz setpoint's VDDARM min voltage is updated
> from 1.125V to 1.150V, adding 25mV to cover board IR
> drop, 1.175V is the right voltage we should use.
> 
> Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>

Applied both.

Please use uppercase "ARM: " as patch prefix in the future.

Shawn
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