From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Rutland Subject: Re: [PATCH v3 1/5] rtc: armada38x: Add the device tree binding documentation Date: Thu, 15 Jan 2015 11:39:47 +0000 Message-ID: <20150115113947.GC16217@leverpostej> References: <1421318826-27268-1-git-send-email-gregory.clement@free-electrons.com> <1421318826-27268-2-git-send-email-gregory.clement@free-electrons.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1421318826-27268-2-git-send-email-gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Gregory CLEMENT Cc: Alessandro Zummo , "rtc-linux-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org" , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Arnaud Ebalard , Thomas Petazzoni , Ezequiel Garcia , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , Maxime Ripard , Boris BREZILLON , Lior Amsalem , Tawfik Bayouk , Nadav Haklai , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: devicetree@vger.kernel.org On Thu, Jan 15, 2015 at 10:47:02AM +0000, Gregory CLEMENT wrote: > The Armada 38x SoCs come with a new RTC which differs from the one > used in the other mvebu SoCs until now. This patch describes the > binding of this RTC. > > Signed-off-by: Gregory CLEMENT > --- > .../devicetree/bindings/rtc/armada-380-rtc.txt | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > create mode 100644 Documentation/devicetree/bindings/rtc/armada-380-rtc.txt > > diff --git a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt > new file mode 100644 > index 000000000000..e6fe29bda608 > --- /dev/null > +++ b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt > @@ -0,0 +1,22 @@ > +* Real Time Clock of the Armada 38x SoCs > + > +RTC controller for the Armada 38x SoCs > + > +Required properties: > +- compatible : Should be "marvell,armada-380-rtc" > +- reg: physical base address of the controller and length of memory > + mapped region, associated to the reg-name "rtc". The other entry is > + related to the interrupt control from the SoC, associated to the > + reg-name "soc-int". > +- reg-names: names of the mapped memory regions listed in reg property > + in the same order: "rtc" and "soc-int". It would be nicer if reg were defined in terms of reg-names to avoid redundancy, e.g. - reg: a list of base address and size pairs, one for each entry in reg-names - reg names: should contain: * "rtc" for the RTC registers * "soc-int" for the interrutp control registers. That said, what are the "soc-int" registers, and why does the RTC driver need to poke them? It looks like they're for a separate component (i.e. the interrupt controller). Thanks, Mark. > +- interrupts: IRQ line for the RTC. > + > +Example: > + > +rtc@a3800 { > + compatible = "marvell,armada-380-rtc"; > + reg = <0xa3800 0x20>, <0x184a0 0x0c>; > + reg-names = "rtc", "soc-int"; > + interrupts = ; > +}; > -- > 1.9.1 > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html