From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Walmsley Subject: [PATCH 07/24] Documentation: DT bindings: add more chip compatible strings for Tegra124 pinmux Date: Wed, 28 Jan 2015 16:49:37 -0700 Message-ID: <20150128234937.20644.9760.stgit@dusk.lan> References: <20150128234935.20644.89300.stgit@dusk.lan> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20150128234935.20644.89300.stgit-orwA252wQtA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Mark Rutland , Alexandre Courbot , Pawel Moll , Stephen Warren , Linus Walleij , Ian Campbell , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , Thierry Reding , Paul Walmsley , Kumar Gala , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Sean Paul List-Id: devicetree@vger.kernel.org Add a Tegra132 compatible string to the pinmux IP blocks present on chips similar to Tegra124. The primary objective here is to avoid checkpatch warnings, per: http://marc.info/?l=linux-tegra&m=142201349727836&w=2 Signed-off-by: Paul Walmsley Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Stephen Warren Cc: Thierry Reding Cc: Alexandre Courbot Cc: Sean Paul Cc: Linus Walleij Cc: Paul Walmsley Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org --- .../bindings/pinctrl/nvidia,tegra124-pinmux.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt index 189814e7cdc7..4eb7163a2eb8 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt @@ -7,6 +7,7 @@ a baseline, and only documents the differences between the two bindings. Required properties: - compatible: "nvidia,tegra124-pinmux" + "nvidia,tegra132-pinmux" (not yet matched in the driver) - reg: Should contain a list of base address and size pairs for: -- first entry - the drive strength and pad control registers. -- second entry - the pinmux registers