* [PATCH v9 1/5] Documentation: Add device tree bindings for Freescale i.MX GPC
[not found] ` <1424713215-3357-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
@ 2015-02-23 17:40 ` Philipp Zabel
[not found] ` <1424713215-3357-2-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2015-02-23 17:40 ` [PATCH v9 2/5] ARM: imx6: gpc: Add PU power domain for GPU/VPU Philipp Zabel
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Philipp Zabel @ 2015-02-23 17:40 UTC (permalink / raw)
To: Shawn Guo
Cc: Ulf Hansson, Tomasz Figa, Rob Herring, Mark Rutland,
Geert Uytterhoeven, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
The i.MX6 contains a power controller that controls power gating and
sequencing for the SoC's power domains.
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
Changes since v8:
- Updated example with IRQ_TYPE_... and IMX6QDL_CLK_... defines
---
.../devicetree/bindings/power/fsl,imx-gpc.txt | 59 ++++++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
new file mode 100644
index 0000000..65cc034
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
@@ -0,0 +1,59 @@
+Freescale i.MX General Power Controller
+=======================================
+
+The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
+counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
+domains.
+
+Required properties:
+- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
+- reg: should be register base and length as documented in the
+ datasheet
+- interrupts: Should contain GPC interrupt request 1
+- pu-supply: Link to the LDO regulator powering the PU power domain
+- clocks: Clock phandles to devices in the PU power domain that need
+ to be enabled during domain power-up for reset propagation.
+- #power-domain-cells: Should be 1, see below:
+
+The gpc node is a power-controller as documented by the generic power domain
+bindings in Documentation/devicetree/bindings/power/power_domain.txt.
+
+Example:
+
+ gpc: gpc@020dc000 {
+ compatible = "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
+ <0 90 IRQ_TYPE_LEVEL_HIGH>;
+ pu-supply = <®_pu>;
+ clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+ <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+ <&clks IMX6QDL_CLK_GPU2D_CORE>,
+ <&clks IMX6QDL_CLK_GPU2D_AXI>,
+ <&clks IMX6QDL_CLK_OPENVG_AXI>,
+ <&clks IMX6QDL_CLK_VPU_AXI>;
+ #power-domain-cells = <1>;
+ };
+
+
+Specifying power domain for IP modules
+======================================
+
+IP cores belonging to a power domain should contain a 'power-domains' property
+that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying
+the power domain the device belongs to.
+
+Example of a device that is part of the PU power domain:
+
+ vpu: vpu@02040000 {
+ reg = <0x02040000 0x3c000>;
+ /* ... */
+ power-domains = <&gpc 1>;
+ /* ... */
+ };
+
+The following DOMAIN_INDEX values are valid for i.MX6Q:
+ARM_DOMAIN 0
+PU_DOMAIN 1
+The following additional DOMAIN_INDEX value is valid for i.MX6SL:
+DISPLAY_DOMAIN 2
--
2.1.4
--
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v9 2/5] ARM: imx6: gpc: Add PU power domain for GPU/VPU
[not found] ` <1424713215-3357-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2015-02-23 17:40 ` [PATCH v9 1/5] Documentation: Add device tree bindings for Freescale i.MX GPC Philipp Zabel
@ 2015-02-23 17:40 ` Philipp Zabel
2015-02-23 17:40 ` [PATCH v9 3/5] ARM: dts: imx6qdl: Add power-domain information to gpc node Philipp Zabel
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Philipp Zabel @ 2015-02-23 17:40 UTC (permalink / raw)
To: Shawn Guo
Cc: Ulf Hansson, Tomasz Figa, Rob Herring, Mark Rutland,
Geert Uytterhoeven, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel, Markus Pargmann
When generic pm domain support is enabled, the PGC can be used
to completely gate power to the PU power domain containing GPU3D,
GPU2D, and VPU cores.
This code triggers the PGC powerdown sequence to disable the GPU/VPU
isolation cells and gate power and then disables the PU regulator.
To reenable, the reverse powerup sequence is triggered after the PU
regulator is enabled again.
The GPU and VPU devices in the PU power domain temporarily need
to be clocked during powerup, so that the reset machinery can work.
[Avoid explicit regulator enabling in probe, unless !PM]
Signed-off-by: Markus Pargmann <mpa-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
Changes since v8:
- Made PU regulator optional to support i.MX6SX, suggested by
Robin Gong
- Removed regulator_enable() call in the probe function, stopped
disabling the regulator in imx6q_pm_pu_power_off() - the regulator
framework will disable unused regulators.
- Enable pu power if CONFIG_PM is not enabled, as some bootloaders
disable pu power on boot, causing it to stay always disabled.
---
arch/arm/mach-imx/Kconfig | 1 +
arch/arm/mach-imx/gpc.c | 213 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 214 insertions(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e8627e0..d988d41 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -50,6 +50,7 @@ config HAVE_IMX_ANATOP
config HAVE_IMX_GPC
bool
+ select PM_GENERIC_DOMAINS if PM
config HAVE_IMX_MMDC
bool
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 745caa1..029f59c 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -10,15 +10,25 @@
* http://www.gnu.org/copyleft/gpl.html
*/
+#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/regulator/consumer.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"
+#include "hardware.h"
+#define GPC_CNTR 0x000
#define GPC_IMR1 0x008
+#define GPC_PGC_GPU_PDN 0x260
+#define GPC_PGC_GPU_PUPSCR 0x264
+#define GPC_PGC_GPU_PDNSCR 0x268
#define GPC_PGC_CPU_PDN 0x2a0
#define GPC_PGC_CPU_PUPSCR 0x2a4
#define GPC_PGC_CPU_PDNSCR 0x2a8
@@ -27,6 +37,18 @@
#define IMR_NUM 4
+#define GPU_VPU_PUP_REQ BIT(1)
+#define GPU_VPU_PDN_REQ BIT(0)
+
+#define GPC_CLK_MAX 6
+
+struct pu_domain {
+ struct generic_pm_domain base;
+ struct regulator *reg;
+ struct clk *clk[GPC_CLK_MAX];
+ int num_clks;
+};
+
static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];
@@ -170,3 +192,194 @@ void __init imx_gpc_init(void)
gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
}
+
+#ifdef CONFIG_PM_GENERIC_DOMAINS
+
+static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
+{
+ int iso, iso2sw;
+ u32 val;
+
+ /* Read ISO and ISO2SW power down delays */
+ val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
+ iso = val & 0x3f;
+ iso2sw = (val >> 8) & 0x3f;
+
+ /* Gate off PU domain when GPU/VPU when powered down */
+ writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
+
+ /* Request GPC to power down GPU/VPU */
+ val = readl_relaxed(gpc_base + GPC_CNTR);
+ val |= GPU_VPU_PDN_REQ;
+ writel_relaxed(val, gpc_base + GPC_CNTR);
+
+ /* Wait ISO + ISO2SW IPG clock cycles */
+ ndelay((iso + iso2sw) * 1000 / 66);
+}
+
+static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
+{
+ struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
+
+ _imx6q_pm_pu_power_off(genpd);
+
+ if (pu->reg)
+ regulator_disable(pu->reg);
+
+ return 0;
+}
+
+static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
+{
+ struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
+ int i, ret, sw, sw2iso;
+ u32 val;
+
+ if (pu->reg)
+ ret = regulator_enable(pu->reg);
+ if (pu->reg && ret) {
+ pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* Enable reset clocks for all devices in the PU domain */
+ for (i = 0; i < pu->num_clks; i++)
+ clk_prepare_enable(pu->clk[i]);
+
+ /* Gate off PU domain when GPU/VPU when powered down */
+ writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
+
+ /* Read ISO and ISO2SW power down delays */
+ val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
+ sw = val & 0x3f;
+ sw2iso = (val >> 8) & 0x3f;
+
+ /* Request GPC to power up GPU/VPU */
+ val = readl_relaxed(gpc_base + GPC_CNTR);
+ val |= GPU_VPU_PUP_REQ;
+ writel_relaxed(val, gpc_base + GPC_CNTR);
+
+ /* Wait ISO + ISO2SW IPG clock cycles */
+ ndelay((sw + sw2iso) * 1000 / 66);
+
+ /* Disable reset clocks for all devices in the PU domain */
+ for (i = 0; i < pu->num_clks; i++)
+ clk_disable_unprepare(pu->clk[i]);
+
+ return 0;
+}
+
+static struct generic_pm_domain imx6q_arm_domain = {
+ .name = "ARM",
+};
+
+static struct pu_domain imx6q_pu_domain = {
+ .base = {
+ .name = "PU",
+ .power_off = imx6q_pm_pu_power_off,
+ .power_on = imx6q_pm_pu_power_on,
+ .power_off_latency_ns = 25000,
+ .power_on_latency_ns = 2000000,
+ },
+};
+
+static struct generic_pm_domain imx6sl_display_domain = {
+ .name = "DISPLAY",
+};
+
+static struct generic_pm_domain *imx_gpc_domains[] = {
+ &imx6q_arm_domain,
+ &imx6q_pu_domain.base,
+ &imx6sl_display_domain,
+};
+
+static struct genpd_onecell_data imx_gpc_onecell_data = {
+ .domains = imx_gpc_domains,
+ .num_domains = ARRAY_SIZE(imx_gpc_domains),
+};
+
+static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
+{
+ struct clk *clk;
+ bool is_off;
+ int i;
+
+ imx6q_pu_domain.reg = pu_reg;
+
+ for (i = 0; ; i++) {
+ clk = of_clk_get(dev->of_node, i);
+ if (IS_ERR(clk))
+ break;
+ if (i >= GPC_CLK_MAX) {
+ dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
+ goto clk_err;
+ }
+ imx6q_pu_domain.clk[i] = clk;
+ }
+ imx6q_pu_domain.num_clks = i;
+
+ is_off = IS_ENABLED(CONFIG_PM);
+ if (is_off) {
+ _imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
+ } else {
+ /*
+ * Enable power if compiled without CONFIG_PM in case the
+ * bootloader disabled it.
+ */
+ imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
+ }
+
+ pm_genpd_init(&imx6q_pu_domain.base, NULL, is_off);
+ return of_genpd_add_provider_onecell(dev->of_node,
+ &imx_gpc_onecell_data);
+
+clk_err:
+ while (i--)
+ clk_put(imx6q_pu_domain.clk[i]);
+ return -EINVAL;
+}
+
+#else
+static inline int imx_gpc_genpd_init(struct device *dev, struct regulator *reg)
+{
+ return 0;
+}
+#endif /* CONFIG_PM_GENERIC_DOMAINS */
+
+static int imx_gpc_probe(struct platform_device *pdev)
+{
+ struct regulator *pu_reg;
+ int ret;
+
+ pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
+ if (PTR_ERR(pu_reg) == -ENODEV)
+ pu_reg = NULL;
+ if (IS_ERR(pu_reg)) {
+ ret = PTR_ERR(pu_reg);
+ dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
+ return ret;
+ }
+
+ return imx_gpc_genpd_init(&pdev->dev, pu_reg);
+}
+
+static const struct of_device_id imx_gpc_dt_ids[] = {
+ { .compatible = "fsl,imx6q-gpc" },
+ { .compatible = "fsl,imx6sl-gpc" },
+ { }
+};
+
+static struct platform_driver imx_gpc_driver = {
+ .driver = {
+ .name = "imx-gpc",
+ .owner = THIS_MODULE,
+ .of_match_table = imx_gpc_dt_ids,
+ },
+ .probe = imx_gpc_probe,
+};
+
+static int __init imx_pgc_init(void)
+{
+ return platform_driver_register(&imx_gpc_driver);
+}
+subsys_initcall(imx_pgc_init);
--
2.1.4
--
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v9 3/5] ARM: dts: imx6qdl: Add power-domain information to gpc node
[not found] ` <1424713215-3357-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2015-02-23 17:40 ` [PATCH v9 1/5] Documentation: Add device tree bindings for Freescale i.MX GPC Philipp Zabel
2015-02-23 17:40 ` [PATCH v9 2/5] ARM: imx6: gpc: Add PU power domain for GPU/VPU Philipp Zabel
@ 2015-02-23 17:40 ` Philipp Zabel
2015-02-23 17:40 ` [PATCH v9 4/5] ARM: dts: imx6sl: " Philipp Zabel
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Philipp Zabel @ 2015-02-23 17:40 UTC (permalink / raw)
To: Shawn Guo
Cc: Ulf Hansson, Tomasz Figa, Rob Herring, Mark Rutland,
Geert Uytterhoeven, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework. It needs a phandle to the PU regulator to turn off power when
the domain is disabled, and a list of phandles to all clocks that must be
enabled during powerup for reset propagation.
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/boot/dts/imx6qdl.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index d6c69ec..7ab00a4 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -695,6 +695,14 @@
reg = <0x020dc000 0x4000>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>;
+ pu-supply = <®_pu>;
+ clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+ <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+ <&clks IMX6QDL_CLK_GPU2D_CORE>,
+ <&clks IMX6QDL_CLK_GPU2D_AXI>,
+ <&clks IMX6QDL_CLK_OPENVG_AXI>,
+ <&clks IMX6QDL_CLK_VPU_AXI>;
+ #power-domain-cells = <1>;
};
gpr: iomuxc-gpr@020e0000 {
--
2.1.4
--
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v9 4/5] ARM: dts: imx6sl: Add power-domain information to gpc node
[not found] ` <1424713215-3357-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
` (2 preceding siblings ...)
2015-02-23 17:40 ` [PATCH v9 3/5] ARM: dts: imx6qdl: Add power-domain information to gpc node Philipp Zabel
@ 2015-02-23 17:40 ` Philipp Zabel
2015-02-23 17:40 ` [PATCH v9 5/5] ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp delay Philipp Zabel
2015-03-11 1:12 ` [PATCH v9 0/5] i.MX6 PU power domain support Shawn Guo
5 siblings, 0 replies; 10+ messages in thread
From: Philipp Zabel @ 2015-02-23 17:40 UTC (permalink / raw)
To: Shawn Guo
Cc: Ulf Hansson, Tomasz Figa, Rob Herring, Mark Rutland,
Geert Uytterhoeven, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework. It needs a phandle to the PU regulator to turn off power when
the domain is disabled and a list of clocks to be enabled during powerup
for reset propagation.
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/boot/dts/imx6sl.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e0..79d2007 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -604,6 +604,10 @@
compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
+ pu-supply = <®_pu>;
+ clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
+ <&clks IMX6SL_CLK_GPU2D_PODF>;
+ #power-domain-cells = <1>;
};
gpr: iomuxc-gpr@020e0000 {
--
2.1.4
--
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v9 5/5] ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp delay
[not found] ` <1424713215-3357-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
` (3 preceding siblings ...)
2015-02-23 17:40 ` [PATCH v9 4/5] ARM: dts: imx6sl: " Philipp Zabel
@ 2015-02-23 17:40 ` Philipp Zabel
2015-03-11 1:12 ` [PATCH v9 0/5] i.MX6 PU power domain support Shawn Guo
5 siblings, 0 replies; 10+ messages in thread
From: Philipp Zabel @ 2015-02-23 17:40 UTC (permalink / raw)
To: Shawn Guo
Cc: Ulf Hansson, Tomasz Figa, Rob Herring, Mark Rutland,
Geert Uytterhoeven, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
The PU regulator is enabled during boot, but not necessarily always-on.
It can be disabled by the generic pm domain framework when the PU power
domain is shut down. The ramp delay of 150 us might be a bit conservative,
the value is taken from the Freescale kernel.
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
Changes since v8:
- Removed regulator-boot-on, this depends on the bootloader
---
arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 7ab00a4..4b12ac0 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -598,7 +598,7 @@
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
- regulator-always-on;
+ regulator-enable-ramp-delay = <150>;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
--
2.1.4
--
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^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v9 0/5] i.MX6 PU power domain support
[not found] ` <1424713215-3357-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
` (4 preceding siblings ...)
2015-02-23 17:40 ` [PATCH v9 5/5] ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp delay Philipp Zabel
@ 2015-03-11 1:12 ` Shawn Guo
2015-03-11 9:06 ` Philipp Zabel
5 siblings, 1 reply; 10+ messages in thread
From: Shawn Guo @ 2015-03-11 1:12 UTC (permalink / raw)
To: Philipp Zabel
Cc: Ulf Hansson, Tomasz Figa, Rob Herring, Mark Rutland,
Geert Uytterhoeven, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
On Mon, Feb 23, 2015 at 06:40:10PM +0100, Philipp Zabel wrote:
> Philipp Zabel (6):
> Documentation: Add device tree bindings for Freescale i.MX GPC
> ARM: imx6: gpc: Add PU power domain for GPU/VPU
> ARM: dts: imx6qdl: Add power-domain information to gpc node
> ARM: dts: imx6sl: Add power-domain information to gpc node
> ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp
> delay
Applied above 5.
> ARM: imx6: gpc: Allow PU regulator bypass
I only received 5 patches in the series.
Shawn
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v9 0/5] i.MX6 PU power domain support
2015-03-11 1:12 ` [PATCH v9 0/5] i.MX6 PU power domain support Shawn Guo
@ 2015-03-11 9:06 ` Philipp Zabel
0 siblings, 0 replies; 10+ messages in thread
From: Philipp Zabel @ 2015-03-11 9:06 UTC (permalink / raw)
To: Shawn Guo
Cc: Ulf Hansson, Tomasz Figa, Rob Herring, Mark Rutland,
Geert Uytterhoeven, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hi Shawn,
Am Mittwoch, den 11.03.2015, 09:12 +0800 schrieb Shawn Guo:
> On Mon, Feb 23, 2015 at 06:40:10PM +0100, Philipp Zabel wrote:
> > Philipp Zabel (6):
> > Documentation: Add device tree bindings for Freescale i.MX GPC
> > ARM: imx6: gpc: Add PU power domain for GPU/VPU
> > ARM: dts: imx6qdl: Add power-domain information to gpc node
> > ARM: dts: imx6sl: Add power-domain information to gpc node
> > ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp
> > delay
>
> Applied above 5.
>
> > ARM: imx6: gpc: Allow PU regulator bypass
>
> I only received 5 patches in the series.
Thank you, this shouldn't have appeared in the list at all.
Allowing regulator bypass isn't part of the series because I still
didn't manage to get rid of race conditions when enabling bypass on the
regulator used in two places (gpc and imx6q-cpufreq).
regards
Philipp
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^ permalink raw reply [flat|nested] 10+ messages in thread