[PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes

[PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes

[Ravikumar Kattekola]

Fix bypass clock source for a few DPLLs.

On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected
to a mux and the output from mux is routed to the bypass clkout.
Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents.

Tested against: 
	tree: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git
	branch: master
On:
CPU  : OMAP5432 ES2.0
Board: OMAP5432 uEVM
and
CPU  : DRA752 ES1.0
Board: DRA7xx


Ravikumar Kattekola (2):
  ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others
  ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others

 arch/arm/boot/dts/dra7xx-clocks.dtsi   |   90 ++++++++++++++++++++++++++++----
 arch/arm/boot/dts/omap54xx-clocks.dtsi |   41 +++++++++++++--
 2 files changed, 118 insertions(+), 13 deletions(-)

-- 
1.7.9.5

[PATCH 1/2] ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others

[Ravikumar Kattekola]

Fixes: ee6c750761 (ARM: dts: dra7 clock data)

On DRA7x, For DPLL_IVA, the ref clock(CLKINP) is connected to sys_clk1 and
the bypass input(CLKINPULOW) is connected to iva_dpll_hs_clk_div clock.
But the bypass input is not directly routed to bypass clkout instead
both CLKINP and CLKINPULOW are connected to bypass clkout via a mux.

This mux is controlled by the bit - CM_CLKSEL_DPLL_IVA[23]:DPLL_BYP_CLKSEL
and it's POR value is zero which selects the CLKINP as bypass clkout.
which means iva_dpll_hs_clk_div is not the bypass clock for dpll_iva_ck

Fix this by adding another mux clock as parent in bypass mode.

This design is common to most of the PLLs and the rest have only one bypass
clock. Below is a list of the DPLLs that need this fix:

DPLL_IVA, DPLL_DDR,
DPLL_DSP, DPLL_EVE,
DPLL_GMAC, DPLL_PER,
DPLL_USB and DPLL_CORE

Signed-off-by: Ravikumar Kattekola <rk@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |   90 ++++++++++++++++++++++++++++++----
 1 file changed, 81 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 4bdcbd6..99b09a4 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -243,10 +243,18 @@
 		ti,invert-autoidle-bit;
 	};
 
+	dpll_core_byp_mux: dpll_core_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+		ti,bit-shift = <23>;
+		reg = <0x012c>;
+	};
+
 	dpll_core_ck: dpll_core_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-core-clock";
-		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+		clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
 		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 	};
 
@@ -309,10 +317,18 @@
 		clock-div = <1>;
 	};
 
+	dpll_dsp_byp_mux: dpll_dsp_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+		ti,bit-shift = <23>;
+		reg = <0x0240>;
+	};
+
 	dpll_dsp_ck: dpll_dsp_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+		clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
 		reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
 	};
 
@@ -335,10 +351,18 @@
 		clock-div = <1>;
 	};
 
+	dpll_iva_byp_mux: dpll_iva_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+		ti,bit-shift = <23>;
+		reg = <0x01ac>;
+	};
+
 	dpll_iva_ck: dpll_iva_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+		clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
 		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 	};
 
@@ -361,10 +385,18 @@
 		clock-div = <1>;
 	};
 
+	dpll_gpu_byp_mux: dpll_gpu_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+		ti,bit-shift = <23>;
+		reg = <0x02e4>;
+	};
+
 	dpll_gpu_ck: dpll_gpu_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+		clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
 		reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
 	};
 
@@ -398,10 +430,18 @@
 		clock-div = <1>;
 	};
 
+	dpll_ddr_byp_mux: dpll_ddr_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+		ti,bit-shift = <23>;
+		reg = <0x021c>;
+	};
+
 	dpll_ddr_ck: dpll_ddr_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+		clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
 		reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 	};
 
@@ -416,10 +456,18 @@
 		ti,invert-autoidle-bit;
 	};
 
+	dpll_gmac_byp_mux: dpll_gmac_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+		ti,bit-shift = <23>;
+		reg = <0x02b4>;
+	};
+
 	dpll_gmac_ck: dpll_gmac_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+		clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
 		reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 	};
 
@@ -482,10 +530,18 @@
 		clock-div = <1>;
 	};
 
+	dpll_eve_byp_mux: dpll_eve_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+		ti,bit-shift = <23>;
+		reg = <0x0290>;
+	};
+
 	dpll_eve_ck: dpll_eve_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+		clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
 		reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 	};
 
@@ -1249,10 +1305,18 @@
 		clock-div = <1>;
 	};
 
+	dpll_per_byp_mux: dpll_per_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+		ti,bit-shift = <23>;
+		reg = <0x014c>;
+	};
+
 	dpll_per_ck: dpll_per_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+		clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
 		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
 	};
 
@@ -1275,10 +1339,18 @@
 		clock-div = <1>;
 	};
 
+	dpll_usb_byp_mux: dpll_usb_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+		ti,bit-shift = <23>;
+		reg = <0x018c>;
+	};
+
 	dpll_usb_ck: dpll_usb_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-j-type-clock";
-		clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+		clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
 		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
 	};
 
-- 
1.7.9.5

[PATCH 2/2] ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others

[Ravikumar Kattekola]

Fixes 85dc74e9 (ARM: dts: omap5 clock data)

On OMAP54xx, For DPLL_IVA, the ref clock(CLKINP) is connected to sys_clk1 and
    the bypass input(CLKINPULOW) is connected to iva_dpll_hs_clk_div clock.
    But the bypass input is not directly routed to bypass clkout instead
    both CLKINP and CLKINPULOW are connected to bypass clkout via a mux.

    This mux is controlled by the bit - CM_CLKSEL_DPLL_IVA[23]:DPLL_BYP_CLKSEL
    and it's POR value is zero which selects the CLKINP as bypass clkout.
    which means iva_dpll_hs_clk_div is not the bypass clock for dpll_iva_ck

    Fix this by adding another mux clock as parent in bypass mode.

    This design is common to most of the PLLs and the rest have only one bypass
    clock. Below is a list of the DPLLs that need this fix:

    DPLL_IVA,
    DPLL_PER,
    DPLL_USB and DPLL_CORE

Signed-off-by: Ravikumar Kattekola <rk@ti.com>
---
 arch/arm/boot/dts/omap54xx-clocks.dtsi |   41 ++++++++++++++++++++++++++++----
 1 file changed, 37 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 58c2746..83b425f 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -167,10 +167,18 @@
 		ti,index-starts-at-one;
 	};
 
+	dpll_core_byp_mux: dpll_core_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+		ti,bit-shift = <23>;
+		reg = <0x012c>;
+	};
+
 	dpll_core_ck: dpll_core_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-core-clock";
-		clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+		clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
 		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 	};
 
@@ -294,10 +302,18 @@
 		clock-div = <1>;
 	};
 
+	dpll_iva_byp_mux: dpll_iva_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+		ti,bit-shift = <23>;
+		reg = <0x01ac>;
+	};
+
 	dpll_iva_ck: dpll_iva_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+		clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
 		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 	};
 
@@ -599,10 +615,19 @@
 	};
 };
 &cm_core_clocks {
+
+	dpll_per_byp_mux: dpll_per_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+		ti,bit-shift = <23>;
+		reg = <0x014c>;
+	};
+
 	dpll_per_ck: dpll_per_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
-		clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+		clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
 		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
 	};
 
@@ -714,10 +739,18 @@
 		ti,index-starts-at-one;
 	};
 
+	dpll_usb_byp_mux: dpll_usb_byp_mux {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+		ti,bit-shift = <23>;
+		reg = <0x018c>;
+	};
+
 	dpll_usb_ck: dpll_usb_ck {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-j-type-clock";
-		clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+		clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
 		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
 	};
 
-- 
1.7.9.5

Re: [PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes

[Ravikumar Kattekola]

On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote:
> Fix bypass clock source for a few DPLLs.
>
> On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected
> to a mux and the output from mux is routed to the bypass clkout.
> Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents.
>
> Tested against:
> 	tree: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git
> 	branch: master
> On:
> CPU  : OMAP5432 ES2.0
> Board: OMAP5432 uEVM
> and
> CPU  : DRA752 ES1.0
> Board: DRA7xx
>
>
> Ravikumar Kattekola (2):
>    ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others
>    ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others
>
>   arch/arm/boot/dts/dra7xx-clocks.dtsi   |   90 ++++++++++++++++++++++++++++----
>   arch/arm/boot/dts/omap54xx-clocks.dtsi |   41 +++++++++++++--
>   2 files changed, 118 insertions(+), 13 deletions(-)
>
Hi Benoit,
     Can these fixes be looked into for 3.20-rc?

Regards,
RK

Re: [PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes

[Tony Lindgren]

* Ravikumar Kattekola <rk@ti.com> [150219 08:13]:
> On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote:
> >Fix bypass clock source for a few DPLLs.
> >
> >On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected
> >to a mux and the output from mux is routed to the bypass clkout.
> >Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents.
> >
> >Tested against:
> >	tree: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git
> >	branch: master
> >On:
> >CPU  : OMAP5432 ES2.0
> >Board: OMAP5432 uEVM
> >and
> >CPU  : DRA752 ES1.0
> >Board: DRA7xx
> >
> >
> >Ravikumar Kattekola (2):
> >   ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others
> >   ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others
> >
> >  arch/arm/boot/dts/dra7xx-clocks.dtsi   |   90 ++++++++++++++++++++++++++++----
> >  arch/arm/boot/dts/omap54xx-clocks.dtsi |   41 +++++++++++++--
> >  2 files changed, 118 insertions(+), 13 deletions(-)
> >
> Hi Benoit,
>     Can these fixes be looked into for 3.20-rc?

Seem like valid fixes to me. Tero, care to take a look at these and ack
if OK?

Regards,

Tony

Re: [PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes

[Tero Kristo]

On 02/24/2015 06:27 PM, Tony Lindgren wrote:
> * Ravikumar Kattekola <rk@ti.com> [150219 08:13]:
>> On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote:
>>> Fix bypass clock source for a few DPLLs.
>>>
>>> On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected
>>> to a mux and the output from mux is routed to the bypass clkout.
>>> Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents.
>>>
>>> Tested against:
>>> 	tree: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git
>>> 	branch: master
>>> On:
>>> CPU  : OMAP5432 ES2.0
>>> Board: OMAP5432 uEVM
>>> and
>>> CPU  : DRA752 ES1.0
>>> Board: DRA7xx
>>>
>>>
>>> Ravikumar Kattekola (2):
>>>    ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others
>>>    ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others
>>>
>>>   arch/arm/boot/dts/dra7xx-clocks.dtsi   |   90 ++++++++++++++++++++++++++++----
>>>   arch/arm/boot/dts/omap54xx-clocks.dtsi |   41 +++++++++++++--
>>>   2 files changed, 118 insertions(+), 13 deletions(-)
>>>
>> Hi Benoit,
>>      Can these fixes be looked into for 3.20-rc?
>
> Seem like valid fixes to me. Tero, care to take a look at these and ack
> if OK?

Yes, both are good to go.

Acked-by: Tero Kristo <t-kristo@ti.com>

Re: [PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [150225 00:05]:
> On 02/24/2015 06:27 PM, Tony Lindgren wrote:
> >* Ravikumar Kattekola <rk@ti.com> [150219 08:13]:
> >>On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote:
> >>>Fix bypass clock source for a few DPLLs.
> >>>
> >>>On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected
> >>>to a mux and the output from mux is routed to the bypass clkout.
> >>>Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents.
> >>>
> >>>Tested against:
> >>>	tree: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git
> >>>	branch: master
> >>>On:
> >>>CPU  : OMAP5432 ES2.0
> >>>Board: OMAP5432 uEVM
> >>>and
> >>>CPU  : DRA752 ES1.0
> >>>Board: DRA7xx
> >>>
> >>>
> >>>Ravikumar Kattekola (2):
> >>>   ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others
> >>>   ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others
> >>>
> >>>  arch/arm/boot/dts/dra7xx-clocks.dtsi   |   90 ++++++++++++++++++++++++++++----
> >>>  arch/arm/boot/dts/omap54xx-clocks.dtsi |   41 +++++++++++++--
> >>>  2 files changed, 118 insertions(+), 13 deletions(-)
> >>>
> >>Hi Benoit,
> >>     Can these fixes be looked into for 3.20-rc?
> >
> >Seem like valid fixes to me. Tero, care to take a look at these and ack
> >if OK?
> 
> Yes, both are good to go.
> 
> Acked-by: Tero Kristo <t-kristo@ti.com>

Applying both into omap-for-v4.0/fixes thanks.

Tony