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From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: "Emilio López" <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>,
	"Mike Turquette"
	<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	"Linus Walleij"
	<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	"Rob Herring" <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	"Chen-Yu Tsai" <wens-jdAy2FN1RRM@public.gmane.org>,
	"Vishnu Patekar"
	<vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	"Hans de Goede"
	<hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: Re: [PATCH v2 03/10] clk: sunxi: Let divs clocks read the base factor clock name from devicetree
Date: Tue, 19 May 2015 10:26:35 +0200	[thread overview]
Message-ID: <20150519082635.GW4004@lukather> (raw)
In-Reply-To: <5559AF58.60508-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

[-- Attachment #1: Type: text/plain, Size: 3811 bytes --]

On Mon, May 18, 2015 at 11:22:32AM +0200, Jens Kuske wrote:
> On 05/17/15 15:06, Maxime Ripard wrote:
> > On Fri, May 15, 2015 at 06:38:53PM +0200, Jens Kuske wrote:
> >> Currently, the sunxi clock driver gets the name for the base factor clock
> >> of divs clocks from the name field in factors_data. This prevents reusing
> >> of the factor clock for clocks with same properties, but different name.
> >>
> >> This commit makes the divs setup function try to get a name from
> >> clock-output-names in the devicetree. It also removes the name field where
> >> possible and merges the sun4i PLL5 and PLL6 clocks.
> >>
> >> The sun4i PLL5 clock doesn't have a output for the base factor clock,
> >> so we still have to use the name field there.
> >>
> >> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> >> ---
> >>  drivers/clk/sunxi/clk-sunxi.c | 22 ++++++++++++----------
> >>  1 file changed, 12 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> >> index 17cba4d..afe560c 100644
> >> --- a/drivers/clk/sunxi/clk-sunxi.c
> >> +++ b/drivers/clk/sunxi/clk-sunxi.c
> >> @@ -708,18 +708,10 @@ static const struct factors_data sun4i_pll5_data __initconst = {
> >>  	.name = "pll5",
> >>  };
> >>  
> >> -static const struct factors_data sun4i_pll6_data __initconst = {
> >> -	.enable = 31,
> >> -	.table = &sun4i_pll5_config,
> >> -	.getter = sun4i_get_pll5_factors,
> >> -	.name = "pll6",
> >> -};
> >> -
> >>  static const struct factors_data sun6i_a31_pll6_data __initconst = {
> >>  	.enable = 31,
> >>  	.table = &sun6i_a31_pll6_config,
> >>  	.getter = sun6i_a31_get_pll6_factors,
> >> -	.name = "pll6x2",
> >>  };
> >>  
> >>  static const struct factors_data sun5i_a13_ahb_data __initconst = {
> >> @@ -1099,7 +1091,7 @@ static const struct divs_data pll5_divs_data __initconst = {
> >>  };
> >>  
> >>  static const struct divs_data pll6_divs_data __initconst = {
> >> -	.factors = &sun4i_pll6_data,
> >> +	.factors = &sun4i_pll5_data,
> >>  	.ndivs = 4,
> >>  	.div = {
> >>  		{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
> >> @@ -1141,6 +1133,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
> >>  	struct clk_gate *gate = NULL;
> >>  	struct clk_fixed_factor *fix_factor;
> >>  	struct clk_divider *divider;
> >> +	struct factors_data factors = *data->factors;
> >>  	void __iomem *reg;
> >>  	int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
> >>  	int flags, clkflags;
> >> @@ -1149,8 +1142,17 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
> >>  	if (data->ndivs)
> >>  		ndivs = data->ndivs;
> >>  
> >> +	/* Try to find a name for base factor clock */
> >> +	for (i = 0; i < ndivs; i++) {
> >> +		if (data->div[i].self) {
> > 
> > I'm not sure we should expect the factor clock to have a self factor.
> 
> Maybe not, but in that case it would fall back to the name provided in
> the factors_data struct, as it is the case for sun4i pll5.

Which doesn't really solve the underlying issue, just make it work in
your (pll6/pll8) case.
 
> > what about taking the first output and taking the substring up to the
> > first "_" ?
> 
> That only works for the sun[457]i pll5 & pll6, for sun[68]i the base
> clock name would have to be "pll6x2".

Why?

It's called pll6 in the datasheet, it should really be called
pll6. The fact that there is some fixed factors or dividers on some
children only impacts those children, and not the system as a whole.

And the fact that the "base" clock is pll6x2 and not pll6 itself is
very debatable. How do you know which clock is the base one? Most
clocks are actually using pll6 as a reference.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

  parent reply	other threads:[~2015-05-19  8:26 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-15 16:38 [PATCH v2 00/10] ARM: sunxi: Introduce Allwinner H3 support Jens Kuske
     [not found] ` <1431707940-19372-1-git-send-email-jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-15 16:38   ` [PATCH v2 01/10] Documentation: sunxi: Update Allwinner SoC documentation Jens Kuske
     [not found]     ` <1431707940-19372-2-git-send-email-jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-17 12:52       ` Maxime Ripard
2015-05-15 16:38   ` [PATCH v2 02/10] clk: sunxi: Add support for multiple parents to gates Jens Kuske
     [not found]     ` <1431707940-19372-3-git-send-email-jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-17 12:50       ` Maxime Ripard
2015-05-18  9:11         ` Jens Kuske
     [not found]           ` <5559ACC6.6050202-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-19  7:53             ` Maxime Ripard
2015-05-15 16:38   ` [PATCH v2 03/10] clk: sunxi: Let divs clocks read the base factor clock name from devicetree Jens Kuske
     [not found]     ` <1431707940-19372-4-git-send-email-jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-16  2:10       ` Chen-Yu Tsai
     [not found]         ` <CAGb2v64y8+bdya3N=gK-YEie3A9nVM5nuxRZTVPXYSaN6WzPoQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-18  9:15           ` Jens Kuske
     [not found]             ` <5559ADBE.7060506-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-18 14:45               ` Chen-Yu Tsai
2015-05-17 13:06       ` Maxime Ripard
2015-05-18  9:22         ` Jens Kuske
     [not found]           ` <5559AF58.60508-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-19  8:26             ` Maxime Ripard [this message]
2015-05-15 16:38   ` [PATCH v2 04/10] pinctrl: sunxi: Prepare for building SoC specific drivers as modules Jens Kuske
     [not found]     ` <1431707940-19372-5-git-send-email-jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-17 14:19       ` Maxime Ripard
2015-05-18  9:32         ` Jens Kuske
2015-05-19  7:55           ` Maxime Ripard
2015-05-19  8:02             ` Chen-Yu Tsai
     [not found]               ` <CAGb2v6608XVsxN0f2DEmqmts1zDo223t+fBv46WjGQVQbw7+CA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-19  8:16                 ` Maxime Ripard
2015-05-19 14:58             ` Linus Walleij
2015-05-15 16:38   ` [PATCH v2 05/10] ARM: sunxi: Introduce Allwinner H3 support Jens Kuske
     [not found]     ` <1431707940-19372-6-git-send-email-jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-17 14:21       ` Maxime Ripard
2015-05-15 16:38   ` [PATCH v2 06/10] clk: sunxi: Add H3 clocks support Jens Kuske
     [not found]     ` <1431707940-19372-7-git-send-email-jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-17 14:27       ` Maxime Ripard
2015-05-18  9:45         ` Jens Kuske
     [not found]           ` <5559B4CE.2050703-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-19  8:50             ` Maxime Ripard
2015-05-15 16:38   ` [PATCH v2 07/10] pinctrl: sunxi: Add H3 PIO controller support Jens Kuske
     [not found]     ` <1431707940-19372-8-git-send-email-jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-16 15:32       ` Paul Bolle
2015-05-17 14:30       ` Maxime Ripard
2015-05-18  9:52         ` Jens Kuske
2015-05-19 14:04       ` Linus Walleij
     [not found]         ` <CACRpkdZnWavNK_o04-mNmA0eDV+ppQJz8Kt+-OF5M=jgysuO_g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-05-19 15:03           ` Maxime Ripard
2015-05-15 16:38   ` [PATCH v2 08/10] reset: sunxi: Add compatible for Allwinner H3 bus resets Jens Kuske
     [not found]     ` <1431707940-19372-9-git-send-email-jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-17 14:31       ` Maxime Ripard
2015-05-18  9:55         ` Jens Kuske
2015-05-15 16:38   ` [PATCH v2 09/10] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske
2015-05-15 16:39   ` [PATCH v2 10/10] ARM: dts: sun8i: Add Orange Pi Plus support Jens Kuske

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