From mboxrd@z Thu Jan 1 00:00:00 1970 From: Brian Norris Subject: Re: [PATCH 5/7] mtd: brcmnand: add bcma driver Date: Wed, 20 May 2015 11:40:28 -0700 Message-ID: <20150520184028.GF11598@ld-irv-0074> References: <1431877266-28566-1-git-send-email-hauke@hauke-m.de> <1431877266-28566-6-git-send-email-hauke@hauke-m.de> <20150520003402.GC11598@ld-irv-0074> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= Cc: Hauke Mehrtens , "linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , Ray Jui , bcm-kernel-feedback-list , Florian Fainelli , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: devicetree@vger.kernel.org On Wed, May 20, 2015 at 08:39:06AM +0200, Rafa=C5=82 Mi=C5=82ecki wrote= : > On 20 May 2015 at 02:34, Brian Norris w= rote: > > On Sun, May 17, 2015 at 05:41:04PM +0200, Hauke Mehrtens wrote: > >> This driver registers at the bcma bus and drives the NAND core if = it > >> was found on this bus. The bcma bus with this NAND core is used on= the > >> bcm53xx and bcm47xx Northstar SoC with ARM CPU cores. The memory r= anges > >> are automatically detected by bcma and the irq numbers read from d= evice > >> tree by bcma bus driver. > > > > If you're going to use device tree for part of it (IRQs) why not th= e > > whole thing? > > > >> This is based on the iproc driver. > > > > This looks like you could probably get by with just using iproc_nan= d.c > > as-is. The main NAND core is apparently MMIO-accessible on your chi= ps, > > so aren't the BCMA bits you're touching also? >=20 > That's right, in case of SoCs cores are MMIO-accessible, however I se= e > few reasons for writing this driver as bcma based: > 1) MMIO access isn't available for bcma bus /hosted/ on PCIe devices. > By using bcma layer we write generic drivers. I strongly doubt that this NAND core is ever put on a PCIe endpoint. > 2) bcma detects cores and their MMIO addresses automatically, if we > are a bit lazy, it's easier to use it rather than keep hardcoding all > addresses Laziness is a pretty bad excuse. You already have to do 60% of the work by putting the IRQs and base NAND register range into the device tree. =46inding those remaining two register addresses is not so hard. > 3) There are some dependencies in cores initialization, e.g. > ChipCommon core usually has to be initialized first Are you aware of any important dependencies? Isn't it safe to assume that the ChipCommon core would have to be initialized way before any peripherals? > 4) bcma provides some helpers like bcma_core_enable so we don't have > to duplicate it in driver code I don't see why we need to reset/re-enable the NAND core in the kernel at all, but if we do, this is touching the exact same registers as iproc_nand.c is already. So it makes sense to *share* that code, and do the same thing on both Cygnus and Northstar, etc. (And no, Cygnus can't convert to BCMA, so we can't do 100% sharing either way.) > That said, I'm for using bcma layer, even if there is some small DT > involvement already. =46or any reasons besides the above? Cause I'm still not convinced we n= eed a BCMA driver at all. Brian -- To unsubscribe from this list: send the line "unsubscribe devicetree" i= n the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html