From: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
To: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Joshua Kinard <kumba-aBrp7R+bbdUdnm+yROfE0A@public.gmane.org>,
Leonid Yegoshin
<Leonid.Yegoshin-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>,
Deng-Cheng Zhu
<dengcheng.zhu-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Markos Chandras
<markos.chandras-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>,
Andreas Herrmann
<andreas.herrmann-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
Subject: Re: [PATCH v5 36/37] MIPS: ingenic: initial JZ4780 support
Date: Tue, 26 May 2015 08:25:48 +0100 [thread overview]
Message-ID: <20150526072548.GS13811@NP-P-BURTON> (raw)
In-Reply-To: <5563019A.2050702-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1519 bytes --]
On Mon, May 25, 2015 at 01:03:54PM +0200, Hauke Mehrtens wrote:
> > diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
> > index 1bed3cb..510fc0d 100644
> > --- a/arch/mips/jz4740/setup.c
> > +++ b/arch/mips/jz4740/setup.c
> > @@ -83,6 +83,9 @@ arch_initcall(populate_machine);
> >
> > const char *get_system_type(void)
> > {
> > + if (config_enabled(CONFIG_MACH_JZ4780))
> > + return "JZ4780";
> > +
> > return "JZ4740";
> > }
>
> Shouldn't this be provided by device tree, now it depends on your kernel
> config.
At some point, when the kernel is generic enough that one binary works
across multiple SoCs, yes definitely. Even better might be to detect it
at runtime. The kernel can currently only be built for a single SoC
though, so the code as-is works just fine & gets things working on the
CI20 without making an already lengthy patchset longer than it needs to
be.
> > diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
> > index 9172553..7ab47fe 100644
> > --- a/arch/mips/jz4740/time.c
> > +++ b/arch/mips/jz4740/time.c
> > @@ -102,7 +102,12 @@ static struct clock_event_device jz4740_clockevent = {
> > .set_next_event = jz4740_clockevent_set_next,
> > .set_mode = jz4740_clockevent_set_mode,
> > .rating = 200,
> > +#ifdef CONFIG_MACH_JZ4740
> > .irq = JZ4740_IRQ_TCU0,
> > +#endif
> > +#ifdef CONFIG_MACH_JZ4780
> > + .irq = JZ4780_IRQ_TCU2,
> > +#endif
> > };
>
> same here.
Same response :)
Thanks,
Paul
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next prev parent reply other threads:[~2015-05-26 7:25 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-24 15:11 [PATCH v5 00/37] JZ4780 & CI20 support Paul Burton
2015-05-24 15:11 ` [PATCH v5 01/37] devicetree/bindings: add Ingenic Semiconductor vendor prefix Paul Burton
2015-05-24 15:11 ` [PATCH v5 02/37] devicetree/bindings: add Qi Hardware " Paul Burton
2015-05-24 15:11 ` [PATCH v5 11/37] MIPS: JZ4740: probe interrupt controller via DT Paul Burton
2015-05-24 15:11 ` [PATCH v5 33/37] devicetree: document Ingenic SoC UART binding Paul Burton
2015-05-24 15:11 ` [PATCH v5 36/37] MIPS: ingenic: initial JZ4780 support Paul Burton
[not found] ` <1432480307-23789-37-git-send-email-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
2015-05-25 11:03 ` Hauke Mehrtens
[not found] ` <5563019A.2050702-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
2015-05-26 7:25 ` Paul Burton [this message]
[not found] ` <1432480307-23789-1-git-send-email-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
2015-05-24 15:11 ` [PATCH v5 05/37] MIPS: JZ4740: require & include DT Paul Burton
2015-05-24 15:11 ` [PATCH v5 07/37] MIPS: JZ4740: probe CPU interrupt controller via DT Paul Burton
[not found] ` <1432480307-23789-8-git-send-email-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
2015-05-24 15:17 ` Sergei Shtylyov
[not found] ` <5561EB79.30209-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2015-05-24 22:37 ` [PATCH v6 " Paul Burton
2015-05-24 15:11 ` [PATCH v5 10/37] devicetree: document Ingenic SoC interrupt controller binding Paul Burton
2015-05-24 15:11 ` [PATCH v5 24/37] devicetree: add Ingenic CGU binding documentation Paul Burton
2015-05-24 15:11 ` [PATCH v5 26/37] MIPS,clk: migrate JZ4740 to common clock framework Paul Burton
2015-05-24 15:11 ` [PATCH v5 35/37] MIPS: JZ4740: use Ingenic SoC UART driver Paul Burton
2015-05-24 15:11 ` [PATCH v5 37/37] MIPS: ingenic: initial MIPS Creator CI20 support Paul Burton
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