DeviceTree FPGA bitstream

[Federico Vaga <federico.vaga-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

Hello,

I'm evaluating the DeviceTree to describe the content of an FPGA.
I noticed that Xilinx is already doing it:

https://www.kernel.org/doc/Documentation/devicetree/bindings/xilinx.txt

I admit that I didn't read the code yet, but before doing it I want to
ask you some simple questions that may save me a lot of time.
My questions are:

- is there any reccomandation about DeviceTree for FPGA content description?
If yes, are they documented somewhere?

- it looks like the DeviceTree is disable for x86 architecture except for
some specific platform. Is it possible to enable it for the entire x86
architecture? Are there any reason to disable it by default?

- I read that since versione 3.17 it should be possible to dynamically add
portion of DeviceTree from configfs. Is it possible on all architecture?

- I'm working on x86_64 and my FPGA can be on a pluggable board (e.g. PCIe).
Is there a way to describe this situation with DeviceTree? Is there any tool
that dynamically computes the addresses (interrupts) translation to use
(e.g. on PCIe) ?

Thank you :)
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