* [PATCH v6 01/15] drm/exynos: remove the dependency of DP driver for ARCH_EXYNOS
[not found] ` <1434113958-15877-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
@ 2015-06-12 12:58 ` Hyungwon Hwang
2015-06-12 12:59 ` [PATCH v6 05/15] drm/exynos: add Exynos5433 decon driver Hyungwon Hwang
` (9 subsequent siblings)
10 siblings, 0 replies; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 12:58 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: inki.dae-Sze3O3UU22JBDgjK7y7TUQ, daniel-rLtY4a/8tF1rovVCs/uTlw,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ, Hyungwon Hwang
This dependency is a historical thing. It is added when this DP driver is
under media subsystem. Now because it is under Exynos DRM, this dependency
is not needed anymore.
Signed-off-by: Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
Changes for v6:
- New
drivers/gpu/drm/exynos/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 8203283..926ed36 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -50,7 +50,7 @@ config DRM_EXYNOS_DSI
config DRM_EXYNOS_DP
bool "EXYNOS DRM DP driver support"
- depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON) && ARCH_EXYNOS && (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS)
+ depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON) && (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS)
default DRM_EXYNOS
select DRM_PANEL
help
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v6 05/15] drm/exynos: add Exynos5433 decon driver
[not found] ` <1434113958-15877-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2015-06-12 12:58 ` [PATCH v6 01/15] drm/exynos: remove the dependency of DP driver for ARCH_EXYNOS Hyungwon Hwang
@ 2015-06-12 12:59 ` Hyungwon Hwang
2015-06-12 12:59 ` [PATCH v6 08/15] drm/exynos: dsi: rename pll_clk to sclk_clk Hyungwon Hwang
` (8 subsequent siblings)
10 siblings, 0 replies; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 12:59 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: inki.dae-Sze3O3UU22JBDgjK7y7TUQ, daniel-rLtY4a/8tF1rovVCs/uTlw,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ, Hyungwon Hwang
From: Joonyoung Shim <jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
DECON(Display and Enhancement Controller) is new IP replacing FIMD in
Exynos5433. This patch adds Exynos5433 decon driver.
Signed-off-by: Joonyoung Shim <jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
Changes before:
- Refer https://patchwork.kernel.org/patch/6192071/
Changes for v6:
- Add support for atomic modeset
.../devicetree/bindings/video/exynos5433-decon.txt | 65 ++
drivers/gpu/drm/exynos/Kconfig | 6 +
drivers/gpu/drm/exynos/Makefile | 1 +
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 694 +++++++++++++++++++++
drivers/gpu/drm/exynos/exynos_drm_drv.h | 1 +
include/video/exynos5433_decon.h | 165 +++++
6 files changed, 932 insertions(+)
create mode 100644 Documentation/devicetree/bindings/video/exynos5433-decon.txt
create mode 100644 drivers/gpu/drm/exynos/exynos5433_drm_decon.c
create mode 100644 include/video/exynos5433_decon.h
diff --git a/Documentation/devicetree/bindings/video/exynos5433-decon.txt b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
new file mode 100644
index 0000000..377afbf
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
@@ -0,0 +1,65 @@
+Device-Tree bindings for Samsung Exynos SoC display controller (DECON)
+
+DECON (Display and Enhancement Controller) is the Display Controller for the
+Exynos series of SoCs which transfers the image data from a video memory
+buffer to an external LCD interface.
+
+Required properties:
+- compatible: value should be "samsung,exynos5433-decon";
+- reg: physical base address and length of the DECON registers set.
+- interrupts: should contain a list of all DECON IP block interrupts in the
+ order: VSYNC, LCD_SYSTEM. The interrupt specifier format
+ depends on the interrupt controller used.
+- interrupt-names: should contain the interrupt names: "vsync", "lcd_sys"
+ in the same order as they were listed in the interrupts
+ property.
+- clocks: must include clock specifiers corresponding to entries in the
+ clock-names property.
+- clock-names: list of clock names sorted in the same order as the clocks
+ property. Must contain "aclk_decon", "aclk_smmu_decon0x",
+ "aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",
+ "sclk_decon_eclk"
+- ports: contains a port which is connected to mic node. address-cells and
+ size-cells must 1 and 0, respectively.
+- port: contains an endpoint node which is connected to the endpoint in the mic
+ node. The reg value muset be 0.
+- i80-if-timings: specify whether the panel which is connected to decon uses
+ i80 lcd interface or mipi video interface. This node contains
+ no timing information as that of fimd does. Because there is
+ no register in decon to specify i80 interface timing value,
+ it is not needed, but make it remain to use same kind of node
+ in fimd and exynos7 decon.
+
+Example:
+SoC specific DT entry:
+decon: decon@13800000 {
+ compatible = "samsung,exynos5433-decon";
+ reg = <0x13800000 0x2104>;
+ clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
+ <&cmu_disp CLK_ACLK_XIU_DECON0X>,
+ <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
+ <&cmu_disp CLK_SCLK_DECON_VCLK>,
+ <&cmu_disp CLK_SCLK_DECON_ECLK>;
+ clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x",
+ "pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk";
+ interrupt-names = "vsync", "lcd_sys";
+ interrupts = <0 202 0>, <0 203 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ decon_to_mic: endpoint {
+ remote-endpoint = <&mic_to_decon>;
+ };
+ };
+ };
+};
+
+Board specific DT entry:
+&decon {
+ i80-if-timings {
+ };
+};
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index ddb7c8a..51a4eb5 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -24,6 +24,12 @@ config DRM_EXYNOS_FIMD
help
Choose this option if you want to use Exynos FIMD for DRM.
+config DRM_EXYNOS5433_DECON
+ bool "Exynos5433 DRM DECON"
+ depends on DRM_EXYNOS
+ help
+ Choose this option if you want to use Exynos5433 DECON for DRM.
+
config DRM_EXYNOS7_DECON
bool "Exynos7 DRM DECON"
depends on DRM_EXYNOS && !FB_S3C
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index cc90679..fbd084d 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -10,6 +10,7 @@ exynosdrm-y := exynos_drm_drv.o exynos_drm_encoder.o \
exynosdrm-$(CONFIG_DRM_EXYNOS_IOMMU) += exynos_drm_iommu.o
exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD) += exynos_drm_fimd.o
+exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON) += exynos5433_drm_decon.o
exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON) += exynos7_drm_decon.o
exynosdrm-$(CONFIG_DRM_EXYNOS_DPI) += exynos_drm_dpi.o
exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
new file mode 100644
index 0000000..a33c0b7
--- /dev/null
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -0,0 +1,694 @@
+/* drivers/gpu/drm/exynos5433_drm_decon.c
+ *
+ * Copyright (C) 2015 Samsung Electronics Co.Ltd
+ * Authors:
+ * Joonyoung Shim <jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ * Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundationr
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_gpio.h>
+
+#include <video/exynos5433_decon.h>
+
+#include "exynos_drm_drv.h"
+#include "exynos_drm_crtc.h"
+#include "exynos_drm_plane.h"
+#include "exynos_drm_iommu.h"
+
+#define WINDOWS_NR 3
+#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
+
+struct decon_context {
+ struct device *dev;
+ struct drm_device *drm_dev;
+ struct exynos_drm_crtc *crtc;
+ struct exynos_drm_plane planes[WINDOWS_NR];
+ void __iomem *addr;
+ struct clk *clks[6];
+ unsigned int default_win;
+ int pipe;
+ bool suspended;
+
+#define BIT_CLKS_ENABLED 0
+#define BIT_IRQS_ENABLED 1
+ unsigned long enabled;
+ bool i80_if;
+ atomic_t win_updated;
+};
+
+static const char * const decon_clks_name[] = {
+ "aclk_decon",
+ "aclk_smmu_decon0x",
+ "aclk_xiu_decon0x",
+ "pclk_smmu_decon0x",
+ "sclk_decon_vclk",
+ "sclk_decon_eclk",
+};
+
+static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
+{
+ struct decon_context *ctx = crtc->ctx;
+ u32 val;
+
+ if (ctx->suspended)
+ return -EPERM;
+
+ if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->enabled)) {
+ val = VIDINTCON0_INTEN;
+ if (ctx->i80_if)
+ val |= VIDINTCON0_FRAMEDONE;
+ else
+ val |= VIDINTCON0_INTFRMEN;
+
+ writel(val, ctx->addr + DECON_VIDINTCON0);
+ }
+
+ return 0;
+}
+
+static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
+{
+ struct decon_context *ctx = crtc->ctx;
+
+ if (ctx->suspended)
+ return;
+
+ if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->enabled))
+ writel(0, ctx->addr + DECON_VIDINTCON0);
+}
+
+static void decon_setup_trigger(struct decon_context *ctx)
+{
+ u32 val = TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
+ TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN;
+ writel(val, ctx->addr + DECON_TRIGCON);
+}
+
+static void decon_commit(struct exynos_drm_crtc *crtc)
+{
+ struct decon_context *ctx = crtc->ctx;
+ struct drm_display_mode *mode = &crtc->base.mode;
+ u32 val;
+
+ if (ctx->suspended)
+ return;
+
+ /* enable clock gate */
+ val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
+ writel(val, ctx->addr + DECON_CMU);
+
+ /* lcd on and use command if */
+ val = VIDOUT_LCD_ON;
+ if (ctx->i80_if)
+ val |= VIDOUT_COMMAND_IF;
+ else
+ val |= VIDOUT_RGB_IF;
+ writel(val, ctx->addr + DECON_VIDOUTCON0);
+
+ val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
+ VIDTCON2_HOZVAL(mode->hdisplay - 1);
+ writel(val, ctx->addr + DECON_VIDTCON2);
+
+ if (!ctx->i80_if) {
+ val = VIDTCON00_VBPD_F(
+ mode->crtc_vtotal - mode->crtc_vsync_end) |
+ VIDTCON00_VFPD_F(
+ mode->crtc_vsync_start - mode->crtc_vdisplay);
+ writel(val, ctx->addr + DECON_VIDTCON00);
+
+ val = VIDTCON01_VSPW_F(
+ mode->crtc_vsync_end - mode->crtc_vsync_start);
+ writel(val, ctx->addr + DECON_VIDTCON01);
+
+ val = VIDTCON10_HBPD_F(
+ mode->crtc_htotal - mode->crtc_hsync_end) |
+ VIDTCON10_HFPD_F(
+ mode->crtc_hsync_start - mode->crtc_hdisplay);
+ writel(val, ctx->addr + DECON_VIDTCON10);
+
+ val = VIDTCON11_HSPW_F(
+ mode->crtc_hsync_end - mode->crtc_hsync_start);
+ writel(val, ctx->addr + DECON_VIDTCON11);
+ }
+
+ decon_setup_trigger(ctx);
+
+ /* enable output and display signal */
+ val = VIDCON0_ENVID | VIDCON0_ENVID_F;
+ writel(val, ctx->addr + DECON_VIDCON0);
+}
+
+#define COORDINATE_X(x) (((x) & 0xfff) << 12)
+#define COORDINATE_Y(x) ((x) & 0xfff)
+#define OFFSIZE(x) (((x) & 0x3fff) << 14)
+#define PAGEWIDTH(x) ((x) & 0x3fff)
+
+static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win)
+{
+ struct exynos_drm_plane *plane = &ctx->planes[win];
+ unsigned long val;
+
+ val = readl(ctx->addr + DECON_WINCONx(win));
+ val &= ~WINCONx_BPPMODE_MASK;
+
+ switch (plane->pixel_format) {
+ case DRM_FORMAT_XRGB1555:
+ val |= WINCONx_BPPMODE_16BPP_I1555;
+ val |= WINCONx_HAWSWP_F;
+ val |= WINCONx_BURSTLEN_16WORD;
+ break;
+ case DRM_FORMAT_RGB565:
+ val |= WINCONx_BPPMODE_16BPP_565;
+ val |= WINCONx_HAWSWP_F;
+ val |= WINCONx_BURSTLEN_16WORD;
+ break;
+ case DRM_FORMAT_XRGB8888:
+ val |= WINCONx_BPPMODE_24BPP_888;
+ val |= WINCONx_WSWP_F;
+ val |= WINCONx_BURSTLEN_16WORD;
+ break;
+ case DRM_FORMAT_ARGB8888:
+ val |= WINCONx_BPPMODE_32BPP_A8888;
+ val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
+ val |= WINCONx_BURSTLEN_16WORD;
+ break;
+ default:
+ DRM_ERROR("Proper pixel format is not set\n");
+ return;
+ }
+
+ DRM_DEBUG_KMS("bpp = %u\n", plane->bpp);
+
+ /*
+ * In case of exynos, setting dma-burst to 16Word causes permanent
+ * tearing for very small buffers, e.g. cursor buffer. Burst Mode
+ * switching which is based on plane size is not recommended as
+ * plane size varies a lot towards the end of the screen and rapid
+ * movement causes unstable DMA which results into iommu crash/tear.
+ */
+
+ if (plane->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
+ val &= ~WINCONx_BURSTLEN_MASK;
+ val |= WINCONx_BURSTLEN_8WORD;
+ }
+
+ writel(val, ctx->addr + DECON_WINCONx(win));
+}
+
+static void decon_shadow_protect_win(struct decon_context *ctx, int win,
+ bool protect)
+{
+ u32 val;
+
+ val = readl(ctx->addr + DECON_SHADOWCON);
+
+ if (protect)
+ val |= SHADOWCON_Wx_PROTECT(win);
+ else
+ val &= ~SHADOWCON_Wx_PROTECT(win);
+
+ writel(val, ctx->addr + DECON_SHADOWCON);
+}
+
+static void decon_win_commit(struct exynos_drm_crtc *crtc, unsigned int win)
+{
+ struct decon_context *ctx = crtc->ctx;
+ struct exynos_drm_plane *plane;
+ u32 val;
+
+ if (win < 0 || win >= WINDOWS_NR)
+ return;
+
+ plane = &ctx->planes[win];
+
+ /* If suspended, enable this on resume */
+ if (ctx->suspended) {
+ plane->resume = true;
+ return;
+ }
+
+ decon_shadow_protect_win(ctx, win, true);
+
+ val = COORDINATE_X(plane->crtc_x) | COORDINATE_Y(plane->crtc_y);
+ writel(val, ctx->addr + DECON_VIDOSDxA(win));
+
+ val = COORDINATE_X(plane->crtc_x + plane->crtc_width - 1) |
+ COORDINATE_Y(plane->crtc_y + plane->crtc_height - 1);
+ writel(val, ctx->addr + DECON_VIDOSDxB(win));
+
+ val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
+ VIDOSD_Wx_ALPHA_B_F(0x0);
+ writel(val, ctx->addr + DECON_VIDOSDxC(win));
+
+ val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
+ VIDOSD_Wx_ALPHA_B_F(0x0);
+ writel(val, ctx->addr + DECON_VIDOSDxD(win));
+
+ writel(plane->dma_addr[0], ctx->addr + DECON_VIDW0xADD0B0(win));
+
+ val = plane->dma_addr[0] + plane->pitch * plane->crtc_height;
+ writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
+
+ val = OFFSIZE(plane->pitch - plane->crtc_width * (plane->bpp >> 3))
+ | PAGEWIDTH(plane->crtc_width * (plane->bpp >> 3));
+ writel(val, ctx->addr + DECON_VIDW0xADD2(win));
+
+ decon_win_set_pixfmt(ctx, win);
+
+ /* window enable */
+ val = readl(ctx->addr + DECON_WINCONx(win));
+ val |= WINCONx_ENWIN_F;
+ writel(val, ctx->addr + DECON_WINCONx(win));
+
+ decon_shadow_protect_win(ctx, win, false);
+
+ /* standalone update */
+ val = readl(ctx->addr + DECON_UPDATE);
+ val |= STANDALONE_UPDATE_F;
+ writel(val, ctx->addr + DECON_UPDATE);
+
+ if (ctx->i80_if)
+ atomic_set(&ctx->win_updated, 1);
+
+ plane->enabled = true;
+}
+
+static void decon_win_disable(struct exynos_drm_crtc *crtc, unsigned int win)
+{
+ struct decon_context *ctx = crtc->ctx;
+ struct exynos_drm_plane *plane;
+ u32 val;
+
+ if (win < 0 || win >= WINDOWS_NR)
+ return;
+
+ plane = &ctx->planes[win];
+
+ if (ctx->suspended) {
+ plane->resume = false;
+ return;
+ }
+
+ decon_shadow_protect_win(ctx, win, true);
+
+ /* window disable */
+ val = readl(ctx->addr + DECON_WINCONx(win));
+ val &= ~WINCONx_ENWIN_F;
+ writel(val, ctx->addr + DECON_WINCONx(win));
+
+ decon_shadow_protect_win(ctx, win, false);
+
+ /* standalone update */
+ val = readl(ctx->addr + DECON_UPDATE);
+ val |= STANDALONE_UPDATE_F;
+ writel(val, ctx->addr + DECON_UPDATE);
+
+ plane->enabled = false;
+}
+
+static void decon_window_suspend(struct decon_context *ctx)
+{
+ struct exynos_drm_plane *plane;
+ int i;
+
+ for (i = 0; i < WINDOWS_NR; i++) {
+ plane = &ctx->planes[i];
+ plane->resume = plane->enabled;
+ if (plane->enabled)
+ decon_win_disable(ctx->crtc, i);
+ }
+}
+
+static void decon_window_resume(struct decon_context *ctx)
+{
+ struct exynos_drm_plane *plane;
+ int i;
+
+ for (i = 0; i < WINDOWS_NR; i++) {
+ plane = &ctx->planes[i];
+ plane->enabled = plane->resume;
+ plane->resume = false;
+ }
+}
+
+static void decon_apply(struct decon_context *ctx)
+{
+ struct exynos_drm_plane *plane;
+ int i;
+
+ decon_setup_trigger(ctx);
+
+ for (i = 0; i < WINDOWS_NR; i++) {
+ plane = &ctx->planes[i];
+ if (plane->enabled)
+ decon_win_commit(ctx->crtc, i);
+ else
+ decon_win_disable(ctx->crtc, i);
+ }
+
+ decon_commit(ctx->crtc);
+}
+
+static void decon_enable(struct exynos_drm_crtc *crtc)
+{
+ struct decon_context *ctx = crtc->ctx;
+ int ret;
+ int i;
+
+ if (!ctx->suspended)
+ return;
+
+ ctx->suspended = false;
+
+ for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
+ ret = clk_prepare_enable(ctx->clks[i]);
+ if (ret < 0)
+ goto err;
+ }
+
+ set_bit(BIT_CLKS_ENABLED, &ctx->enabled);
+
+ decon_window_resume(ctx);
+ decon_apply(ctx);
+
+ return;
+err:
+ while (--i >= 0)
+ clk_disable_unprepare(ctx->clks[i]);
+
+ ctx->suspended = true;
+}
+
+static void decon_swreset(struct decon_context *ctx)
+{
+ unsigned int tries;
+
+ writel(0, ctx->addr + DECON_VIDCON0);
+ for (tries = 2000; tries; --tries) {
+ if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
+ break;
+ udelay(10);
+ }
+
+ WARN(tries == 0, "failed to disable DECON\n");
+
+ writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
+ for (tries = 2000; tries; --tries) {
+ if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
+ break;
+ udelay(10);
+ }
+
+ WARN(tries == 0, "failed to software reset DECON\n");
+}
+
+static void decon_disable(struct exynos_drm_crtc *crtc)
+{
+ struct decon_context *ctx = crtc->ctx;
+ int i;
+
+ if (ctx->suspended)
+ return;
+
+ clear_bit(BIT_CLKS_ENABLED, &ctx->enabled);
+ decon_window_suspend(ctx);
+ decon_swreset(ctx);
+
+ for (i = ARRAY_SIZE(decon_clks_name) - 1; i >= 0; i--)
+ clk_disable_unprepare(ctx->clks[i]);
+
+ ctx->suspended = true;
+}
+
+void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
+{
+ struct decon_context *ctx = crtc->ctx;
+ u32 val;
+
+ if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled))
+ return;
+
+ if (atomic_add_unless(&ctx->win_updated, -1, 0)) {
+ /* trigger */
+ val = readl(ctx->addr + DECON_TRIGCON);
+ val |= TRIGCON_SWTRIGCMD;
+ writel(val, ctx->addr + DECON_TRIGCON);
+ }
+
+ drm_handle_vblank(ctx->drm_dev, ctx->pipe);
+}
+
+static void decon_clear_channels(struct exynos_drm_crtc *crtc)
+{
+ struct decon_context *ctx = crtc->ctx;
+ int win, i, ret;
+ u32 val;
+
+ DRM_DEBUG_KMS("%s\n", __FILE__);
+
+ for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
+ ret = clk_prepare_enable(ctx->clks[i]);
+ if (ret < 0)
+ goto err;
+ }
+
+ for (win = 0; win < WINDOWS_NR; win++) {
+ /* shadow update disable */
+ val = readl(ctx->addr + DECON_SHADOWCON);
+ val |= SHADOWCON_Wx_PROTECT(win);
+ writel(val, ctx->addr + DECON_SHADOWCON);
+
+ /* window disable */
+ val = readl(ctx->addr + DECON_WINCONx(win));
+ val &= ~WINCONx_ENWIN_F;
+ writel(val, ctx->addr + DECON_WINCONx(win));
+
+ /* shadow update enable */
+ val = readl(ctx->addr + DECON_SHADOWCON);
+ val &= ~SHADOWCON_Wx_PROTECT(win);
+ writel(val, ctx->addr + DECON_SHADOWCON);
+
+ /* standalone update */
+ val = readl(ctx->addr + DECON_UPDATE);
+ val |= STANDALONE_UPDATE_F;
+ writel(val, ctx->addr + DECON_UPDATE);
+ }
+ /* TODO: wait for possible vsync */
+ msleep(50);
+
+err:
+ while (--i >= 0)
+ clk_disable_unprepare(ctx->clks[i]);
+}
+
+static struct exynos_drm_crtc_ops decon_crtc_ops = {
+ .enable = decon_enable,
+ .disable = decon_disable,
+ .commit = decon_commit,
+ .enable_vblank = decon_enable_vblank,
+ .disable_vblank = decon_disable_vblank,
+ .commit = decon_commit,
+ .win_commit = decon_win_commit,
+ .win_disable = decon_win_disable,
+ .te_handler = decon_te_irq_handler,
+ .clear_channels = decon_clear_channels,
+};
+
+static int decon_bind(struct device *dev, struct device *master, void *data)
+{
+ struct decon_context *ctx = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ struct exynos_drm_private *priv = drm_dev->dev_private;
+ struct exynos_drm_plane *exynos_plane;
+ enum drm_plane_type type;
+ unsigned int zpos;
+ int ret;
+
+ ctx->drm_dev = drm_dev;
+ ctx->pipe = priv->pipe++;
+
+ for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
+ type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
+ DRM_PLANE_TYPE_OVERLAY;
+ ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
+ 1 << ctx->pipe, type, zpos);
+ if (ret)
+ return ret;
+ }
+
+ exynos_plane = &ctx->planes[ctx->default_win];
+ ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
+ ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
+ &decon_crtc_ops, ctx);
+ if (IS_ERR(ctx->crtc)) {
+ ret = PTR_ERR(ctx->crtc);
+ goto err;
+ }
+
+ ret = drm_iommu_attach_device_if_possible(ctx->crtc, drm_dev, dev);
+ if (ret)
+ goto err;
+
+ return ret;
+err:
+ priv->pipe--;
+ return ret;
+}
+
+static void decon_unbind(struct device *dev, struct device *master, void *data)
+{
+ struct decon_context *ctx = dev_get_drvdata(dev);
+
+ decon_disable(ctx->crtc);
+
+ /* detach this sub driver from iommu mapping if supported. */
+ if (is_drm_iommu_supported(ctx->drm_dev))
+ drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
+}
+
+static const struct component_ops decon_component_ops = {
+ .bind = decon_bind,
+ .unbind = decon_unbind,
+};
+
+static irqreturn_t decon_vsync_irq_handler(int irq, void *dev_id)
+{
+ struct decon_context *ctx = dev_id;
+ u32 val;
+
+ if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled))
+ goto out;
+
+ val = readl(ctx->addr + DECON_VIDINTCON1);
+ if (val & VIDINTCON1_INTFRMPEND) {
+ drm_handle_vblank(ctx->drm_dev, ctx->pipe);
+
+ /* clear */
+ writel(VIDINTCON1_INTFRMPEND, ctx->addr + DECON_VIDINTCON1);
+ }
+
+out:
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t decon_lcd_sys_irq_handler(int irq, void *dev_id)
+{
+ struct decon_context *ctx = dev_id;
+ u32 val;
+
+ if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled))
+ goto out;
+
+ val = readl(ctx->addr + DECON_VIDINTCON1);
+ if (val & VIDINTCON1_INTFRMDONEPEND) {
+ exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
+
+ /* clear */
+ writel(VIDINTCON1_INTFRMDONEPEND,
+ ctx->addr + DECON_VIDINTCON1);
+ }
+
+out:
+ return IRQ_HANDLED;
+}
+
+static int exynos5433_decon_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct decon_context *ctx;
+ struct resource *res;
+ int ret;
+ int i;
+
+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ ctx->default_win = 0;
+ ctx->suspended = true;
+ ctx->dev = dev;
+ if (of_get_child_by_name(dev->of_node, "i80-if-timings"))
+ ctx->i80_if = true;
+
+ for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
+ struct clk *clk;
+
+ clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ ctx->clks[i] = clk;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "cannot find IO resource\n");
+ return -ENXIO;
+ }
+
+ ctx->addr = devm_ioremap_resource(dev, res);
+ if (IS_ERR(ctx->addr)) {
+ dev_err(dev, "ioremap failed\n");
+ return PTR_ERR(ctx->addr);
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
+ ctx->i80_if ? "lcd_sys" : "vsync");
+ if (!res) {
+ dev_err(dev, "cannot find IRQ resource\n");
+ return -ENXIO;
+ }
+
+ ret = devm_request_irq(dev, res->start, ctx->i80_if ?
+ decon_lcd_sys_irq_handler : decon_vsync_irq_handler, 0,
+ "drm_decon", ctx);
+ if (ret < 0) {
+ dev_err(dev, "lcd_sys irq request failed\n");
+ return ret;
+ }
+
+ ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
+ EXYNOS_DISPLAY_TYPE_LCD);
+ if (ret < 0)
+ return ret;
+
+ platform_set_drvdata(pdev, ctx);
+
+ ret = component_add(dev, &decon_component_ops);
+ if (ret < 0) {
+ exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int exynos5433_decon_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &decon_component_ops);
+ exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
+
+ return 0;
+}
+
+static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
+ { .compatible = "samsung,exynos5433-decon" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
+
+struct platform_driver exynos5433_decon_driver = {
+ .probe = exynos5433_decon_probe,
+ .remove = exynos5433_decon_remove,
+ .driver = {
+ .name = "exynos5433-decon",
+ .of_match_table = exynos5433_decon_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 1ba34f1..769edfd 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -306,6 +306,7 @@ int exynos_drm_create_enc_conn(struct drm_device *dev,
struct exynos_drm_display *display);
extern struct platform_driver fimd_driver;
+extern struct platform_driver exynos5433_decon_driver;
extern struct platform_driver decon_driver;
extern struct platform_driver dp_driver;
extern struct platform_driver dsi_driver;
diff --git a/include/video/exynos5433_decon.h b/include/video/exynos5433_decon.h
new file mode 100644
index 0000000..3696575
--- /dev/null
+++ b/include/video/exynos5433_decon.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics Co.Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundationr
+ */
+
+#ifndef EXYNOS_REGS_DECON_H
+#define EXYNOS_REGS_DECON_H
+
+/* Exynos543X DECON */
+#define DECON_VIDCON0 0x0000
+#define DECON_VIDOUTCON0 0x0010
+#define DECON_WINCONx(n) (0x0020 + ((n) * 4))
+#define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4))
+#define DECON_SHADOWCON 0x00A0
+#define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20))
+#define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20))
+#define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20))
+#define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20))
+#define DECON_VIDOSDxE(n) (0x00C0 + ((n) * 0x20))
+#define DECON_VIDW0xADD0B0(n) (0x0150 + ((n) * 0x10))
+#define DECON_VIDW0xADD0B1(n) (0x0154 + ((n) * 0x10))
+#define DECON_VIDW0xADD0B2(n) (0x0158 + ((n) * 0x10))
+#define DECON_VIDW0xADD1B0(n) (0x01A0 + ((n) * 0x10))
+#define DECON_VIDW0xADD1B1(n) (0x01A4 + ((n) * 0x10))
+#define DECON_VIDW0xADD1B2(n) (0x01A8 + ((n) * 0x10))
+#define DECON_VIDW0xADD2(n) (0x0200 + ((n) * 4))
+#define DECON_LOCALxSIZE(n) (0x0214 + ((n) * 4))
+#define DECON_VIDINTCON0 0x0220
+#define DECON_VIDINTCON1 0x0224
+#define DECON_WxKEYCON0(n) (0x0230 + ((n - 1) * 8))
+#define DECON_WxKEYCON1(n) (0x0234 + ((n - 1) * 8))
+#define DECON_WxKEYALPHA(n) (0x0250 + ((n - 1) * 4))
+#define DECON_WINxMAP(n) (0x0270 + ((n) * 4))
+#define DECON_QOSLUT07_00 0x02C0
+#define DECON_QOSLUT15_08 0x02C4
+#define DECON_QOSCTRL 0x02C8
+#define DECON_BLENDERQx(n) (0x0300 + ((n - 1) * 4))
+#define DECON_BLENDCON 0x0310
+#define DECON_OPE_VIDW0xADD0(n) (0x0400 + ((n) * 4))
+#define DECON_OPE_VIDW0xADD1(n) (0x0414 + ((n) * 4))
+#define DECON_FRAMEFIFO_REG7 0x051C
+#define DECON_FRAMEFIFO_REG8 0x0520
+#define DECON_FRAMEFIFO_STATUS 0x0524
+#define DECON_CMU 0x1404
+#define DECON_UPDATE 0x1410
+#define DECON_UPDATE_SCHEME 0x1438
+#define DECON_VIDCON1 0x2000
+#define DECON_VIDCON2 0x2004
+#define DECON_VIDCON3 0x2008
+#define DECON_VIDCON4 0x200C
+#define DECON_VIDTCON2 0x2028
+#define DECON_FRAME_SIZE 0x2038
+#define DECON_LINECNT_OP_THRESHOLD 0x203C
+#define DECON_TRIGCON 0x2040
+#define DECON_TRIGSKIP 0x2050
+#define DECON_CRCRDATA 0x20B0
+#define DECON_CRCCTRL 0x20B4
+
+/* Exynos5430 DECON */
+#define DECON_VIDTCON0 0x2020
+#define DECON_VIDTCON1 0x2024
+
+/* Exynos5433 DECON */
+#define DECON_VIDTCON00 0x2010
+#define DECON_VIDTCON01 0x2014
+#define DECON_VIDTCON10 0x2018
+#define DECON_VIDTCON11 0x201C
+
+/* Exynos543X DECON Internal */
+#define DECON_W013DSTREOCON 0x0320
+#define DECON_W233DSTREOCON 0x0324
+#define DECON_FRAMEFIFO_REG0 0x0500
+#define DECON_ENHANCER_CTRL 0x2100
+
+/* Exynos543X DECON TV */
+#define DECON_VCLKCON0 0x0014
+#define DECON_VIDINTCON2 0x0228
+#define DECON_VIDINTCON3 0x022C
+
+/* VIDCON0 */
+#define VIDCON0_SWRESET (1 << 28)
+#define VIDCON0_STOP_STATUS (1 << 2)
+#define VIDCON0_ENVID (1 << 1)
+#define VIDCON0_ENVID_F (1 << 0)
+
+/* VIDOUTCON0 */
+#define VIDOUT_LCD_ON (1 << 24)
+#define VIDOUT_IF_F_MASK (0x3 << 20)
+#define VIDOUT_RGB_IF (0x0 << 20)
+#define VIDOUT_COMMAND_IF (0x2 << 20)
+
+/* WINCONx */
+#define WINCONx_HAWSWP_F (1 << 16)
+#define WINCONx_WSWP_F (1 << 15)
+#define WINCONx_BURSTLEN_MASK (0x3 << 10)
+#define WINCONx_BURSTLEN_16WORD (0x0 << 10)
+#define WINCONx_BURSTLEN_8WORD (0x1 << 10)
+#define WINCONx_BURSTLEN_4WORD (0x2 << 10)
+#define WINCONx_BLD_PIX_F (1 << 6)
+#define WINCONx_BPPMODE_MASK (0xf << 2)
+#define WINCONx_BPPMODE_16BPP_565 (0x5 << 2)
+#define WINCONx_BPPMODE_16BPP_A1555 (0x6 << 2)
+#define WINCONx_BPPMODE_16BPP_I1555 (0x7 << 2)
+#define WINCONx_BPPMODE_24BPP_888 (0xb << 2)
+#define WINCONx_BPPMODE_24BPP_A1887 (0xc << 2)
+#define WINCONx_BPPMODE_25BPP_A1888 (0xd << 2)
+#define WINCONx_BPPMODE_32BPP_A8888 (0xd << 2)
+#define WINCONx_BPPMODE_16BPP_A4444 (0xe << 2)
+#define WINCONx_ALPHA_SEL_F (1 << 1)
+#define WINCONx_ENWIN_F (1 << 0)
+
+/* SHADOWCON */
+#define SHADOWCON_Wx_PROTECT(n) (1 << (10 + (n)))
+
+/* VIDOSDxD */
+#define VIDOSD_Wx_ALPHA_R_F(n) (((n) & 0xff) << 16)
+#define VIDOSD_Wx_ALPHA_G_F(n) (((n) & 0xff) << 8)
+#define VIDOSD_Wx_ALPHA_B_F(n) (((n) & 0xff) << 0)
+
+/* VIDINTCON0 */
+#define VIDINTCON0_FRAMEDONE (1 << 17)
+#define VIDINTCON0_INTFRMEN (1 << 12)
+#define VIDINTCON0_INTEN (1 << 0)
+
+/* VIDINTCON1 */
+#define VIDINTCON1_INTFRMDONEPEND (1 << 2)
+#define VIDINTCON1_INTFRMPEND (1 << 1)
+#define VIDINTCON1_INTFIFOPEND (1 << 0)
+
+/* DECON_CMU */
+#define CMU_CLKGAGE_MODE_SFR_F (1 << 1)
+#define CMU_CLKGAGE_MODE_MEM_F (1 << 0)
+
+/* DECON_UPDATE */
+#define STANDALONE_UPDATE_F (1 << 0)
+
+/* DECON_VIDTCON00 */
+#define VIDTCON00_VBPD_F(x) (((x) & 0xfff) << 16)
+#define VIDTCON00_VFPD_F(x) ((x) & 0xfff)
+
+/* DECON_VIDTCON01 */
+#define VIDTCON01_VSPW_F(x) (((x) & 0xfff) << 16)
+
+/* DECON_VIDTCON10 */
+#define VIDTCON10_HBPD_F(x) (((x) & 0xfff) << 16)
+#define VIDTCON10_HFPD_F(x) ((x) & 0xfff)
+
+/* DECON_VIDTCON11 */
+#define VIDTCON11_HSPW_F(x) (((x) & 0xfff) << 16)
+
+/* DECON_VIDTCON2 */
+#define VIDTCON2_LINEVAL(x) (((x) & 0xfff) << 16)
+#define VIDTCON2_HOZVAL(x) ((x) & 0xfff)
+
+/* TRIGCON */
+#define TRIGCON_TRIGEN_PER_F (1 << 31)
+#define TRIGCON_TRIGEN_F (1 << 30)
+#define TRIGCON_TE_AUTO_MASK (1 << 29)
+#define TRIGCON_SWTRIGCMD (1 << 1)
+#define TRIGCON_SWTRIGEN (1 << 0)
+
+#endif /* EXYNOS_REGS_DECON_H */
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v6 08/15] drm/exynos: dsi: rename pll_clk to sclk_clk
[not found] ` <1434113958-15877-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2015-06-12 12:58 ` [PATCH v6 01/15] drm/exynos: remove the dependency of DP driver for ARCH_EXYNOS Hyungwon Hwang
2015-06-12 12:59 ` [PATCH v6 05/15] drm/exynos: add Exynos5433 decon driver Hyungwon Hwang
@ 2015-06-12 12:59 ` Hyungwon Hwang
2015-06-22 12:25 ` Inki Dae
2015-06-12 12:59 ` [PATCH v6 09/15] drm/exynos: dsi: add macros for register access Hyungwon Hwang
` (7 subsequent siblings)
10 siblings, 1 reply; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 12:59 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: inki.dae-Sze3O3UU22JBDgjK7y7TUQ, daniel-rLtY4a/8tF1rovVCs/uTlw,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ, Hyungwon Hwang
This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk
is actually not the pll input clock for dsi. The pll input clock comes
from the board's oscillator directly. But for the backward
compatibility, the old clock name "pll_clk" is also OK.
Signed-off-by: Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
Changes before:
- Refer https://patchwork.kernel.org/patch/6191721
Changes for v6:
- Merged 2 patches
drm/exynos: dsi: add the backward compatibility for the renamed clock
drm/exynos: dsi: rename pll_clk to sclk_clk
.../devicetree/bindings/video/exynos_dsim.txt | 7 +++--
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 36 ++++++++++------------
2 files changed, 20 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt
index 802aa7e..44659dd 100644
--- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -10,13 +10,14 @@ Required properties:
- interrupts: should contain DSI interrupt
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- - clock-names: should include "bus_clk"and "pll_clk" entries
+ - clock-names: should include "bus_clk"and "sclk_mipi" entries
+ the use of "pll_clk" is deprecated
- phys: list of phy specifiers, must contain an entry for each required
entry in phy-names
- phy-names: should include "dsim" entry
- vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
- vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
- - samsung,pll-clock-frequency: specifies frequency of the "pll_clk" clock
+ - samsung,pll-clock-frequency: specifies frequency of the oscillator clock
- #address-cells, #size-cells: should be set respectively to <1> and <0>
according to DSI host bindings (see MIPI DSI bindings [1])
@@ -48,7 +49,7 @@ Example:
reg = <0x11C80000 0x10000>;
interrupts = <0 79 0>;
clocks = <&clock 286>, <&clock 143>;
- clock-names = "bus_clk", "pll_clk";
+ clock-names = "bus_clk", "sclk_mipi";
phys = <&mipi_phy 1>;
phy-names = "dsim";
vddcore-supply = <&vusb_reg>;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index c1999ad..a3bfac2 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -235,6 +235,8 @@
#define DSI_XFER_TIMEOUT_MS 100
#define DSI_RX_FIFO_EMPTY 0x30800002
+#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
+
enum exynos_dsi_transfer_type {
EXYNOS_DSI_TX,
EXYNOS_DSI_RX,
@@ -279,7 +281,7 @@ struct exynos_dsi {
void __iomem *reg_base;
struct phy *phy;
- struct clk *pll_clk;
+ struct clk *sclk_clk;
struct clk *bus_clk;
struct regulator_bulk_data supplies[2];
int irq;
@@ -433,16 +435,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
u16 m;
u32 reg;
- clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate);
-
- fin = clk_get_rate(dsi->pll_clk);
- if (!fin) {
- dev_err(dsi->dev, "failed to get PLL clock frequency\n");
- return 0;
- }
-
- dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin);
-
+ fin = dsi->pll_clk_rate;
fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
if (!fout) {
dev_err(dsi->dev,
@@ -1313,10 +1306,10 @@ static int exynos_dsi_poweron(struct exynos_dsi *dsi)
goto err_bus_clk;
}
- ret = clk_prepare_enable(dsi->pll_clk);
+ ret = clk_prepare_enable(dsi->sclk_clk);
if (ret < 0) {
dev_err(dsi->dev, "cannot enable pll clock %d\n", ret);
- goto err_pll_clk;
+ goto err_sclk_clk;
}
ret = phy_power_on(dsi->phy);
@@ -1328,8 +1321,8 @@ static int exynos_dsi_poweron(struct exynos_dsi *dsi)
return 0;
err_phy:
- clk_disable_unprepare(dsi->pll_clk);
-err_pll_clk:
+ clk_disable_unprepare(dsi->sclk_clk);
+err_sclk_clk:
clk_disable_unprepare(dsi->bus_clk);
err_bus_clk:
regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
@@ -1355,7 +1348,7 @@ static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
phy_power_off(dsi->phy);
- clk_disable_unprepare(dsi->pll_clk);
+ clk_disable_unprepare(dsi->sclk_clk);
clk_disable_unprepare(dsi->bus_clk);
ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
@@ -1722,10 +1715,13 @@ static int exynos_dsi_probe(struct platform_device *pdev)
return -EPROBE_DEFER;
}
- dsi->pll_clk = devm_clk_get(dev, "pll_clk");
- if (IS_ERR(dsi->pll_clk)) {
- dev_info(dev, "failed to get dsi pll input clock\n");
- return PTR_ERR(dsi->pll_clk);
+ dsi->sclk_clk = devm_clk_get(dev, "sclk_mipi");
+ if (IS_ERR(dsi->sclk_clk)) {
+ dsi->sclk_clk = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
+ if (IS_ERR(dsi->sclk_clk)) {
+ dev_info(dev, "failed to get dsi sclk clock\n");
+ eturn PTR_ERR(dsi->sclk_clk);
+ }
}
dsi->bus_clk = devm_clk_get(dev, "bus_clk");
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v6 08/15] drm/exynos: dsi: rename pll_clk to sclk_clk
2015-06-12 12:59 ` [PATCH v6 08/15] drm/exynos: dsi: rename pll_clk to sclk_clk Hyungwon Hwang
@ 2015-06-22 12:25 ` Inki Dae
0 siblings, 0 replies; 41+ messages in thread
From: Inki Dae @ 2015-06-22 12:25 UTC (permalink / raw)
To: Hyungwon Hwang
Cc: devicetree, linux-samsung-soc@vger.kernel.org, sw0312.kim,
dri-devel
+ Samsung SoC mailing list.
On 2015년 06월 12일 21:59, Hyungwon Hwang wrote:
> This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk
> is actually not the pll input clock for dsi. The pll input clock comes
> from the board's oscillator directly. But for the backward
> compatibility, the old clock name "pll_clk" is also OK.
>
> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
> ---
> Changes before:
> - Refer https://patchwork.kernel.org/patch/6191721
> Changes for v6:
> - Merged 2 patches
> drm/exynos: dsi: add the backward compatibility for the renamed clock
> drm/exynos: dsi: rename pll_clk to sclk_clk
>
> .../devicetree/bindings/video/exynos_dsim.txt | 7 +++--
> drivers/gpu/drm/exynos/exynos_drm_dsi.c | 36 ++++++++++------------
> 2 files changed, 20 insertions(+), 23 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt
> index 802aa7e..44659dd 100644
> --- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
> +++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
> @@ -10,13 +10,14 @@ Required properties:
> - interrupts: should contain DSI interrupt
> - clocks: list of clock specifiers, must contain an entry for each required
> entry in clock-names
> - - clock-names: should include "bus_clk"and "pll_clk" entries
> + - clock-names: should include "bus_clk"and "sclk_mipi" entries
> + the use of "pll_clk" is deprecated
> - phys: list of phy specifiers, must contain an entry for each required
> entry in phy-names
> - phy-names: should include "dsim" entry
> - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
> - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
> - - samsung,pll-clock-frequency: specifies frequency of the "pll_clk" clock
> + - samsung,pll-clock-frequency: specifies frequency of the oscillator clock
> - #address-cells, #size-cells: should be set respectively to <1> and <0>
> according to DSI host bindings (see MIPI DSI bindings [1])
>
> @@ -48,7 +49,7 @@ Example:
> reg = <0x11C80000 0x10000>;
> interrupts = <0 79 0>;
> clocks = <&clock 286>, <&clock 143>;
> - clock-names = "bus_clk", "pll_clk";
> + clock-names = "bus_clk", "sclk_mipi";
> phys = <&mipi_phy 1>;
> phy-names = "dsim";
> vddcore-supply = <&vusb_reg>;
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> index c1999ad..a3bfac2 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> @@ -235,6 +235,8 @@
> #define DSI_XFER_TIMEOUT_MS 100
> #define DSI_RX_FIFO_EMPTY 0x30800002
>
> +#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
> +
> enum exynos_dsi_transfer_type {
> EXYNOS_DSI_TX,
> EXYNOS_DSI_RX,
> @@ -279,7 +281,7 @@ struct exynos_dsi {
>
> void __iomem *reg_base;
> struct phy *phy;
> - struct clk *pll_clk;
> + struct clk *sclk_clk;
> struct clk *bus_clk;
> struct regulator_bulk_data supplies[2];
> int irq;
> @@ -433,16 +435,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
> u16 m;
> u32 reg;
>
> - clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate);
> -
> - fin = clk_get_rate(dsi->pll_clk);
> - if (!fin) {
> - dev_err(dsi->dev, "failed to get PLL clock frequency\n");
> - return 0;
> - }
> -
> - dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin);
> -
> + fin = dsi->pll_clk_rate;
> fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
> if (!fout) {
> dev_err(dsi->dev,
> @@ -1313,10 +1306,10 @@ static int exynos_dsi_poweron(struct exynos_dsi *dsi)
> goto err_bus_clk;
> }
>
> - ret = clk_prepare_enable(dsi->pll_clk);
> + ret = clk_prepare_enable(dsi->sclk_clk);
> if (ret < 0) {
> dev_err(dsi->dev, "cannot enable pll clock %d\n", ret);
> - goto err_pll_clk;
> + goto err_sclk_clk;
> }
>
> ret = phy_power_on(dsi->phy);
> @@ -1328,8 +1321,8 @@ static int exynos_dsi_poweron(struct exynos_dsi *dsi)
> return 0;
>
> err_phy:
> - clk_disable_unprepare(dsi->pll_clk);
> -err_pll_clk:
> + clk_disable_unprepare(dsi->sclk_clk);
> +err_sclk_clk:
> clk_disable_unprepare(dsi->bus_clk);
> err_bus_clk:
> regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
> @@ -1355,7 +1348,7 @@ static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
>
> phy_power_off(dsi->phy);
>
> - clk_disable_unprepare(dsi->pll_clk);
> + clk_disable_unprepare(dsi->sclk_clk);
> clk_disable_unprepare(dsi->bus_clk);
>
> ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
> @@ -1722,10 +1715,13 @@ static int exynos_dsi_probe(struct platform_device *pdev)
> return -EPROBE_DEFER;
> }
>
> - dsi->pll_clk = devm_clk_get(dev, "pll_clk");
> - if (IS_ERR(dsi->pll_clk)) {
> - dev_info(dev, "failed to get dsi pll input clock\n");
> - return PTR_ERR(dsi->pll_clk);
> + dsi->sclk_clk = devm_clk_get(dev, "sclk_mipi");
> + if (IS_ERR(dsi->sclk_clk)) {
> + dsi->sclk_clk = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
> + if (IS_ERR(dsi->sclk_clk)) {
> + dev_info(dev, "failed to get dsi sclk clock\n");
> + eturn PTR_ERR(dsi->sclk_clk);
> + }
> }
>
> dsi->bus_clk = devm_clk_get(dev, "bus_clk");
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v6 09/15] drm/exynos: dsi: add macros for register access
[not found] ` <1434113958-15877-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
` (2 preceding siblings ...)
2015-06-12 12:59 ` [PATCH v6 08/15] drm/exynos: dsi: rename pll_clk to sclk_clk Hyungwon Hwang
@ 2015-06-12 12:59 ` Hyungwon Hwang
2015-06-12 12:59 ` [PATCH v6 10/15] drm/exynos: dsi: make use of driver data for static values Hyungwon Hwang
` (6 subsequent siblings)
10 siblings, 0 replies; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 12:59 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: inki.dae-Sze3O3UU22JBDgjK7y7TUQ, daniel-rLtY4a/8tF1rovVCs/uTlw,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ, Hyungwon Hwang
This patch adds macros for register writing/reading. This is needed for
adding support Exynos5433 MIPI DSI driver, not by using if statement, but
by using driver data.
Signed-off-by: Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
Changes before:
- Refer https://patchwork.kernel.org/patch/6191761
Changes for v6:
- None
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 98 +++++++++++++++++----------------
1 file changed, 51 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index a3bfac2..70367d0 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -237,6 +237,9 @@
#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
+#define DSI_WRITE(dsi, reg, val) writel((val), (dsi)->reg_base + (reg))
+#define DSI_READ(dsi, reg) readl((dsi)->reg_base + (reg))
+
enum exynos_dsi_transfer_type {
EXYNOS_DSI_TX,
EXYNOS_DSI_RX,
@@ -365,8 +368,10 @@ static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
static void exynos_dsi_reset(struct exynos_dsi *dsi)
{
+ struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
+
reinit_completion(&dsi->completed);
- writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG);
+ DSI_WRITE(dsi, DSIM_SWRST_REG, DSIM_SWRST);
}
#ifndef MHZ
@@ -376,6 +381,7 @@ static void exynos_dsi_reset(struct exynos_dsi *dsi)
static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
{
+ struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
unsigned long best_freq = 0;
u32 min_delta = 0xffffffff;
u8 p_min, p_max;
@@ -466,7 +472,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
reg |= DSIM_FREQ_BAND(band);
}
- writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
+ DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg);
timeout = 1000;
do {
@@ -474,7 +480,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
dev_err(dsi->dev, "PLL failed to stabilize\n");
return 0;
}
- reg = readl(dsi->reg_base + DSIM_STATUS_REG);
+ reg = DSI_READ(dsi, DSIM_STATUS_REG);
} while ((reg & DSIM_PLL_STABLE) == 0);
return fout;
@@ -504,7 +510,7 @@ static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
hs_clk, byte_clk, esc_clk);
- reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
+ reg = DSI_READ(dsi, DSIM_CLKCTRL_REG);
reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
| DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
| DSIM_BYTE_CLK_SRC_MASK);
@@ -514,7 +520,7 @@ static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
| DSIM_BYTE_CLK_SRC(0)
| DSIM_TX_REQUEST_HSCLK;
- writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
+ DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg);
return 0;
}
@@ -529,7 +535,7 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
/* B D-PHY: D-PHY Master & Slave Analog Block control */
reg = DSIM_PHYCTRL_ULPS_EXIT(0x0af);
- writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG);
+ DSI_WRITE(dsi, DSIM_PHYCTRL_REG, reg);
/*
* T LPX: Transmitted length of any Low-Power state period
@@ -537,7 +543,7 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
* burst
*/
reg = DSIM_PHYTIMING_LPX(0x06) | DSIM_PHYTIMING_HS_EXIT(0x0b);
- writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG);
+ DSI_WRITE(dsi, DSIM_PHYTIMING_REG, reg);
/*
* T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
@@ -556,7 +562,7 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
DSIM_PHYTIMING1_CLK_ZERO(0x27) |
DSIM_PHYTIMING1_CLK_POST(0x0d) |
DSIM_PHYTIMING1_CLK_TRAIL(0x08);
- writel(reg, dsi->reg_base + DSIM_PHYTIMING1_REG);
+ DSI_WRITE(dsi, DSIM_PHYTIMING1_REG, reg);
/*
* T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
@@ -569,21 +575,21 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
*/
reg = DSIM_PHYTIMING2_HS_PREPARE(0x09) | DSIM_PHYTIMING2_HS_ZERO(0x0d) |
DSIM_PHYTIMING2_HS_TRAIL(0x0b);
- writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG);
+ DSI_WRITE(dsi, DSIM_PHYTIMING2_REG, reg);
}
static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
{
u32 reg;
- reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
+ reg = DSI_READ(dsi, DSIM_CLKCTRL_REG);
reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
| DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
- writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
+ DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg);
- reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG);
+ reg = DSI_READ(dsi, DSIM_PLLCTRL_REG);
reg &= ~DSIM_PLL_EN;
- writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
+ DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg);
}
static int exynos_dsi_init_link(struct exynos_dsi *dsi)
@@ -594,15 +600,14 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
u32 lanes_mask;
/* Initialize FIFO pointers */
- reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
+ reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG);
reg &= ~0x1f;
- writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
+ DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg);
usleep_range(9000, 11000);
reg |= 0x1f;
- writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
-
+ DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg);
usleep_range(9000, 11000);
/* DSI configuration */
@@ -661,14 +666,14 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1);
- writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
+ DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
reg |= DSIM_LANE_EN_CLK;
- writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
+ DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
lanes_mask = BIT(dsi->lanes) - 1;
reg |= DSIM_LANE_EN(lanes_mask);
- writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
+ DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
/*
* Use non-continuous clock mode if the periparal wants and
@@ -681,7 +686,7 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
if (driver_data->has_clklane_stop &&
dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
reg |= DSIM_CLKLANE_STOP;
- writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
+ DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
}
/* Check clock and data lane state are stop state */
@@ -692,19 +697,19 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
return -EFAULT;
}
- reg = readl(dsi->reg_base + DSIM_STATUS_REG);
+ reg = DSI_READ(dsi, DSIM_STATUS_REG);
if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
!= DSIM_STOP_STATE_DAT(lanes_mask))
continue;
} while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
- reg = readl(dsi->reg_base + DSIM_ESCMODE_REG);
+ reg = DSI_READ(dsi, DSIM_ESCMODE_REG);
reg &= ~DSIM_STOP_STATE_CNT_MASK;
reg |= DSIM_STOP_STATE_CNT(0xf);
- writel(reg, dsi->reg_base + DSIM_ESCMODE_REG);
+ DSI_WRITE(dsi, DSIM_ESCMODE_REG, reg);
reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
- writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG);
+ DSI_WRITE(dsi, DSIM_TIMEOUT_REG, reg);
return 0;
}
@@ -718,19 +723,19 @@ static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
reg = DSIM_CMD_ALLOW(0xf)
| DSIM_STABLE_VFP(vm->vfront_porch)
| DSIM_MAIN_VBP(vm->vback_porch);
- writel(reg, dsi->reg_base + DSIM_MVPORCH_REG);
+ DSI_WRITE(dsi, DSIM_MVPORCH_REG, reg);
reg = DSIM_MAIN_HFP(vm->hfront_porch)
| DSIM_MAIN_HBP(vm->hback_porch);
- writel(reg, dsi->reg_base + DSIM_MHPORCH_REG);
+ DSI_WRITE(dsi, DSIM_MHPORCH_REG, reg);
reg = DSIM_MAIN_VSA(vm->vsync_len)
| DSIM_MAIN_HSA(vm->hsync_len);
- writel(reg, dsi->reg_base + DSIM_MSYNC_REG);
+ DSI_WRITE(dsi, DSIM_MSYNC_REG, reg);
}
reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive);
- writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
+ DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg);
dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
}
@@ -739,12 +744,12 @@ static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
{
u32 reg;
- reg = readl(dsi->reg_base + DSIM_MDRESOL_REG);
+ reg = DSI_READ(dsi, DSIM_MDRESOL_REG);
if (enable)
reg |= DSIM_MAIN_STAND_BY;
else
reg &= ~DSIM_MAIN_STAND_BY;
- writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
+ DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg);
}
static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
@@ -752,7 +757,7 @@ static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
int timeout = 2000;
do {
- u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
+ u32 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG);
if (!(reg & DSIM_SFR_HEADER_FULL))
return 0;
@@ -766,22 +771,21 @@ static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
{
- u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
+ u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG);
if (lpm)
v |= DSIM_CMD_LPDT_LP;
else
v &= ~DSIM_CMD_LPDT_LP;
- writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
+ DSI_WRITE(dsi, DSIM_ESCMODE_REG, v);
}
static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
{
- u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
-
+ u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG);
v |= DSIM_FORCE_BTA;
- writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
+ DSI_WRITE(dsi, DSIM_ESCMODE_REG, v);
}
static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
@@ -805,7 +809,7 @@ static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
while (length >= 4) {
reg = (payload[3] << 24) | (payload[2] << 16)
| (payload[1] << 8) | payload[0];
- writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
+ DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg);
payload += 4;
length -= 4;
}
@@ -820,7 +824,7 @@ static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
/* Fall through */
case 1:
reg |= payload[0];
- writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
+ DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg);
break;
case 0:
/* Do nothing */
@@ -843,7 +847,7 @@ static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
dsi->state ^= DSIM_STATE_CMD_LPM;
}
- writel(reg, dsi->reg_base + DSIM_PKTHDR_REG);
+ DSI_WRITE(dsi, DSIM_PKTHDR_REG, reg);
if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
exynos_dsi_force_bta(dsi);
@@ -859,7 +863,7 @@ static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
u32 reg;
if (first) {
- reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
+ reg = DSI_READ(dsi, DSIM_RXFIFO_REG);
switch (reg & 0x3f) {
case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
@@ -898,7 +902,7 @@ static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
/* Receive payload */
while (length >= 4) {
- reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
+ reg = DSI_READ(dsi, DSIM_RXFIFO_REG);
payload[0] = (reg >> 0) & 0xff;
payload[1] = (reg >> 8) & 0xff;
payload[2] = (reg >> 16) & 0xff;
@@ -908,7 +912,7 @@ static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
}
if (length) {
- reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
+ reg = DSI_READ(dsi, DSIM_RXFIFO_REG);
switch (length) {
case 3:
payload[2] = (reg >> 16) & 0xff;
@@ -927,7 +931,7 @@ static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
clear_fifo:
length = DSI_RX_FIFO_SIZE / 4;
do {
- reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
+ reg = DSI_READ(dsi, DSIM_RXFIFO_REG);
if (reg == DSI_RX_FIFO_EMPTY)
break;
} while (--length);
@@ -1083,18 +1087,18 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
struct exynos_dsi *dsi = dev_id;
u32 status;
- status = readl(dsi->reg_base + DSIM_INTSRC_REG);
+ status = DSI_READ(dsi, DSIM_INTSRC_REG);
if (!status) {
static unsigned long int j;
if (printk_timed_ratelimit(&j, 500))
dev_warn(dsi->dev, "spurious interrupt\n");
return IRQ_HANDLED;
}
- writel(status, dsi->reg_base + DSIM_INTSRC_REG);
+ DSI_WRITE(dsi, DSIM_INTSRC_REG, status);
if (status & DSIM_INT_SW_RST_RELEASE) {
u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY);
- writel(mask, dsi->reg_base + DSIM_INTMSK_REG);
+ DSI_WRITE(dsi, DSIM_INTMSK_REG, mask);
complete(&dsi->completed);
return IRQ_HANDLED;
}
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v6 10/15] drm/exynos: dsi: make use of driver data for static values
[not found] ` <1434113958-15877-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
` (3 preceding siblings ...)
2015-06-12 12:59 ` [PATCH v6 09/15] drm/exynos: dsi: add macros for register access Hyungwon Hwang
@ 2015-06-12 12:59 ` Hyungwon Hwang
2015-06-12 12:59 ` [PATCH v6 11/15] drm/exynos: dsi: make use of array for clock access Hyungwon Hwang
` (5 subsequent siblings)
10 siblings, 0 replies; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 12:59 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: inki.dae-Sze3O3UU22JBDgjK7y7TUQ, daniel-rLtY4a/8tF1rovVCs/uTlw,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ, Hyungwon Hwang
Exynos MIPI DSI driver uses some static values such as address offsets,
register setting values, and etc. This patch makes the driver get those
values from the driver data.
Signed-off-by: Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
Changes before:
- Refer https://patchwork.kernel.org/patch/6191731
Changes for v6:
- None
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 196 +++++++++++++++++++++++---------
1 file changed, 145 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 70367d0..0b468d7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -34,38 +34,6 @@
/* returns true iff both arguments logically differs */
#define NEQV(a, b) (!(a) ^ !(b))
-#define DSIM_STATUS_REG 0x0 /* Status register */
-#define DSIM_SWRST_REG 0x4 /* Software reset register */
-#define DSIM_CLKCTRL_REG 0x8 /* Clock control register */
-#define DSIM_TIMEOUT_REG 0xc /* Time out register */
-#define DSIM_CONFIG_REG 0x10 /* Configuration register */
-#define DSIM_ESCMODE_REG 0x14 /* Escape mode register */
-
-/* Main display image resolution register */
-#define DSIM_MDRESOL_REG 0x18
-#define DSIM_MVPORCH_REG 0x1c /* Main display Vporch register */
-#define DSIM_MHPORCH_REG 0x20 /* Main display Hporch register */
-#define DSIM_MSYNC_REG 0x24 /* Main display sync area register */
-
-/* Sub display image resolution register */
-#define DSIM_SDRESOL_REG 0x28
-#define DSIM_INTSRC_REG 0x2c /* Interrupt source register */
-#define DSIM_INTMSK_REG 0x30 /* Interrupt mask register */
-#define DSIM_PKTHDR_REG 0x34 /* Packet Header FIFO register */
-#define DSIM_PAYLOAD_REG 0x38 /* Payload FIFO register */
-#define DSIM_RXFIFO_REG 0x3c /* Read FIFO register */
-#define DSIM_FIFOTHLD_REG 0x40 /* FIFO threshold level register */
-#define DSIM_FIFOCTRL_REG 0x44 /* FIFO status and control register */
-
-/* FIFO memory AC characteristic register */
-#define DSIM_PLLCTRL_REG 0x4c /* PLL control register */
-#define DSIM_PHYACCHR_REG 0x54 /* D-PHY AC characteristic register */
-#define DSIM_PHYACCHR1_REG 0x58 /* D-PHY AC characteristic register1 */
-#define DSIM_PHYCTRL_REG 0x5c
-#define DSIM_PHYTIMING_REG 0x64
-#define DSIM_PHYTIMING1_REG 0x68
-#define DSIM_PHYTIMING2_REG 0x6c
-
/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
#define DSIM_STOP_STATE_CLK (1 << 8)
@@ -129,8 +97,8 @@
/* DSIM_MDRESOL */
#define DSIM_MAIN_STAND_BY (1 << 31)
-#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
-#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
+#define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
+#define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
/* DSIM_MVPORCH */
#define DSIM_CMD_ALLOW(x) ((x) << 28)
@@ -237,8 +205,11 @@
#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
-#define DSI_WRITE(dsi, reg, val) writel((val), (dsi)->reg_base + (reg))
-#define DSI_READ(dsi, reg) readl((dsi)->reg_base + (reg))
+#define REG_ADDR(dsi, reg_idx) ((dsi)->reg_base + \
+ dsi->driver_data->reg_ofs[(reg_idx)])
+#define DSI_WRITE(dsi, reg_idx, val) writel((val), \
+ REG_ADDR((dsi), (reg_idx)))
+#define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx)))
enum exynos_dsi_transfer_type {
EXYNOS_DSI_TX,
@@ -268,10 +239,15 @@ struct exynos_dsi_transfer {
#define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
struct exynos_dsi_driver_data {
+ unsigned int *reg_ofs;
unsigned int plltmr_reg;
-
unsigned int has_freqband:1;
unsigned int has_clklane_stop:1;
+ unsigned int num_clks;
+ unsigned int max_freq;
+ unsigned int wait_for_reset;
+ unsigned int num_bits_resol;
+ unsigned int *reg_values;
};
struct exynos_dsi {
@@ -316,25 +292,133 @@ static inline struct exynos_dsi *display_to_dsi(struct exynos_drm_display *d)
return container_of(d, struct exynos_dsi, display);
}
+enum reg_idx {
+ DSIM_STATUS_REG, /* Status register */
+ DSIM_SWRST_REG, /* Software reset register */
+ DSIM_CLKCTRL_REG, /* Clock control register */
+ DSIM_TIMEOUT_REG, /* Time out register */
+ DSIM_CONFIG_REG, /* Configuration register */
+ DSIM_ESCMODE_REG, /* Escape mode register */
+ DSIM_MDRESOL_REG,
+ DSIM_MVPORCH_REG, /* Main display Vporch register */
+ DSIM_MHPORCH_REG, /* Main display Hporch register */
+ DSIM_MSYNC_REG, /* Main display sync area register */
+ DSIM_INTSRC_REG, /* Interrupt source register */
+ DSIM_INTMSK_REG, /* Interrupt mask register */
+ DSIM_PKTHDR_REG, /* Packet Header FIFO register */
+ DSIM_PAYLOAD_REG, /* Payload FIFO register */
+ DSIM_RXFIFO_REG, /* Read FIFO register */
+ DSIM_FIFOCTRL_REG, /* FIFO status and control register */
+ DSIM_PLLCTRL_REG, /* PLL control register */
+ DSIM_PHYCTRL_REG,
+ DSIM_PHYTIMING_REG,
+ DSIM_PHYTIMING1_REG,
+ DSIM_PHYTIMING2_REG,
+ NUM_REGS
+};
+static unsigned int exynos_reg_ofs[] = {
+ [DSIM_STATUS_REG] = 0x00,
+ [DSIM_SWRST_REG] = 0x04,
+ [DSIM_CLKCTRL_REG] = 0x08,
+ [DSIM_TIMEOUT_REG] = 0x0c,
+ [DSIM_CONFIG_REG] = 0x10,
+ [DSIM_ESCMODE_REG] = 0x14,
+ [DSIM_MDRESOL_REG] = 0x18,
+ [DSIM_MVPORCH_REG] = 0x1c,
+ [DSIM_MHPORCH_REG] = 0x20,
+ [DSIM_MSYNC_REG] = 0x24,
+ [DSIM_INTSRC_REG] = 0x2c,
+ [DSIM_INTMSK_REG] = 0x30,
+ [DSIM_PKTHDR_REG] = 0x34,
+ [DSIM_PAYLOAD_REG] = 0x38,
+ [DSIM_RXFIFO_REG] = 0x3c,
+ [DSIM_FIFOCTRL_REG] = 0x44,
+ [DSIM_PLLCTRL_REG] = 0x4c,
+ [DSIM_PHYCTRL_REG] = 0x5c,
+ [DSIM_PHYTIMING_REG] = 0x64,
+ [DSIM_PHYTIMING1_REG] = 0x68,
+ [DSIM_PHYTIMING2_REG] = 0x6c,
+};
+
+enum reg_value_idx {
+ RESET_TYPE,
+ PLL_TIMER,
+ STOP_STATE_CNT,
+ PHYCTRL_ULPS_EXIT,
+ PHYCTRL_VREG_LP,
+ PHYCTRL_SLEW_UP,
+ PHYTIMING_LPX,
+ PHYTIMING_HS_EXIT,
+ PHYTIMING_CLK_PREPARE,
+ PHYTIMING_CLK_ZERO,
+ PHYTIMING_CLK_POST,
+ PHYTIMING_CLK_TRAIL,
+ PHYTIMING_HS_PREPARE,
+ PHYTIMING_HS_ZERO,
+ PHYTIMING_HS_TRAIL
+};
+
+static unsigned int reg_values[] = {
+ [RESET_TYPE] = DSIM_SWRST,
+ [PLL_TIMER] = 500,
+ [STOP_STATE_CNT] = 0xf,
+ [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
+ [PHYCTRL_VREG_LP] = 0,
+ [PHYCTRL_SLEW_UP] = 0,
+ [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
+ [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
+ [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
+ [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
+ [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
+ [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
+ [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
+ [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
+ [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
+};
+
static struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
+ .reg_ofs = exynos_reg_ofs,
.plltmr_reg = 0x50,
.has_freqband = 1,
.has_clklane_stop = 1,
+ .num_clks = 2,
+ .max_freq = 1000,
+ .wait_for_reset = 1,
+ .num_bits_resol = 11,
+ .reg_values = reg_values,
};
static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+ .reg_ofs = exynos_reg_ofs,
.plltmr_reg = 0x50,
.has_freqband = 1,
.has_clklane_stop = 1,
+ .num_clks = 2,
+ .max_freq = 1000,
+ .wait_for_reset = 1,
+ .num_bits_resol = 11,
+ .reg_values = reg_values,
};
static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
+ .reg_ofs = exynos_reg_ofs,
.plltmr_reg = 0x58,
.has_clklane_stop = 1,
+ .num_clks = 2,
+ .max_freq = 1000,
+ .wait_for_reset = 1,
+ .num_bits_resol = 11,
+ .reg_values = reg_values,
};
static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+ .reg_ofs = exynos_reg_ofs,
.plltmr_reg = 0x58,
+ .num_clks = 2,
+ .max_freq = 1000,
+ .wait_for_reset = 1,
+ .num_bits_resol = 11,
+ .reg_values = reg_values,
};
static struct of_device_id exynos_dsi_of_match[] = {
@@ -371,7 +455,7 @@ static void exynos_dsi_reset(struct exynos_dsi *dsi)
struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
reinit_completion(&dsi->completed);
- DSI_WRITE(dsi, DSIM_SWRST_REG, DSIM_SWRST);
+ DSI_WRITE(dsi, DSIM_SWRST_REG, driver_data->reg_values[RESET_TYPE]);
}
#ifndef MHZ
@@ -405,7 +489,8 @@ static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
tmp = (u64)_m * fin;
do_div(tmp, _p);
- if (tmp < 500 * MHZ || tmp > 1000 * MHZ)
+ if (tmp < 500 * MHZ ||
+ tmp > driver_data->max_freq * MHZ)
continue;
tmp = (u64)_m * fin;
@@ -450,7 +535,8 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
}
dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
- writel(500, dsi->reg_base + driver_data->plltmr_reg);
+ writel(driver_data->reg_values[PLL_TIMER],
+ dsi->reg_base + driver_data->plltmr_reg);
reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
@@ -528,13 +614,15 @@ static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
{
struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
+ unsigned int *reg_values = driver_data->reg_values;
u32 reg;
if (driver_data->has_freqband)
return;
/* B D-PHY: D-PHY Master & Slave Analog Block control */
- reg = DSIM_PHYCTRL_ULPS_EXIT(0x0af);
+ reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
+ reg_values[PHYCTRL_SLEW_UP];
DSI_WRITE(dsi, DSIM_PHYCTRL_REG, reg);
/*
@@ -542,7 +630,7 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
* T HS-EXIT: Time that the transmitter drives LP-11 following a HS
* burst
*/
- reg = DSIM_PHYTIMING_LPX(0x06) | DSIM_PHYTIMING_HS_EXIT(0x0b);
+ reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
DSI_WRITE(dsi, DSIM_PHYTIMING_REG, reg);
/*
@@ -558,10 +646,11 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
* T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
* the last payload clock bit of a HS transmission burst
*/
- reg = DSIM_PHYTIMING1_CLK_PREPARE(0x07) |
- DSIM_PHYTIMING1_CLK_ZERO(0x27) |
- DSIM_PHYTIMING1_CLK_POST(0x0d) |
- DSIM_PHYTIMING1_CLK_TRAIL(0x08);
+ reg = reg_values[PHYTIMING_CLK_PREPARE] |
+ reg_values[PHYTIMING_CLK_ZERO] |
+ reg_values[PHYTIMING_CLK_POST] |
+ reg_values[PHYTIMING_CLK_TRAIL];
+
DSI_WRITE(dsi, DSIM_PHYTIMING1_REG, reg);
/*
@@ -573,8 +662,8 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
* T HS-TRAIL: Time that the transmitter drives the flipped differential
* state after last payload data bit of a HS transmission burst
*/
- reg = DSIM_PHYTIMING2_HS_PREPARE(0x09) | DSIM_PHYTIMING2_HS_ZERO(0x0d) |
- DSIM_PHYTIMING2_HS_TRAIL(0x0b);
+ reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
+ reg_values[PHYTIMING_HS_TRAIL];
DSI_WRITE(dsi, DSIM_PHYTIMING2_REG, reg);
}
@@ -705,7 +794,7 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
reg = DSI_READ(dsi, DSIM_ESCMODE_REG);
reg &= ~DSIM_STOP_STATE_CNT_MASK;
- reg |= DSIM_STOP_STATE_CNT(0xf);
+ reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
DSI_WRITE(dsi, DSIM_ESCMODE_REG, reg);
reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
@@ -717,6 +806,7 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
{
struct videomode *vm = &dsi->vm;
+ unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
u32 reg;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
@@ -733,8 +823,9 @@ static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
| DSIM_MAIN_HSA(vm->hsync_len);
DSI_WRITE(dsi, DSIM_MSYNC_REG, reg);
}
+ reg = DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) |
+ DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol);
- reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive);
DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg);
dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
@@ -1141,10 +1232,13 @@ static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
static int exynos_dsi_init(struct exynos_dsi *dsi)
{
+ struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
+
exynos_dsi_reset(dsi);
exynos_dsi_enable_irq(dsi);
exynos_dsi_enable_clock(dsi);
- exynos_dsi_wait_for_reset(dsi);
+ if (driver_data->wait_for_reset)
+ exynos_dsi_wait_for_reset(dsi);
exynos_dsi_set_phy_ctrl(dsi);
exynos_dsi_init_link(dsi);
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v6 11/15] drm/exynos: dsi: make use of array for clock access
[not found] ` <1434113958-15877-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
` (4 preceding siblings ...)
2015-06-12 12:59 ` [PATCH v6 10/15] drm/exynos: dsi: make use of driver data for static values Hyungwon Hwang
@ 2015-06-12 12:59 ` Hyungwon Hwang
2015-06-12 12:59 ` [PATCH v6 13/15] drm/exynos: dsi: add support for MIC driver as a bridge Hyungwon Hwang
` (4 subsequent siblings)
10 siblings, 0 replies; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 12:59 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: inki.dae-Sze3O3UU22JBDgjK7y7TUQ, daniel-rLtY4a/8tF1rovVCs/uTlw,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ, Hyungwon Hwang
This patch make the driver to use an array for clock access. The number
of clocks are different from the existing MIPI DSI driver and Exynos5433
MIPI DSI driver. So this patch is needed before adding support for
Exynos5433 MIPI DSI driver.
Signed-off-by: Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
Changes before:
- Refer https://patchwork.kernel.org/patch/6191801
Changes for v6:
- None
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 68 ++++++++++++++++-----------------
1 file changed, 33 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 0b468d7..557b9d2 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -211,6 +211,8 @@
REG_ADDR((dsi), (reg_idx)))
#define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx)))
+static char *clk_names[2] = { "bus_clk", "sclk_mipi" };
+
enum exynos_dsi_transfer_type {
EXYNOS_DSI_TX,
EXYNOS_DSI_RX,
@@ -260,8 +262,7 @@ struct exynos_dsi {
void __iomem *reg_base;
struct phy *phy;
- struct clk *sclk_clk;
- struct clk *bus_clk;
+ struct clk **clks;
struct regulator_bulk_data supplies[2];
int irq;
int te_gpio;
@@ -1390,7 +1391,8 @@ static const struct mipi_dsi_host_ops exynos_dsi_ops = {
static int exynos_dsi_poweron(struct exynos_dsi *dsi)
{
- int ret;
+ struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
+ int ret, i;
ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
if (ret < 0) {
@@ -1398,31 +1400,23 @@ static int exynos_dsi_poweron(struct exynos_dsi *dsi)
return ret;
}
- ret = clk_prepare_enable(dsi->bus_clk);
- if (ret < 0) {
- dev_err(dsi->dev, "cannot enable bus clock %d\n", ret);
- goto err_bus_clk;
- }
-
- ret = clk_prepare_enable(dsi->sclk_clk);
- if (ret < 0) {
- dev_err(dsi->dev, "cannot enable pll clock %d\n", ret);
- goto err_sclk_clk;
+ for (i = 0; i < driver_data->num_clks; i++) {
+ ret = clk_prepare_enable(dsi->clks[i]);
+ if (ret < 0)
+ goto err_clk;
}
ret = phy_power_on(dsi->phy);
if (ret < 0) {
dev_err(dsi->dev, "cannot enable phy %d\n", ret);
- goto err_phy;
+ goto err_clk;
}
return 0;
-err_phy:
- clk_disable_unprepare(dsi->sclk_clk);
-err_sclk_clk:
- clk_disable_unprepare(dsi->bus_clk);
-err_bus_clk:
+err_clk:
+ while (--i > -1)
+ clk_disable_unprepare(dsi->clks[i]);
regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
return ret;
@@ -1430,7 +1424,8 @@ err_bus_clk:
static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
{
- int ret;
+ struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
+ int ret, i;
usleep_range(10000, 20000);
@@ -1446,8 +1441,8 @@ static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
phy_power_off(dsi->phy);
- clk_disable_unprepare(dsi->sclk_clk);
- clk_disable_unprepare(dsi->bus_clk);
+ for (i = driver_data->num_clks - 1; i > -1; i--)
+ clk_disable_unprepare(dsi->clks[i]);
ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
if (ret < 0)
@@ -1778,7 +1773,7 @@ static int exynos_dsi_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct resource *res;
struct exynos_dsi *dsi;
- int ret;
+ int ret, i;
dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
if (!dsi)
@@ -1813,19 +1808,22 @@ static int exynos_dsi_probe(struct platform_device *pdev)
return -EPROBE_DEFER;
}
- dsi->sclk_clk = devm_clk_get(dev, "sclk_mipi");
- if (IS_ERR(dsi->sclk_clk)) {
- dsi->sclk_clk = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
- if (IS_ERR(dsi->sclk_clk)) {
- dev_info(dev, "failed to get dsi sclk clock\n");
- eturn PTR_ERR(dsi->sclk_clk);
- }
- }
+ dsi->clks = devm_kzalloc(dev,
+ sizeof(*dsi->clks) * dsi->driver_data->num_clks,
+ GFP_KERNEL);
+ for (i = 0; i < dsi->driver_data->num_clks; i++) {
+ dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
+ if (IS_ERR(dsi->clks[i])) {
+ if (strcmp(clk_names[i], "sclk_mipi") == 0) {
+ strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
+ i--;
+ continue;
+ }
- dsi->bus_clk = devm_clk_get(dev, "bus_clk");
- if (IS_ERR(dsi->bus_clk)) {
- dev_info(dev, "failed to get dsi bus clock\n");
- return PTR_ERR(dsi->bus_clk);
+ dev_info(dev, "failed to get the clock: %s\n",
+ clk_names[i]);
+ return PTR_ERR(dsi->clks[i]);
+ }
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v6 13/15] drm/exynos: dsi: add support for MIC driver as a bridge
[not found] ` <1434113958-15877-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
` (5 preceding siblings ...)
2015-06-12 12:59 ` [PATCH v6 11/15] drm/exynos: dsi: make use of array for clock access Hyungwon Hwang
@ 2015-06-12 12:59 ` Hyungwon Hwang
2015-06-12 12:59 ` [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi' Hyungwon Hwang
` (3 subsequent siblings)
10 siblings, 0 replies; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 12:59 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: inki.dae-Sze3O3UU22JBDgjK7y7TUQ, daniel-rLtY4a/8tF1rovVCs/uTlw,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ, Hyungwon Hwang
MIC must be initilized by MIPI DSI when it is being bound.
Signed-off-by: Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
Changes before:
- Refer https://patchwork.kernel.org/patch/6191811
Changes for v6:
- None
.../devicetree/bindings/video/exynos_dsim.txt | 23 ++++++++++++++++++---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 24 ++++++++++++++++++++++
2 files changed, 44 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt
index 11ccac9..0be0362 100644
--- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -32,10 +32,19 @@ Video interfaces:
Device node can contain video interface port nodes according to [2].
The following are properties specific to those nodes:
- port node:
- - reg: (required) can be 0 for input RGB/I80 port or 1 for DSI port;
+ port node inbound:
+ - reg: (required) must be 0.
+ port node outbound:
+ - reg: (required) must be 1.
- endpoint node of DSI port (reg = 1):
+ endpoint node connected from mic node (reg = 0):
+ - remote-endpoint: specifies the endpoint in mic node. This node is required
+ for Exynos5433 mipi dsi. So mic can access to panel node
+ thoughout this dsi node.
+ endpoint node connected to panel node (reg = 1):
+ - remote-endpoint: specifies the endpoint in panel node. This node is
+ required in all kinds of exynos mipi dsi to represent
+ the connection between mipi dsi and panel.
- samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst
mode
- samsung,esc-clock-frequency: specifies DSI frequency in escape mode
@@ -74,7 +83,15 @@ Example:
#address-cells = <1>;
#size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ decon_to_mic: endpoint {
+ remote-endpoint = <&mic_to_decon>;
+ };
+ };
+
port@1 {
+ reg = <1>;
dsi_ep: endpoint {
reg = <0>;
samsung,burst-clock-frequency = <500000000>;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index d9bcdb9..0719114 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -21,6 +21,7 @@
#include <linux/irq.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
+#include <linux/of_graph.h>
#include <linux/phy/phy.h>
#include <linux/regulator/consumer.h>
#include <linux/component.h>
@@ -288,6 +289,7 @@ struct exynos_dsi {
struct list_head transfer_list;
struct exynos_dsi_driver_data *driver_data;
+ struct device_node *bridge_node;
};
#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
@@ -1794,7 +1796,22 @@ static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
&dsi->esc_clk_rate);
+ if (ret < 0)
+ goto end;
+
+ of_node_put(ep);
+
+ ep = of_graph_get_next_endpoint(node, NULL);
+ if (!ep) {
+ ret = -ENXIO;
+ goto end;
+ }
+ dsi->bridge_node = of_graph_get_remote_port_parent(ep);
+ if (!dsi->bridge_node) {
+ ret = -ENXIO;
+ goto end;
+ }
end:
of_node_put(ep);
@@ -1807,6 +1824,7 @@ static int exynos_dsi_bind(struct device *dev, struct device *master,
struct exynos_drm_display *display = dev_get_drvdata(dev);
struct exynos_dsi *dsi = display_to_dsi(display);
struct drm_device *drm_dev = data;
+ struct drm_bridge *bridge;
int ret;
ret = exynos_drm_create_enc_conn(drm_dev, display);
@@ -1816,6 +1834,12 @@ static int exynos_dsi_bind(struct device *dev, struct device *master,
return ret;
}
+ bridge = of_drm_find_bridge(dsi->bridge_node);
+ if (bridge) {
+ display->encoder->bridge = bridge;
+ drm_bridge_attach(drm_dev, bridge);
+ }
+
return mipi_dsi_host_register(&dsi->dsi_host);
}
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
[not found] ` <1434113958-15877-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
` (6 preceding siblings ...)
2015-06-12 12:59 ` [PATCH v6 13/15] drm/exynos: dsi: add support for MIC driver as a bridge Hyungwon Hwang
@ 2015-06-12 12:59 ` Hyungwon Hwang
2015-06-22 9:10 ` Inki Dae
2015-06-12 12:59 ` [PATCH 1/2] drm/exynos: ipp: fix wrong index referencing a config element Hyungwon Hwang
` (2 subsequent siblings)
10 siblings, 1 reply; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 12:59 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: inki.dae-Sze3O3UU22JBDgjK7y7TUQ, daniel-rLtY4a/8tF1rovVCs/uTlw,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ, Hyungwon Hwang
The clock which was named as 'pll_clk' is actually not the clock source
of PLL in MIPI DSI. This patch fixes this disagreement.
Signed-off-by: Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
Changes before:
- Refer https://patchwork.kernel.org/patch/6191811
Changes for v6:
- None
arch/arm/boot/dts/exynos4.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index e20cdc2..1538d7a 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -167,7 +167,7 @@
phys = <&mipi_phy 1>;
phy-names = "dsim";
clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
- clock-names = "bus_clk", "pll_clk";
+ clock-names = "bus_clk", "sclk_mipi";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
2015-06-12 12:59 ` [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi' Hyungwon Hwang
@ 2015-06-22 9:10 ` Inki Dae
2015-06-22 11:42 ` Inki Dae
0 siblings, 1 reply; 41+ messages in thread
From: Inki Dae @ 2015-06-22 9:10 UTC (permalink / raw)
To: Hyungwon Hwang, Kukjin Kim, Krzysztof Kozlowski
Cc: devicetree, sw0312.kim, dri-devel
On 2015년 06월 12일 21:59, Hyungwon Hwang wrote:
> The clock which was named as 'pll_clk' is actually not the clock source
> of PLL in MIPI DSI. This patch fixes this disagreement.
Mr. Kukjin and Krzysztof, can you give me Acked-by or Singed-off-by? I'd
like to merge this patch to mainline through drm-next.
Thanks,
Inki Dae
>
> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
> ---
> Changes before:
> - Refer https://patchwork.kernel.org/patch/6191811
> Changes for v6:
> - None
>
> arch/arm/boot/dts/exynos4.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
> index e20cdc2..1538d7a 100644
> --- a/arch/arm/boot/dts/exynos4.dtsi
> +++ b/arch/arm/boot/dts/exynos4.dtsi
> @@ -167,7 +167,7 @@
> phys = <&mipi_phy 1>;
> phy-names = "dsim";
> clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
> - clock-names = "bus_clk", "pll_clk";
> + clock-names = "bus_clk", "sclk_mipi";
> status = "disabled";
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
2015-06-22 9:10 ` Inki Dae
@ 2015-06-22 11:42 ` Inki Dae
2015-06-22 11:59 ` Krzysztof Kozlowski
2015-06-22 12:35 ` Krzysztof Kozlowski
0 siblings, 2 replies; 41+ messages in thread
From: Inki Dae @ 2015-06-22 11:42 UTC (permalink / raw)
To: Hyungwon Hwang, Kukjin Kim, Krzysztof Kozlowski,
Krzysztof Kozlowski
Cc: devicetree, sw0312.kim, dri-devel
+ Krzysztof
On 2015년 06월 22일 18:10, Inki Dae wrote:
> On 2015년 06월 12일 21:59, Hyungwon Hwang wrote:
>> The clock which was named as 'pll_clk' is actually not the clock source
>> of PLL in MIPI DSI. This patch fixes this disagreement.
>
> Mr. Kukjin and Krzysztof, can you give me Acked-by or Singed-off-by? I'd
> like to merge this patch to mainline through drm-next.
>
> Thanks,
> Inki Dae
>
>>
>> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
>> ---
>> Changes before:
>> - Refer https://patchwork.kernel.org/patch/6191811
>> Changes for v6:
>> - None
>>
>> arch/arm/boot/dts/exynos4.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
>> index e20cdc2..1538d7a 100644
>> --- a/arch/arm/boot/dts/exynos4.dtsi
>> +++ b/arch/arm/boot/dts/exynos4.dtsi
>> @@ -167,7 +167,7 @@
>> phys = <&mipi_phy 1>;
>> phy-names = "dsim";
>> clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
>> - clock-names = "bus_clk", "pll_clk";
>> + clock-names = "bus_clk", "sclk_mipi";
>> status = "disabled";
>> #address-cells = <1>;
>> #size-cells = <0>;
>> --
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
2015-06-22 11:42 ` Inki Dae
@ 2015-06-22 11:59 ` Krzysztof Kozlowski
2015-06-22 12:10 ` Inki Dae
2015-06-22 12:35 ` Krzysztof Kozlowski
1 sibling, 1 reply; 41+ messages in thread
From: Krzysztof Kozlowski @ 2015-06-22 11:59 UTC (permalink / raw)
To: Inki Dae
Cc: Hyungwon Hwang, Kukjin Kim, Krzysztof Kozlowski, dri-devel,
devicetree, daniel, sw0312.kim, jy0922.shim, linux-samsung-soc
2015-06-22 20:42 GMT+09:00 Inki Dae <inki.dae@samsung.com>:
> + Krzysztof
>
> On 2015년 06월 22일 18:10, Inki Dae wrote:
>> On 2015년 06월 12일 21:59, Hyungwon Hwang wrote:
>>> The clock which was named as 'pll_clk' is actually not the clock source
>>> of PLL in MIPI DSI. This patch fixes this disagreement.
>>
>> Mr. Kukjin and Krzysztof, can you give me Acked-by or Singed-off-by? I'd
>> like to merge this patch to mainline through drm-next.
Dear Hyungwon Hwang,
Please always CC samsung-soc mailing list on such patches. I won't
receive it on my personal email if you don't CC the list. The
get_maintainers.pl gives necessary addresses.
Comment below,
>>
>> Thanks,
>> Inki Dae
>>
>>>
>>> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
>>> ---
>>> Changes before:
>>> - Refer https://patchwork.kernel.org/patch/6191811
>>> Changes for v6:
>>> - None
>>>
>>> arch/arm/boot/dts/exynos4.dtsi | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
>>> index e20cdc2..1538d7a 100644
>>> --- a/arch/arm/boot/dts/exynos4.dtsi
>>> +++ b/arch/arm/boot/dts/exynos4.dtsi
>>> @@ -167,7 +167,7 @@
>>> phys = <&mipi_phy 1>;
>>> phy-names = "dsim";
>>> clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
>>> - clock-names = "bus_clk", "pll_clk";
>>> + clock-names = "bus_clk", "sclk_mipi";
It seems wrong. The driver fetches reference from a name of "pll_clk",
not "sclk_mipi". Also bindings documentation mentions pll_clk and
bus_clk only.
Best regards,
Krzysztof
>>> status = "disabled";
>>> #address-cells = <1>;
>>> #size-cells = <0>;
>>> --
>>> 1.9.1
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>>
>>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
2015-06-22 11:59 ` Krzysztof Kozlowski
@ 2015-06-22 12:10 ` Inki Dae
2015-06-22 12:20 ` Krzysztof Kozlowski
0 siblings, 1 reply; 41+ messages in thread
From: Inki Dae @ 2015-06-22 12:10 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: devicetree, Kukjin Kim, sw0312.kim, dri-devel, linux-samsung-soc
On 2015년 06월 22일 20:59, Krzysztof Kozlowski wrote:
> 2015-06-22 20:42 GMT+09:00 Inki Dae <inki.dae@samsung.com>:
>> + Krzysztof
>>
>> On 2015년 06월 22일 18:10, Inki Dae wrote:
>>> On 2015년 06월 12일 21:59, Hyungwon Hwang wrote:
>>>> The clock which was named as 'pll_clk' is actually not the clock source
>>>> of PLL in MIPI DSI. This patch fixes this disagreement.
>>>
>>> Mr. Kukjin and Krzysztof, can you give me Acked-by or Singed-off-by? I'd
>>> like to merge this patch to mainline through drm-next.
>
> Dear Hyungwon Hwang,
>
> Please always CC samsung-soc mailing list on such patches. I won't
> receive it on my personal email if you don't CC the list. The
> get_maintainers.pl gives necessary addresses.
>
> Comment below,
>
>>>
>>> Thanks,
>>> Inki Dae
>>>
>>>>
>>>> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
>>>> ---
>>>> Changes before:
>>>> - Refer https://patchwork.kernel.org/patch/6191811
>>>> Changes for v6:
>>>> - None
>>>>
>>>> arch/arm/boot/dts/exynos4.dtsi | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
>>>> index e20cdc2..1538d7a 100644
>>>> --- a/arch/arm/boot/dts/exynos4.dtsi
>>>> +++ b/arch/arm/boot/dts/exynos4.dtsi
>>>> @@ -167,7 +167,7 @@
>>>> phys = <&mipi_phy 1>;
>>>> phy-names = "dsim";
>>>> clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
>>>> - clock-names = "bus_clk", "pll_clk";
>>>> + clock-names = "bus_clk", "sclk_mipi";
>
> It seems wrong. The driver fetches reference from a name of "pll_clk",
> not "sclk_mipi". Also bindings documentation mentions pll_clk and
> bus_clk only.
Krzysztof,
There is your missing point. The driver is already considered for
pll_clk also. See the below codes,
#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
...
for (i = 0; i < dsi->driver_data->num_clks; i++) {
dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
if (IS_ERR(dsi->clks[i])) {
if (strcmp(clk_names[i], "sclk_mipi") == 0) {
strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
i--;
continue;
}
dev_info(dev, "failed to get the clock: %s\n",
clk_names[i]);
return PTR_ERR(dsi->clks[i]);
}
}
Above codes make the driver to try to get the pll_clk - defined as
OLD_SCLK_MIPI_CLK_NAME macro - again if getting sclk_mipi clock failed
so there is no problem even though a little bit ugly.
As you know, we should guarantee the backward compatibility so this
codes check two clock names.
Thanks,
Inki Dae
>
> Best regards,
> Krzysztof
>
>
>>>> status = "disabled";
>>>> #address-cells = <1>;
>>>> #size-cells = <0>;
>>>> --
>>>> 1.9.1
>>>>
>>>> --
>>>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>>>> the body of a message to majordomo@vger.kernel.org
>>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>>>
>>>
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
2015-06-22 12:10 ` Inki Dae
@ 2015-06-22 12:20 ` Krzysztof Kozlowski
0 siblings, 0 replies; 41+ messages in thread
From: Krzysztof Kozlowski @ 2015-06-22 12:20 UTC (permalink / raw)
To: Inki Dae, Hyungwon Hwang
Cc: devicetree, Krzysztof Kozlowski, Kukjin Kim, sw0312.kim,
linux-samsung-soc, dri-devel
2015-06-22 21:10 GMT+09:00 Inki Dae <inki.dae@samsung.com>:
> On 2015년 06월 22일 20:59, Krzysztof Kozlowski wrote:
>> 2015-06-22 20:42 GMT+09:00 Inki Dae <inki.dae@samsung.com>:
>>> + Krzysztof
>>>
>>> On 2015년 06월 22일 18:10, Inki Dae wrote:
>>>> On 2015년 06월 12일 21:59, Hyungwon Hwang wrote:
>>>>> The clock which was named as 'pll_clk' is actually not the clock source
>>>>> of PLL in MIPI DSI. This patch fixes this disagreement.
>>>>
>>>> Mr. Kukjin and Krzysztof, can you give me Acked-by or Singed-off-by? I'd
>>>> like to merge this patch to mainline through drm-next.
>>
>> Dear Hyungwon Hwang,
>>
>> Please always CC samsung-soc mailing list on such patches. I won't
>> receive it on my personal email if you don't CC the list. The
>> get_maintainers.pl gives necessary addresses.
>>
>> Comment below,
>>
>>>>
>>>> Thanks,
>>>> Inki Dae
>>>>
>>>>>
>>>>> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
>>>>> ---
>>>>> Changes before:
>>>>> - Refer https://patchwork.kernel.org/patch/6191811
>>>>> Changes for v6:
>>>>> - None
>>>>>
>>>>> arch/arm/boot/dts/exynos4.dtsi | 2 +-
>>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
>>>>> index e20cdc2..1538d7a 100644
>>>>> --- a/arch/arm/boot/dts/exynos4.dtsi
>>>>> +++ b/arch/arm/boot/dts/exynos4.dtsi
>>>>> @@ -167,7 +167,7 @@
>>>>> phys = <&mipi_phy 1>;
>>>>> phy-names = "dsim";
>>>>> clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
>>>>> - clock-names = "bus_clk", "pll_clk";
>>>>> + clock-names = "bus_clk", "sclk_mipi";
>>
>> It seems wrong. The driver fetches reference from a name of "pll_clk",
>> not "sclk_mipi". Also bindings documentation mentions pll_clk and
>> bus_clk only.
>
> Krzysztof,
>
> There is your missing point. The driver is already considered for
> pll_clk also. See the below codes,
>
> #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
> ...
>
> for (i = 0; i < dsi->driver_data->num_clks; i++) {
> dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
> if (IS_ERR(dsi->clks[i])) {
> if (strcmp(clk_names[i], "sclk_mipi") == 0) {
> strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
> i--;
> continue;
> }
>
> dev_info(dev, "failed to get the clock: %s\n",
> clk_names[i]);
> return PTR_ERR(dsi->clks[i]);
> }
> }
>
> Above codes make the driver to try to get the pll_clk - defined as
> OLD_SCLK_MIPI_CLK_NAME macro - again if getting sclk_mipi clock failed
> so there is no problem even though a little bit ugly.
>
> As you know, we should guarantee the backward compatibility so this
> codes check two clock names.
I am looking at next-20150622 and file
drivers/gpu/drm/exynos/exynos_drm_dsi.c. There is no such code there.
There is only pll_clk. No sclk_mipi.
Maybe it was changed by other patch... but I haven't received it. Also
I cannot find such patch on linux-kernel, linux-arm-kernel and
linux-samsung-soc. I cannot ack something that I cannot see :) .
If you sent whole patchset to my office address, then I will look at
it tomorrow. From home I can only look at LKML patches.
Best regards,
Krzysztof
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
2015-06-22 11:42 ` Inki Dae
2015-06-22 11:59 ` Krzysztof Kozlowski
@ 2015-06-22 12:35 ` Krzysztof Kozlowski
2015-06-23 2:10 ` Krzysztof Kozlowski
1 sibling, 1 reply; 41+ messages in thread
From: Krzysztof Kozlowski @ 2015-06-22 12:35 UTC (permalink / raw)
To: Inki Dae
Cc: Hyungwon Hwang, Kukjin Kim, Krzysztof Kozlowski, dri-devel,
devicetree, daniel, sw0312.kim, jy0922.shim, linux-samsung-soc
2015-06-22 20:42 GMT+09:00 Inki Dae <inki.dae@samsung.com>:
> + Krzysztof
>
> On 2015년 06월 22일 18:10, Inki Dae wrote:
>> On 2015년 06월 12일 21:59, Hyungwon Hwang wrote:
>>> The clock which was named as 'pll_clk' is actually not the clock source
>>> of PLL in MIPI DSI. This patch fixes this disagreement.
>>
>> Mr. Kukjin and Krzysztof, can you give me Acked-by or Singed-off-by? I'd
>> like to merge this patch to mainline through drm-next.
Thanks for forwarding me other necessary patch. All that burden could
be easily avoided by sending everything to samsung-soc anyway.
The patch itself looks good:
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Best regards,
Krzysztof
>>
>> Thanks,
>> Inki Dae
>>
>>>
>>> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
>>> ---
>>> Changes before:
>>> - Refer https://patchwork.kernel.org/patch/6191811
>>> Changes for v6:
>>> - None
>>>
>>> arch/arm/boot/dts/exynos4.dtsi | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
>>> index e20cdc2..1538d7a 100644
>>> --- a/arch/arm/boot/dts/exynos4.dtsi
>>> +++ b/arch/arm/boot/dts/exynos4.dtsi
>>> @@ -167,7 +167,7 @@
>>> phys = <&mipi_phy 1>;
>>> phy-names = "dsim";
>>> clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
>>> - clock-names = "bus_clk", "pll_clk";
>>> + clock-names = "bus_clk", "sclk_mipi";
>>> status = "disabled";
>>> #address-cells = <1>;
>>> #size-cells = <0>;
>>> --
>>> 1.9.1
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>>
>>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
2015-06-22 12:35 ` Krzysztof Kozlowski
@ 2015-06-23 2:10 ` Krzysztof Kozlowski
2015-06-23 2:28 ` Inki Dae
0 siblings, 1 reply; 41+ messages in thread
From: Krzysztof Kozlowski @ 2015-06-23 2:10 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Inki Dae, Hyungwon Hwang, Kukjin Kim, dri-devel, devicetree,
daniel, sw0312.kim, jy0922.shim, linux-samsung-soc, Rob Herring
2015-06-22 21:35 GMT+09:00 Krzysztof Kozlowski <k.kozlowski@samsung.com>:
> 2015-06-22 20:42 GMT+09:00 Inki Dae <inki.dae@samsung.com>:
>> + Krzysztof
>>
>> On 2015년 06월 22일 18:10, Inki Dae wrote:
>>> On 2015년 06월 12일 21:59, Hyungwon Hwang wrote:
>>>> The clock which was named as 'pll_clk' is actually not the clock source
>>>> of PLL in MIPI DSI. This patch fixes this disagreement.
>>>
>>> Mr. Kukjin and Krzysztof, can you give me Acked-by or Singed-off-by? I'd
>>> like to merge this patch to mainline through drm-next.
>
> Thanks for forwarding me other necessary patch. All that burden could
> be easily avoided by sending everything to samsung-soc anyway.
>
> The patch itself looks good:
> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>
> Best regards,
> Krzysztof
To clarify. There were seven versions of this patch and none of them
were sent to samsung-soc list, to Kukjin Kim or to me.
I also wonder about patch 2: "of: add helper for getting endpoint node
with specific identifiers"
for which I can't find respective ack from Rob Herring (+Cc). I only found this:
http://www.spinics.net/lists/devicetree/msg69336.html
but there are only comments, not an ack.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
2015-06-23 2:10 ` Krzysztof Kozlowski
@ 2015-06-23 2:28 ` Inki Dae
2015-06-23 4:00 ` Krzysztof Kozlowski
0 siblings, 1 reply; 41+ messages in thread
From: Inki Dae @ 2015-06-23 2:28 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: devicetree, Kukjin Kim, sw0312.kim, dri-devel, Rob Herring,
linux-samsung-soc
On 2015년 06월 23일 11:10, Krzysztof Kozlowski wrote:
> 2015-06-22 21:35 GMT+09:00 Krzysztof Kozlowski <k.kozlowski@samsung.com>:
>> 2015-06-22 20:42 GMT+09:00 Inki Dae <inki.dae@samsung.com>:
>>> + Krzysztof
>>>
>>> On 2015년 06월 22일 18:10, Inki Dae wrote:
>>>> On 2015년 06월 12일 21:59, Hyungwon Hwang wrote:
>>>>> The clock which was named as 'pll_clk' is actually not the clock source
>>>>> of PLL in MIPI DSI. This patch fixes this disagreement.
>>>>
>>>> Mr. Kukjin and Krzysztof, can you give me Acked-by or Singed-off-by? I'd
>>>> like to merge this patch to mainline through drm-next.
>>
>> Thanks for forwarding me other necessary patch. All that burden could
>> be easily avoided by sending everything to samsung-soc anyway.
>>
>> The patch itself looks good:
>> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>>
>> Best regards,
>> Krzysztof
>
> To clarify. There were seven versions of this patch and none of them
> were sent to samsung-soc list, to Kukjin Kim or to me.
>
> I also wonder about patch 2: "of: add helper for getting endpoint node
> with specific identifiers"
> for which I can't find respective ack from Rob Herring (+Cc). I only found this:
> http://www.spinics.net/lists/devicetree/msg69336.html
> but there are only comments, not an ack.
Below is the comments from Rob Herring. How about subscribing device
tree mainling list? You are a maintainer of Exynos SoC. This patch was
posted to device tree mailing list ccing Grant and Rob. If you listen to
only Samsung SoC mailing list then you couldn't find this patch in your
email box.
"On Sun, Feb 22, 2015 at 7:41 PM, Hyungwon Hwang
<human.hwang@samsung.com> wrote:
> When there are multiple ports or multiple endpoints in a port, they
have to be
> distinguished by the value of reg property. It is common. The drivers
can get
> the specific endpoint in the specific port via this function. Now the
drivers
> have to implement this code in themselves or have to force the order
of dt nodes
> to get the right node.
>
> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
I'm not applying as there is no user, so apply this patch along with a
user of the function."
That is why I merged this patch to exynos-drm-next.
Thanks,
Inki Dae
>
> Best regards,
> Krzysztof
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
2015-06-23 2:28 ` Inki Dae
@ 2015-06-23 4:00 ` Krzysztof Kozlowski
0 siblings, 0 replies; 41+ messages in thread
From: Krzysztof Kozlowski @ 2015-06-23 4:00 UTC (permalink / raw)
To: Inki Dae
Cc: devicetree, Kukjin Kim, sw0312.kim, dri-devel, Rob Herring,
linux-samsung-soc
On 23.06.2015 11:28, Inki Dae wrote:
> On 2015년 06월 23일 11:10, Krzysztof Kozlowski wrote:
>> 2015-06-22 21:35 GMT+09:00 Krzysztof Kozlowski <k.kozlowski@samsung.com>:
>>> 2015-06-22 20:42 GMT+09:00 Inki Dae <inki.dae@samsung.com>:
>>>> + Krzysztof
>>>>
>>>> On 2015년 06월 22일 18:10, Inki Dae wrote:
>>>>> On 2015년 06월 12일 21:59, Hyungwon Hwang wrote:
>>>>>> The clock which was named as 'pll_clk' is actually not the clock source
>>>>>> of PLL in MIPI DSI. This patch fixes this disagreement.
>>>>>
>>>>> Mr. Kukjin and Krzysztof, can you give me Acked-by or Singed-off-by? I'd
>>>>> like to merge this patch to mainline through drm-next.
>>>
>>> Thanks for forwarding me other necessary patch. All that burden could
>>> be easily avoided by sending everything to samsung-soc anyway.
>>>
>>> The patch itself looks good:
>>> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>>>
>>> Best regards,
>>> Krzysztof
>>
>> To clarify. There were seven versions of this patch and none of them
>> were sent to samsung-soc list, to Kukjin Kim or to me.
>>
>> I also wonder about patch 2: "of: add helper for getting endpoint node
>> with specific identifiers"
>> for which I can't find respective ack from Rob Herring (+Cc). I only found this:
>> http://www.spinics.net/lists/devicetree/msg69336.html
>> but there are only comments, not an ack.
>
> Below is the comments from Rob Herring. How about subscribing device
> tree mainling list? You are a maintainer of Exynos SoC. This patch was
> posted to device tree mailing list ccing Grant and Rob. If you listen to
> only Samsung SoC mailing list then you couldn't find this patch in your
> email box.
Some time ago I was subscribing devicetree, but as I am not device tree
maintainer and the traffic there is really huge, I unsubscribed.
>
> "On Sun, Feb 22, 2015 at 7:41 PM, Hyungwon Hwang
> <human.hwang@samsung.com> wrote:
> > When there are multiple ports or multiple endpoints in a port, they
> have to be
> > distinguished by the value of reg property. It is common. The drivers
> can get
> > the specific endpoint in the specific port via this function. Now the
> drivers
> > have to implement this code in themselves or have to force the order
> of dt nodes
> > to get the right node.
> >
> > Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
>
> Acked-by: Rob Herring <robh@kernel.org>
>
> I'm not applying as there is no user, so apply this patch along with a
> user of the function."
Thanks! That helped me finding it in the archives.
Best regards,
Krzysztof
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 1/2] drm/exynos: ipp: fix wrong index referencing a config element
[not found] ` <1434113958-15877-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
` (7 preceding siblings ...)
2015-06-12 12:59 ` [PATCH v6 15/15] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi' Hyungwon Hwang
@ 2015-06-12 12:59 ` Hyungwon Hwang
2015-06-12 13:02 ` Hyungwon Hwang
2015-06-12 12:59 ` [PATCH 2/3] ARM: dts: Add the reference node for syscon to mipi phy for Exynos3250 Hyungwon Hwang
2015-06-12 12:59 ` [v3,2/3] drm/panel: add s6e63j0x03 LCD panel driver Hyungwon Hwang
10 siblings, 1 reply; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 12:59 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: inki.dae-Sze3O3UU22JBDgjK7y7TUQ, daniel-rLtY4a/8tF1rovVCs/uTlw,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ, Hyungwon Hwang
Config depends on the opreation. So it must be referenced by an
operation id, not a property id.
Signed-off-by: Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index b7f1cbc..54c5cf4 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -486,8 +486,7 @@ static int ipp_validate_mem_node(struct drm_device *drm_dev,
unsigned int bpp;
int i;
- /* The property id should already be varified */
- ipp_cfg = &c_node->property.config[m_node->prop_id];
+ ipp_cfg = &c_node->property.config[m_node->ops_id];
num_plane = drm_format_num_planes(ipp_cfg->fmt);
/**
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH 1/2] drm/exynos: ipp: fix wrong index referencing a config element
2015-06-12 12:59 ` [PATCH 1/2] drm/exynos: ipp: fix wrong index referencing a config element Hyungwon Hwang
@ 2015-06-12 13:02 ` Hyungwon Hwang
0 siblings, 0 replies; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 13:02 UTC (permalink / raw)
To: Hyungwon Hwang; +Cc: devicetree, sw0312.kim, dri-devel
Please ignore this mail. I didn't know that "git send *" includes all
files in the subdirectories. I am very sorry for disturbing you.
Best regards,
Hyungwon Hwang
On Fri, 12 Jun 2015 21:59:11 +0900
Hyungwon Hwang <human.hwang@samsung.com> wrote:
> Config depends on the opreation. So it must be referenced by an
> operation id, not a property id.
>
> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
> ---
> drivers/gpu/drm/exynos/exynos_drm_ipp.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
> b/drivers/gpu/drm/exynos/exynos_drm_ipp.c index b7f1cbc..54c5cf4
> 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
> @@ -486,8 +486,7 @@ static int ipp_validate_mem_node(struct
> drm_device *drm_dev, unsigned int bpp;
> int i;
>
> - /* The property id should already be varified */
> - ipp_cfg = &c_node->property.config[m_node->prop_id];
> + ipp_cfg = &c_node->property.config[m_node->ops_id];
> num_plane = drm_format_num_planes(ipp_cfg->fmt);
>
> /**
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 2/3] ARM: dts: Add the reference node for syscon to mipi phy for Exynos3250
[not found] ` <1434113958-15877-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
` (8 preceding siblings ...)
2015-06-12 12:59 ` [PATCH 1/2] drm/exynos: ipp: fix wrong index referencing a config element Hyungwon Hwang
@ 2015-06-12 12:59 ` Hyungwon Hwang
2015-06-12 13:02 ` Hyungwon Hwang
2015-06-12 12:59 ` [v3,2/3] drm/panel: add s6e63j0x03 LCD panel driver Hyungwon Hwang
10 siblings, 1 reply; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 12:59 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: inki.dae-Sze3O3UU22JBDgjK7y7TUQ, daniel-rLtY4a/8tF1rovVCs/uTlw,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ, Hyungwon Hwang
Exynos mipi phy driver needs syscon node to be probed successfully.
Signed-off-by: Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
arch/arm/boot/dts/exynos3250.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index e3bfb11..f8c02dd 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -140,6 +140,7 @@
compatible = "samsung,s5pv210-mipi-video-phy";
reg = <0x10020710 8>;
#phy-cells = <1>;
+ syscon = <&pmu_system_controller>;
};
pd_cam: cam-power-domain@10023C00 {
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH 2/3] ARM: dts: Add the reference node for syscon to mipi phy for Exynos3250
2015-06-12 12:59 ` [PATCH 2/3] ARM: dts: Add the reference node for syscon to mipi phy for Exynos3250 Hyungwon Hwang
@ 2015-06-12 13:02 ` Hyungwon Hwang
0 siblings, 0 replies; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 13:02 UTC (permalink / raw)
To: Hyungwon Hwang; +Cc: devicetree, sw0312.kim, dri-devel
Please ignore this mail. I didn't know that "git send *" includes all
files in the subdirectories. I am very sorry for disturbing you.
Best regards,
Hyungwon Hwang
On Fri, 12 Jun 2015 21:59:15 +0900
Hyungwon Hwang <human.hwang@samsung.com> wrote:
> Exynos mipi phy driver needs syscon node to be probed successfully.
>
> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
> ---
> arch/arm/boot/dts/exynos3250.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi
> b/arch/arm/boot/dts/exynos3250.dtsi index e3bfb11..f8c02dd 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -140,6 +140,7 @@
> compatible =
> "samsung,s5pv210-mipi-video-phy"; reg = <0x10020710 8>;
> #phy-cells = <1>;
> + syscon = <&pmu_system_controller>;
> };
>
> pd_cam: cam-power-domain@10023C00 {
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [v3,2/3] drm/panel: add s6e63j0x03 LCD panel driver
[not found] ` <1434113958-15877-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
` (9 preceding siblings ...)
2015-06-12 12:59 ` [PATCH 2/3] ARM: dts: Add the reference node for syscon to mipi phy for Exynos3250 Hyungwon Hwang
@ 2015-06-12 12:59 ` Hyungwon Hwang
10 siblings, 0 replies; 41+ messages in thread
From: Hyungwon Hwang @ 2015-06-12 12:59 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: inki.dae-Sze3O3UU22JBDgjK7y7TUQ, daniel-rLtY4a/8tF1rovVCs/uTlw,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ, Hyungwon Hwang,
treding-DDmLM1+adcrQT0dZR+AlfA
From: Inki Dae <inki.dae-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
This patch adds MIPI-DSI based S6E63J0X03 AMOLED LCD panel driver
which uses mipi_dsi bus to communicate with panel. The panel has
320×320 resolution in 1.63-inch physical panel. This panel is used in
Samsung Galaxy Gear 2.
Signed-off-by: Inki Dae <inki.dae-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Acked-by: Kyungmin Park <kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
Changes for v2:
- Change the gamma table to 2-dimensional array
- Change the way to make index for brightness
- Make command functions to an array so that it can be called simply
- Change command id for reading device ID
- Change the way to handle the error condition
- Remove power variable, and use the same name variable in bl_dev
- Add the state FB_BLANK_NORMAL to represent the state which the panel
is working but blanked
- Miscellaneous changes to increase the readability and follow the
coding-style standard
Changes for v3:
- Add DT binding documentation
- Add the code getting DT properties of 'panel-width-mm' and 'panel-height-mm'
- Remove the code getting unnecessary DT properties flip-*
.../bindings/panel/samsung,s6e63j0x03.txt | 55 +++
drivers/gpu/drm/panel/Kconfig | 6 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-s6e63j0x03.c | 546 +++++++++++++++++++++
4 files changed, 608 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e63j0x03.txt
create mode 100644 drivers/gpu/drm/panel/panel-s6e63j0x03.c
--
1.9.1
diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e63j0x03.txt b/Documentation/devicetree/bindings/panel/samsung,s6e63j0x03.txt
new file mode 100644
index 0000000..f8215e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e63j0x03.txt
@@ -0,0 +1,55 @@
+Samsung S6E63J0X03 1.63" 320x320 TFT LCD panel
+
+Required properties:
+ - compatible: "samsung,s6e63j0x03"
+ - reg: the virtual channel number of a DSI peripheral
+ - vdd3-supply: core voltage supply
+ - vci-supply: voltage supply for analog circuits
+ - reset-gpios: a GPIO spec for the reset pin
+ - te-gpios: a GPIO spec for the tearing effect synchronization signal gpio pin
+
+Optional properties:
+ - display-timings: timings for the connected panel as described by [1]
+ - power-on-delay: delay after turning regulators on [ms]
+ - power-off-delay: delay after turning regulators off [ms]
+ - reset-delay: delay after reset sequence [ms]
+ - panel-width-mm: physical panel width [mm]
+ - panel-height-mm: physical panel height [mm]
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in [2]. This
+node should describe panel's video bus.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+panel@0 {
+ compatible = "samsung,s6e63j0x03";
+ reg = <0>;
+ vdd3-supply = <&ldo16_reg>;
+ vci-supply = <&ldo20_reg>;
+ reset-gpios = <&gpe0 1 0>;
+ te-gpios = <&gpx0 6 0>;
+ power-on-delay= <30>;
+ power-off-delay= <120>;
+ reset-delay = <5>;
+ init-delay = <100>;
+ panel-width-mm = <29>;
+ panel-height-mm = <29>;
+
+ display-timings {
+ timing-0 {
+ clock-frequency = <0>;
+ hactive = <320>;
+ vactive = <320>;
+ hfront-porch = <1>;
+ hback-porch = <1>;
+ hsync-len = <1>;
+ vfront-porch = <150>;
+ vback-porch = <1>;
+ vsync-len = <2>;
+ };
+ };
+};
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 3df9b9b..8fa7610 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -46,4 +46,10 @@ config DRM_PANEL_S6E3HA2
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS
+config DRM_PANEL_S6E63J0X03
+ tristate "S6E63J0X03 DSI video mode panel"
+ depends on OF
+ select DRM_MIPI_DSI
+ select VIDEOMODE_HELPERS
+
endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 16ff312..9054da1 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
obj-$(CONFIG_DRM_PANEL_S6E3HA2) += panel-s6e3ha2.o
+obj-$(CONFIG_DRM_PANEL_S6E63J0X03) += panel-s6e63j0x03.o
diff --git a/drivers/gpu/drm/panel/panel-s6e63j0x03.c b/drivers/gpu/drm/panel/panel-s6e63j0x03.c
new file mode 100644
index 0000000..51cf1f6
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e63j0x03.c
@@ -0,0 +1,546 @@
+/*
+ * MIPI-DSI based S6E63J0X03 AMOLED lcd 1.63 inch panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * Inki Dae, <inki.dae-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <drm/drmP.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+
+#include <linux/of_gpio.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/backlight.h>
+
+#include <video/mipi_display.h>
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+#define READ_ID1 0xDA
+#define READ_ID2 0xDB
+#define READ_ID3 0xDC
+
+#define MCS_LEVEL2_KEY 0xf0
+#define MCS_MTP_KEY 0xf1
+#define MCS_MTP_SET3 0xd4
+
+#define MIN_BRIGHTNESS 0
+#define MAX_BRIGHTNESS 100
+#define DEFAULT_BRIGHTNESS 80
+
+#define GAMMA_LEVEL_NUM 30
+#define NUM_GAMMA_STEPS 9
+#define GAMMA_CMD_CNT 28
+
+struct s6e63j0x03 {
+ struct device *dev;
+ struct drm_panel panel;
+ struct backlight_device *bl_dev;
+
+ struct regulator_bulk_data supplies[2];
+ struct gpio_desc *reset_gpio;
+ u32 power_on_delay;
+ u32 power_off_delay;
+ u32 reset_delay;
+ u32 init_delay;
+ struct videomode vm;
+ unsigned int width_mm;
+ unsigned int height_mm;
+};
+
+static const unsigned char gamma_tbl[NUM_GAMMA_STEPS][GAMMA_CMD_CNT] = {
+ { /* Gamma 10 */
+ MCS_MTP_SET3,
+ 0x00, 0x00, 0x00, 0x7f, 0x7f, 0x7f, 0x52, 0x6b, 0x6f, 0x26,
+ 0x28, 0x2d, 0x28, 0x26, 0x27, 0x33, 0x34, 0x32, 0x36, 0x36,
+ 0x35, 0x00, 0xab, 0x00, 0xae, 0x00, 0xbf
+ },
+ { /* gamma 30 */
+ MCS_MTP_SET3,
+ 0x00, 0x00, 0x00, 0x70, 0x7f, 0x7f, 0x4e, 0x64, 0x69, 0x26,
+ 0x27, 0x2a, 0x28, 0x29, 0x27, 0x31, 0x32, 0x31, 0x35, 0x34,
+ 0x35, 0x00, 0xc4, 0x00, 0xca, 0x00, 0xdc
+ },
+ { /* gamma 60 */
+ MCS_MTP_SET3,
+ 0x00, 0x00, 0x00, 0x65, 0x7b, 0x7d, 0x5f, 0x67, 0x68, 0x2a,
+ 0x28, 0x29, 0x28, 0x2a, 0x27, 0x31, 0x2f, 0x30, 0x34, 0x33,
+ 0x34, 0x00, 0xd9, 0x00, 0xe4, 0x00, 0xf5
+ },
+ { /* gamma 90 */
+ MCS_MTP_SET3,
+ 0x00, 0x00, 0x00, 0x4d, 0x6f, 0x71, 0x67, 0x6a, 0x6c, 0x29,
+ 0x28, 0x28, 0x28, 0x29, 0x27, 0x30, 0x2e, 0x30, 0x32, 0x31,
+ 0x31, 0x00, 0xea, 0x00, 0xf6, 0x01, 0x09
+ },
+ { /* gamma 120 */
+ MCS_MTP_SET3,
+ 0x00, 0x00, 0x00, 0x3d, 0x66, 0x68, 0x69, 0x69, 0x69, 0x28,
+ 0x28, 0x27, 0x28, 0x28, 0x27, 0x30, 0x2e, 0x2f, 0x31, 0x31,
+ 0x30, 0x00, 0xf9, 0x01, 0x05, 0x01, 0x1b
+ },
+ { /* gamma 150 */
+ MCS_MTP_SET3,
+ 0x00, 0x00, 0x00, 0x31, 0x51, 0x53, 0x66, 0x66, 0x67, 0x28,
+ 0x29, 0x27, 0x28, 0x27, 0x27, 0x2e, 0x2d, 0x2e, 0x31, 0x31,
+ 0x30, 0x01, 0x04, 0x01, 0x11, 0x01, 0x29
+ },
+ { /* gamma 200 */
+ MCS_MTP_SET3,
+ 0x00, 0x00, 0x00, 0x2f, 0x4f, 0x51, 0x67, 0x65, 0x65, 0x29,
+ 0x2a, 0x28, 0x27, 0x25, 0x26, 0x2d, 0x2c, 0x2c, 0x30, 0x30,
+ 0x30, 0x01, 0x14, 0x01, 0x23, 0x01, 0x3b
+ },
+ { /* gamma 240 */
+ MCS_MTP_SET3,
+ 0x00, 0x00, 0x00, 0x2c, 0x4d, 0x50, 0x65, 0x63, 0x64, 0x2a,
+ 0x2c, 0x29, 0x26, 0x24, 0x25, 0x2c, 0x2b, 0x2b, 0x30, 0x30,
+ 0x30, 0x01, 0x1e, 0x01, 0x2f, 0x01, 0x47
+ },
+ { /* gamma 300 */
+ MCS_MTP_SET3,
+ 0x00, 0x00, 0x00, 0x38, 0x61, 0x64, 0x65, 0x63, 0x64, 0x28,
+ 0x2a, 0x27, 0x26, 0x23, 0x25, 0x2b, 0x2b, 0x2a, 0x30, 0x2f,
+ 0x30, 0x01, 0x2d, 0x01, 0x3f, 0x01, 0x57
+ }
+};
+
+static const unsigned char prepare_cmds1[][15] = {
+ { 3, 0xf2, 0x1c, 0x28 }, /* porch_adjustment */
+ { 4, 0xb5, 0x00, 0x02, 0x00 }, /* frame_freq */
+ { 5, 0x2a, 0x00, 0x14, 0x01, 0x53 }, /* mem_addr_set_0 */
+ { 5, 0x2b, 0x00, 0x00, 0x01, 0x3f }, /* mem_addr_set_1 */
+ { 14, 0xf8, 0x08, 0x08, 0x08, 0x17, /* ltps_timming_set_0_60hz */
+ 0x00, 0x2a, 0x02, 0x26,
+ 0x00, 0x00, 0x02, 0x00, 0x00 },
+ { 2, 0xf7, 0x02 }, /* ltps_timming_set_1 */
+ { 2, 0xb0, 0x01 }, /* param_pos_te_edge */
+ { 2, 0xe2, 0x0f }, /* te_rising_edge */
+ { 2, 0xb0, 0x00 }, /* param_pos_default */
+ { 1, MIPI_DCS_EXIT_SLEEP_MODE },
+};
+
+static const unsigned char prepare_cmds2[][4] = {
+ { 3, 0xb1, 0x00, 0x09 }, /* elvss_cond */
+ { 2, 0x36, 0x40 }, /* set_pos */
+ { 2, 0x51, 0xff }, /* white_brightness_default */
+ { 2, 0x53, 0x20 }, /* white_ctrl */
+ { 2, 0x55, 0x00 }, /* acl_off */
+ { 1, MIPI_DCS_SET_TEAR_ON },
+};
+
+
+static inline struct s6e63j0x03 *panel_to_s6e63j0x03(struct drm_panel *panel)
+{
+ return container_of(panel, struct s6e63j0x03, panel);
+}
+
+static inline ssize_t s6e63j0x03_dcs_write_seq(struct s6e63j0x03 *ctx,
+ const u8 *seq, const unsigned char len)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+
+ return mipi_dsi_dcs_write(dsi, seq, len);
+}
+
+static inline int s6e63j0x03_enable_lv2_command(struct s6e63j0x03 *ctx)
+{
+ unsigned char seq[] = { MCS_LEVEL2_KEY, 0x5a, 0x5a };
+
+ return s6e63j0x03_dcs_write_seq(ctx, seq, ARRAY_SIZE(seq));
+}
+
+static inline int s6e63j0x03_apply_mtp_key(struct s6e63j0x03 *ctx, bool on)
+{
+ unsigned char seq1[3] = { MCS_MTP_KEY, 0x5a, 0x5a };
+ unsigned char seq2[3] = { MCS_MTP_KEY, 0xa5, 0xa5 };
+
+ return s6e63j0x03_dcs_write_seq(ctx, on ? seq1 : seq2,
+ ARRAY_SIZE(seq1));
+}
+
+static int s6e63j0x03_read_mtp_id(struct s6e63j0x03 *ctx)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+ unsigned char cmds[3] = { READ_ID1, READ_ID2, READ_ID3 };
+ unsigned char id[3];
+ int ret;
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ ret = mipi_dsi_dcs_read(dsi, cmds[i], &id[i], 1);
+
+ if (ret < 0)
+ return ret;
+ }
+
+ dev_info(ctx->dev, "ID: 0x%02x, 0x%02x, 0x%02x\n", id[0], id[1], id[2]);
+
+ return 0;
+}
+
+static int s6e63j0x03_power_on(struct s6e63j0x03 *ctx)
+{
+ int ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+ if (ret < 0)
+ return ret;
+
+ msleep(ctx->power_on_delay);
+
+ gpiod_set_value(ctx->reset_gpio, 0);
+ usleep_range(1000, 2000);
+ gpiod_set_value(ctx->reset_gpio, 1);
+
+ usleep_range(ctx->reset_delay * 1000, (ctx->reset_delay + 1) * 1000);
+
+ return 0;
+}
+
+static int s6e63j0x03_power_off(struct s6e63j0x03 *ctx)
+{
+ int ret;
+
+ gpiod_set_value(ctx->reset_gpio, 0);
+
+ ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int s6e63j0x03_get_brightness(struct backlight_device *bl_dev)
+{
+ return bl_dev->props.brightness;
+}
+
+static unsigned int s6e63j0x03_get_brightness_index(unsigned int brightness)
+{
+ unsigned int index;
+
+ index = brightness / (MAX_BRIGHTNESS / NUM_GAMMA_STEPS);
+
+ if (index >= NUM_GAMMA_STEPS)
+ index = NUM_GAMMA_STEPS - 1;
+
+ return index;
+}
+
+static int s6e63j0x03_update_gamma(struct s6e63j0x03 *ctx,
+ unsigned int brightness)
+{
+ struct backlight_device *bl_dev = ctx->bl_dev;
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+ unsigned int index = s6e63j0x03_get_brightness_index(brightness);
+ int ret;
+
+ ret = s6e63j0x03_apply_mtp_key(ctx, true);
+ if (ret < 0)
+ return ret;
+
+ ret = mipi_dsi_dcs_write(dsi, gamma_tbl[index], GAMMA_CMD_CNT);
+ if (ret < 0)
+ return ret;
+
+ ret = s6e63j0x03_apply_mtp_key(ctx, false);
+ if (ret < 0)
+ return ret;
+
+ bl_dev->props.brightness = brightness;
+
+ return 0;
+}
+
+static int s6e63j0x03_set_brightness(struct backlight_device *bl_dev)
+{
+ struct s6e63j0x03 *ctx = (struct s6e63j0x03 *)bl_get_data(bl_dev);
+ unsigned int brightness = bl_dev->props.brightness;
+ int ret;
+
+ if (brightness < MIN_BRIGHTNESS ||
+ brightness > bl_dev->props.max_brightness) {
+ dev_err(ctx->dev, "Invalid brightness: %u\n", brightness);
+ return -EINVAL;
+ }
+
+ if (bl_dev->props.power > FB_BLANK_NORMAL) {
+ dev_err(ctx->dev,
+ "panel must be at least in fb blank normal state\n");
+ return -EPERM;
+ }
+
+ ret = s6e63j0x03_update_gamma(ctx, brightness);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static const struct backlight_ops s6e63j0x03_bl_ops = {
+ .get_brightness = s6e63j0x03_get_brightness,
+ .update_status = s6e63j0x03_set_brightness,
+};
+
+static int s6e63j0x03_disable(struct drm_panel *panel)
+{
+ struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
+ struct backlight_device *bl_dev = ctx->bl_dev;
+ u8 seq[] = { MIPI_DCS_SET_DISPLAY_OFF };
+ int ret;
+
+ ret = s6e63j0x03_dcs_write_seq(ctx, seq, ARRAY_SIZE(seq));
+ if (ret > 0)
+ bl_dev->props.power = FB_BLANK_NORMAL;
+
+ return 0;
+}
+
+static int s6e63j0x03_unprepare(struct drm_panel *panel)
+{
+ struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
+ struct backlight_device *bl_dev = ctx->bl_dev;
+ u8 seq[] = { MIPI_DCS_ENTER_SLEEP_MODE };
+ int ret;
+
+ ret = s6e63j0x03_dcs_write_seq(ctx, seq, ARRAY_SIZE(seq));
+ if (ret < 0)
+ return ret;
+
+ msleep(ctx->power_off_delay);
+
+ ret = s6e63j0x03_power_off(ctx);
+ if (ret < 0)
+ return ret;
+
+ bl_dev->props.power = FB_BLANK_POWERDOWN;
+
+ return 0;
+}
+
+static int s6e63j0x03_prepare(struct drm_panel *panel)
+{
+ struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
+ struct backlight_device *bl_dev = ctx->bl_dev;
+ int ret;
+ int i;
+
+ ret = s6e63j0x03_power_on(ctx);
+ if (ret < 0)
+ return ret;
+
+ ret = s6e63j0x03_enable_lv2_command(ctx);
+ if (ret < 0)
+ return ret;
+
+ ret = s6e63j0x03_apply_mtp_key(ctx, true);
+ if (ret < 0)
+ return ret;
+
+ ret = s6e63j0x03_read_mtp_id(ctx);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < ARRAY_SIZE(prepare_cmds1); i++) {
+ ret = s6e63j0x03_dcs_write_seq(ctx, &prepare_cmds1[i][1],
+ prepare_cmds1[i][0]);
+ if (ret < 0)
+ return ret;
+ }
+
+ msleep(120);
+
+ for (i = 0; i < ARRAY_SIZE(prepare_cmds2); i++) {
+ ret = s6e63j0x03_dcs_write_seq(ctx, &prepare_cmds2[i][1],
+ prepare_cmds2[i][0]);
+ if (ret < 0)
+ return ret;
+ }
+
+ ret = s6e63j0x03_apply_mtp_key(ctx, false);
+ if (ret < 0)
+ return ret;
+
+ bl_dev->props.power = FB_BLANK_NORMAL;
+
+ return 0;
+}
+
+static int s6e63j0x03_enable(struct drm_panel *panel)
+{
+ struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
+ struct backlight_device *bl_dev = ctx->bl_dev;
+ u8 seq[] = { MIPI_DCS_SET_DISPLAY_ON };
+ int ret;
+
+ ret = s6e63j0x03_dcs_write_seq(ctx, seq, ARRAY_SIZE(seq));
+ if (ret > 0)
+ bl_dev->props.power = FB_BLANK_UNBLANK;
+
+ return 0;
+}
+
+static int s6e63j0x03_get_modes(struct drm_panel *panel)
+{
+ struct drm_connector *connector = panel->connector;
+ struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
+ struct drm_display_mode *mode;
+
+ mode = drm_mode_create(connector->dev);
+ if (!mode) {
+ DRM_ERROR("failed to create a new display mode\n");
+ return 0;
+ }
+
+ drm_display_mode_from_videomode(&ctx->vm, mode);
+ mode->width_mm = ctx->width_mm;
+ mode->height_mm = ctx->height_mm;
+ connector->display_info.width_mm = mode->width_mm;
+ connector->display_info.height_mm = mode->height_mm;
+
+ mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+ drm_mode_probed_add(connector, mode);
+
+ return 1;
+}
+
+static const struct drm_panel_funcs s6e63j0x03_funcs = {
+ .disable = s6e63j0x03_disable,
+ .unprepare = s6e63j0x03_unprepare,
+ .prepare = s6e63j0x03_prepare,
+ .enable = s6e63j0x03_enable,
+ .get_modes = s6e63j0x03_get_modes,
+};
+
+static int s6e63j0x03_parse_dt(struct s6e63j0x03 *ctx)
+{
+ struct device *dev = ctx->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ ret = of_get_videomode(np, &ctx->vm, 0);
+ if (ret < 0)
+ return ret;
+
+ of_property_read_u32(np, "power-on-delay", &ctx->power_on_delay);
+ of_property_read_u32(np, "power-off-delay", &ctx->power_off_delay);
+ of_property_read_u32(np, "reset-delay", &ctx->reset_delay);
+ of_property_read_u32(np, "init-delay", &ctx->init_delay);
+ of_property_read_u32(np, "panel-width-mm", &ctx->width_mm);
+ of_property_read_u32(np, "panel-height-mm", &ctx->height_mm);
+
+ return ret;
+}
+
+static int s6e63j0x03_probe(struct mipi_dsi_device *dsi)
+{
+ struct device *dev = &dsi->dev;
+ struct s6e63j0x03 *ctx;
+ int ret;
+
+ ctx = devm_kzalloc(dev, sizeof(struct s6e63j0x03), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ mipi_dsi_set_drvdata(dsi, ctx);
+
+ ctx->dev = dev;
+
+ dsi->lanes = 1;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->mode_flags = MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_BURST;
+
+ ret = s6e63j0x03_parse_dt(ctx);
+ if (ret < 0)
+ return ret;
+
+ ctx->supplies[0].supply = "vdd3";
+ ctx->supplies[1].supply = "vci";
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
+ ctx->supplies);
+ if (ret < 0) {
+ dev_err(dev, "failed to get regulators: %d\n", ret);
+ return ret;
+ }
+
+ ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(ctx->reset_gpio)) {
+ dev_err(dev, "cannot get reset-gpio: %ld\n",
+ PTR_ERR(ctx->reset_gpio));
+ return PTR_ERR(ctx->reset_gpio);
+ }
+
+ drm_panel_init(&ctx->panel);
+ ctx->panel.dev = dev;
+ ctx->panel.funcs = &s6e63j0x03_funcs;
+
+ ctx->bl_dev = backlight_device_register("s6e63j0x03", dev, ctx,
+ &s6e63j0x03_bl_ops, NULL);
+ if (IS_ERR(ctx->bl_dev)) {
+ dev_err(dev, "failed to register backlight device\n");
+ return PTR_ERR(ctx->bl_dev);
+ }
+
+ ctx->bl_dev->props.max_brightness = MAX_BRIGHTNESS;
+ ctx->bl_dev->props.brightness = DEFAULT_BRIGHTNESS;
+ ctx->bl_dev->props.power = FB_BLANK_POWERDOWN;
+
+
+ ret = drm_panel_add(&ctx->panel);
+ if (ret < 0)
+ goto unregister_backlight;
+
+ ret = mipi_dsi_attach(dsi);
+ if (ret < 0)
+ goto remove_panel;
+
+ return ret;
+
+remove_panel:
+ drm_panel_remove(&ctx->panel);
+
+unregister_backlight:
+ backlight_device_unregister(ctx->bl_dev);
+
+ return ret;
+}
+
+static int s6e63j0x03_remove(struct mipi_dsi_device *dsi)
+{
+ struct s6e63j0x03 *ctx = mipi_dsi_get_drvdata(dsi);
+
+ mipi_dsi_detach(dsi);
+ drm_panel_remove(&ctx->panel);
+
+ backlight_device_unregister(ctx->bl_dev);
+
+ return 0;
+}
+
+static const struct of_device_id s6e63j0x03_of_match[] = {
+ { .compatible = "samsung,s6e63j0x03" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, s6e63j0x03_of_match);
+
+static struct mipi_dsi_driver s6e63j0x03_driver = {
+ .probe = s6e63j0x03_probe,
+ .remove = s6e63j0x03_remove,
+ .driver = {
+ .name = "panel_s6e63j0x03",
+ .of_match_table = s6e63j0x03_of_match,
+ },
+};
+module_mipi_dsi_driver(s6e63j0x03_driver);
+
+MODULE_AUTHOR("Inki Dae <inki.dae-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
+MODULE_DESCRIPTION("MIPI-DSI based s6e8aa0 AMOLED LCD Panel Driver");
+MODULE_LICENSE("GPL v2");
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 41+ messages in thread