From: Stephen Boyd <sboyd@codeaurora.org>
To: James Liao <jamesjj.liao@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Mike Turquette <mturquette@baylibre.com>,
Heiko Stubner <heiko@sntech.de>,
srv_heupstream@mediatek.com, Daniel Kurtz <djkurtz@chromium.org>,
Ricky Liang <jcliang@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
Sascha Hauer <kernel@pengutronix.de>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org
Subject: Re: [PATCH v3 2/3] clk: mediatek: Fix calculation of PLL rate settings
Date: Fri, 17 Jul 2015 17:47:53 -0700 [thread overview]
Message-ID: <20150718004753.GW30412@codeaurora.org> (raw)
In-Reply-To: <1436517574-17895-3-git-send-email-jamesjj.liao@mediatek.com>
On 07/10, James Liao wrote:
> Avoid u32 overflow when calculate post divider setting, and
> increase the max post divider setting from 3 (/8) to 4 (/16).
>
> Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-07-18 0:47 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-10 8:39 [PATCH v3 0/3] Fixes for MT8173 PLLs James Liao
2015-07-10 8:39 ` [PATCH v3 1/3] clk: mediatek: Fix PLL registers setting flow James Liao
[not found] ` <1436517574-17895-2-git-send-email-jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2015-07-18 0:47 ` Stephen Boyd
2015-07-10 8:39 ` [PATCH v3 2/3] clk: mediatek: Fix calculation of PLL rate settings James Liao
2015-07-18 0:47 ` Stephen Boyd [this message]
2015-07-10 8:39 ` [PATCH v3 3/3] clk: mediatek: Add MT8173 MMPLL change rate support James Liao
2015-07-18 0:47 ` Stephen Boyd
[not found] ` <1436517574-17895-1-git-send-email-jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2015-07-13 5:45 ` [PATCH v3 0/3] Fixes for MT8173 PLLs Sascha Hauer
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