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From: Bjorn Helgaas <bhelgaas@google.com>
To: Zhou Wang <wangzhou1@hisilicon.com>
Cc: Jingoo Han <jg1.han@samsung.com>,
	Pratyush Anand <pratyush.anand@gmail.com>,
	Arnd Bergmann <arnd@arndb.de>,
	gabriele.paoloni@huawei.com, lorenzo.pieralisi@arm.com,
	James Morse <james.morse@arm.com>,
	Liviu.Dudau@arm.com, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	yuanzhichang@hisilicon.com, zhudacai@hisilicon.com,
	zhangjukuo@huawei.com, qiuzhenfa@hisilicon.com,
	liudongdong3@huawei.com, qiujiang@huawei.com,
	kangfenglong@huawei.com, liguozhu@hisilicon.com,
	Rob Herring <robh@kernel.org>
Subject: Re: [PATCH v4 4/5] Documentation: DT: Add Hisilicon PCIe host binding
Date: Tue, 21 Jul 2015 18:02:05 -0500	[thread overview]
Message-ID: <20150721230205.GN21967@google.com> (raw)
In-Reply-To: <1437461323-3531-5-git-send-email-wangzhou1@hisilicon.com>

[+cc Rob]

On Tue, Jul 21, 2015 at 02:48:42PM +0800, Zhou Wang wrote:
> This patch adds related DTS binding document for Hisilicon PCIe host driver.
> 
> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>

If I merge this via my tree, I'm looking for an ack from Arnd and/or Rob
here.

> ---
>  .../devicetree/bindings/pci/hisilicon-pcie.txt     | 46 ++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> 
> diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> new file mode 100644
> index 0000000..6c9b827
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> @@ -0,0 +1,46 @@
> +Hisilicon PCIe host bridge DT description

Even the website at http://hisilicon.com isn't consistent, but there is
some indication that the correct capitalization would be "HiSilicon".
Since this is English text, feel free to capitalize it correctly here :)

Similarly, Synopsys seems to use "DesignWare," so I try to use that when
it makes sense.

> +Hisilicon PCIe host controller is based on Designware PCI core.
> +It shares common functions with PCIe Designware core driver and inherits
> +common properties defined in
> +Documentation/devicetree/bindings/pci/designware-pci.txt.
> +
> +Additional properties are described here:
> +
> +Required properties:
> +- compatible: Should contain "hisilicon,hip05-pcie".
> +- reg: Should contain rc_dbi, subctrl, config registers location and length.
> +- reg-names: Must include the following entries:
> +  "rc_dbi": controller configuration registers;
> +  "subctrl": whole PCIe hosts configuration registers;
> +  "config": PCIe configuration space registers.
> +- msi-parent: Should be its_pcie which is an its receiving MSI interrupts.

I guess "its" here is an abbreviation for something; if so, this would read
better as "... which is an ITS receiving ..."

> +- port-id: Should be 0, 1, 2 or 3.
> +
> +Optional properties:
> +- status: Either "ok" or "disabled".
> +- dma-coherent: Present if dma operations are coherent.

"if DMA operations"

> +
> +Example:
> +	pcie@0xb0080000 {
> +		compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
> +		reg = <0 0xb0080000 0 0x10000>, <0 0xb0000000 0 0x10000>,
> +		      <0x220 0x00000000 0 0x2000>;
> +		reg-names = "rc_dbi", "subctrl", "config";
> +		bus-range = <0  15>;
> +		msi-parent = <&its_pcie>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		device_type = "pci";
> +		dma-coherent;
> +		ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
> +		num-lanes = <8>;
> +		port-id = <1>;
> +		#interrupts-cells = <1>;
> +		interrupts-map-mask = <0xf800 0 0 7>;
> +		interrupts-map = <0x0 0 0 1 &mbigen_pcie 1 10
> +				  0x0 0 0 2 &mbigen_pcie 2 11
> +				  0x0 0 0 3 &mbigen_pcie 3 12
> +				  0x0 0 0 4 &mbigen_pcie 4 13>;
> +		status = "ok";
> +	};
> -- 
> 1.9.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
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  reply	other threads:[~2015-07-21 23:02 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-21  6:48 [PATCH v4 0/5] PCI: hisi: Add PCIe host support for Hisilicon Soc Hip05 Zhou Wang
2015-07-21  6:48 ` [PATCH v4 1/5] ARM/PCI: remove align_resource in pci_sys_data Zhou Wang
2015-07-21 22:44   ` Bjorn Helgaas
2015-07-22  2:00     ` Zhou Wang
2015-07-23 18:06   ` Lorenzo Pieralisi
2015-07-21  6:48 ` [PATCH v4 2/5] PCI: designware: Add ARM64 support Zhou Wang
2015-07-21  6:48 ` [PATCH v4 3/5] PCI: hisi: Add PCIe host support for Hisilicon Soc Hip05 Zhou Wang
2015-07-21 22:37   ` Bjorn Helgaas
2015-07-22  2:33     ` Zhou Wang
     [not found] ` <1437461323-3531-1-git-send-email-wangzhou1-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
2015-07-21  6:48   ` [PATCH v4 4/5] Documentation: DT: Add Hisilicon PCIe host binding Zhou Wang
2015-07-21 23:02     ` Bjorn Helgaas [this message]
     [not found]       ` <20150721230205.GN21967-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
2015-07-22  2:50         ` Zhou Wang
2015-07-21  6:48   ` [PATCH v4 5/5] MAINTAINERS: Add pcie-hisi maintainer Zhou Wang

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