[PATCH 1/2] MIPS: ath79: set irq ACK handler for ar7100-misc-intc irq chip

[PATCH 1/2] MIPS: ath79: set irq ACK handler for ar7100-misc-intc irq chip

[Alexander Couzens]

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
---
 arch/mips/ath79/irq.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index afb0096..dc76fa1 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -303,13 +303,20 @@ static int __init ath79_misc_intc_of_init(
 	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
 
-
 	irq_set_chained_handler(irq, ath79_misc_irq_handler);
 
 	return 0;
 }
-IRQCHIP_DECLARE(ath79_misc_intc, "qca,ar7100-misc-intc",
-		ath79_misc_intc_of_init);
+
+static int __init ar7100_misc_intc_of_init(
+	struct device_node *node, struct device_node *parent)
+{
+	ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
+	return ath79_misc_intc_of_init(node, parent);
+}
+
+IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
+		ar7100_misc_intc_of_init);
 
 static int __init ar79_cpu_intc_of_init(
 	struct device_node *node, struct device_node *parent)
-- 
2.4.0

[PATCH 2/2] MIPS: ath79: add irq chip ar7240-misc-intc

[Alexander Couzens]

The ar7240 misc irq chip use ack handler instead of ack_mask handler.
All new ath79 SoCs use the ar7240 misc irq chip

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
---
 .../interrupt-controller/qca,ath79-misc-intc.txt       | 18 +++++++++++++++++-
 arch/mips/ath79/irq.c                                  |  9 +++++++++
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
index 391717a..56ccaf3 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
@@ -4,7 +4,7 @@ The MISC interrupt controller is a secondary controller for lower priority
 interrupt.
 
 Required Properties:
-- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"
+- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar{7100,7240}-misc-intc"
   as fallback
 - reg: Base address and size of the controllers memory area
 - interrupt-parent: phandle of the parent interrupt controller.
@@ -13,6 +13,9 @@ Required Properties:
 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
 		     source, should be 1
 
+Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
+use ar7240 for all other SoCs.
+
 Please refer to interrupts.txt in this directory for details of the common
 Interrupt Controllers bindings used by client devices.
 
@@ -28,3 +31,16 @@ Example:
 		interrupt-controller;
 		#interrupt-cells = <1>;
 	};
+
+Another example:
+
+	interrupt-controller@18060010 {
+		compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
+		reg = <0x18060010 0x4>;
+
+		interrupt-parent = <&cpuintc>;
+		interrupts = <6>;
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index dc76fa1..bcb2fb32 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -315,8 +315,17 @@ static int __init ar7100_misc_intc_of_init(
 	return ath79_misc_intc_of_init(node, parent);
 }
 
+static int __init ar7240_misc_intc_of_init(
+	struct device_node *node, struct device_node *parent)
+{
+	ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+	return ath79_misc_intc_of_init(node, parent);
+}
+
 IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
 		ar7100_misc_intc_of_init);
+IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
+		ar7240_misc_intc_of_init);
 
 static int __init ar79_cpu_intc_of_init(
 	struct device_node *node, struct device_node *parent)
-- 
2.4.0

Re: [PATCH 1/2] MIPS: ath79: set irq ACK handler for ar7100-misc-intc irq chip

[Alban]

On Thu,  6 Aug 2015 12:43:24 +0200
Alexander Couzens <lynxis-qyMx1GtpvWw@public.gmane.org> wrote:

A log message would be nice. IMHO it should mention that the ACK
callbacks have been missed when introducing OF support.

> Signed-off-by: Alexander Couzens <lynxis-qyMx1GtpvWw@public.gmane.org>
> ---
>  arch/mips/ath79/irq.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
> index afb0096..dc76fa1 100644
> --- a/arch/mips/ath79/irq.c
> +++ b/arch/mips/ath79/irq.c
> @@ -303,13 +303,20 @@ static int __init ath79_misc_intc_of_init(
>  	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
>  	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
>  
> -

I would prefer to see this in another patch.


[...]

Alban
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Re: [PATCH 2/2] MIPS: ath79: add irq chip ar7240-misc-intc

[Alban]

On Thu,  6 Aug 2015 12:43:25 +0200
Alexander Couzens <lynxis-qyMx1GtpvWw@public.gmane.org> wrote:

> The ar7240 misc irq chip use ack handler instead of ack_mask handler.
> All new ath79 SoCs use the ar7240 misc irq chip

except the ar913x family according to the later documentation.

[...]

> --- a/arch/mips/ath79/irq.c
> +++ b/arch/mips/ath79/irq.c
> @@ -315,8 +315,17 @@ static int __init ar7100_misc_intc_of_init(
>  	return ath79_misc_intc_of_init(node, parent);
>  }
>  
> +static int __init ar7240_misc_intc_of_init(
> +	struct device_node *node, struct device_node *parent)
> +{
> +	ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
> +	return ath79_misc_intc_of_init(node, parent);
> +}
> +
>  IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
>  		ar7100_misc_intc_of_init);
> +IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
> +		ar7240_misc_intc_of_init);

It would be better to keep the same formatting as the surrounding code.
Could you keep the IRQCHIP_DECLARE() together with the init function
and remove the extra blank line?

Alban
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[PATCH 2/2] MIPS: ath79: add irq chip ar7240-misc-intc

[Alexander Couzens]

The ar7240 misc irq chip use ack handler
instead of ack_mask handler. All new ath79 chips use
the ar7240 misc irq chip

Signed-off-by: Alexander Couzens <lynxis-qyMx1GtpvWw@public.gmane.org>
---
 .../interrupt-controller/qca,ath79-misc-intc.txt       | 18 +++++++++++++++++-
 arch/mips/ath79/irq.c                                  | 10 ++++++++++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
index 391717a..56ccaf3 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
@@ -4,7 +4,7 @@ The MISC interrupt controller is a secondary controller for lower priority
 interrupt.
 
 Required Properties:
-- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"
+- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar{7100,7240}-misc-intc"
   as fallback
 - reg: Base address and size of the controllers memory area
 - interrupt-parent: phandle of the parent interrupt controller.
@@ -13,6 +13,9 @@ Required Properties:
 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
 		     source, should be 1
 
+Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
+use ar7240 for all other SoCs.
+
 Please refer to interrupts.txt in this directory for details of the common
 Interrupt Controllers bindings used by client devices.
 
@@ -28,3 +31,16 @@ Example:
 		interrupt-controller;
 		#interrupt-cells = <1>;
 	};
+
+Another example:
+
+	interrupt-controller@18060010 {
+		compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
+		reg = <0x18060010 0x4>;
+
+		interrupt-parent = <&cpuintc>;
+		interrupts = <6>;
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index 1917f55..7b38958 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -320,6 +320,16 @@ static int __init ar7100_misc_intc_of_init(
 IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
 		ar7100_misc_intc_of_init);
 
+static int __init ar7240_misc_intc_of_init(
+	struct device_node *node, struct device_node *parent)
+{
+	ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+	return ath79_misc_intc_of_init(node, parent);
+}
+
+IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
+		ar7240_misc_intc_of_init);
+
 static int __init ar79_cpu_intc_of_init(
 	struct device_node *node, struct device_node *parent)
 {
-- 
2.4.0

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Re: [PATCH 2/2] MIPS: ath79: add irq chip ar7240-misc-intc

[Alban]

On Thu,  3 Sep 2015 05:34:22 +0200
Alexander Couzens <lynxis-qyMx1GtpvWw@public.gmane.org> wrote:

> The ar7240 misc irq chip use ack handler
> instead of ack_mask handler. All new ath79 chips use
> the ar7240 misc irq chip
> 
> Signed-off-by: Alexander Couzens <lynxis-qyMx1GtpvWw@public.gmane.org>
> ---
>  .../interrupt-controller/qca,ath79-misc-intc.txt       | 18 +++++++++++++++++-
>  arch/mips/ath79/irq.c                                  | 10 ++++++++++
>  2 files changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
> index 391717a..56ccaf3 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
> @@ -4,7 +4,7 @@ The MISC interrupt controller is a secondary controller for lower priority
>  interrupt.
>  
>  Required Properties:
> -- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"
> +- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar{7100,7240}-misc-intc"
>    as fallback
>  - reg: Base address and size of the controllers memory area
>  - interrupt-parent: phandle of the parent interrupt controller.
> @@ -13,6 +13,9 @@ Required Properties:
>  - #interrupt-cells : Specifies the number of cells needed to encode interrupt
>  		     source, should be 1
>  
> +Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
> +use ar7240 for all other SoCs.
> +
>  Please refer to interrupts.txt in this directory for details of the common
>  Interrupt Controllers bindings used by client devices.
>  
> @@ -28,3 +31,16 @@ Example:
>  		interrupt-controller;
>  		#interrupt-cells = <1>;
>  	};
> +
> +Another example:
> +
> +	interrupt-controller@18060010 {
> +		compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
> +		reg = <0x18060010 0x4>;
> +
> +		interrupt-parent = <&cpuintc>;
> +		interrupts = <6>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +	};
> diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
> index 1917f55..7b38958 100644
> --- a/arch/mips/ath79/irq.c
> +++ b/arch/mips/ath79/irq.c
> @@ -320,6 +320,16 @@ static int __init ar7100_misc_intc_of_init(
>  IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
>  		ar7100_misc_intc_of_init);
>  
> +static int __init ar7240_misc_intc_of_init(
> +	struct device_node *node, struct device_node *parent)
> +{
> +	ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
> +	return ath79_misc_intc_of_init(node, parent);
> +}
> +
> +IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
> +		ar7240_misc_intc_of_init);
> +
>  static int __init ar79_cpu_intc_of_init(
>  	struct device_node *node, struct device_node *parent)
>  {

Acked-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
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Re: [PATCH 2/2] MIPS: ath79: add irq chip ar7240-misc-intc

[Mark Rutland]

On Thu, Sep 03, 2015 at 04:34:22AM +0100, Alexander Couzens wrote:
> The ar7240 misc irq chip use ack handler
> instead of ack_mask handler. All new ath79 chips use
> the ar7240 misc irq chip
> 
> Signed-off-by: Alexander Couzens <lynxis-qyMx1GtpvWw@public.gmane.org>
> ---
>  .../interrupt-controller/qca,ath79-misc-intc.txt       | 18 +++++++++++++++++-
>  arch/mips/ath79/irq.c                                  | 10 ++++++++++
>  2 files changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
> index 391717a..56ccaf3 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
> @@ -4,7 +4,7 @@ The MISC interrupt controller is a secondary controller for lower priority
>  interrupt.
>  
>  Required Properties:
> -- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"
> +- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar{7100,7240}-misc-intc"

Please list those strings separately, in full, such that they can be
searched for. Otherwise the addition looks fine to me.

Mark.

>    as fallback
>  - reg: Base address and size of the controllers memory area
>  - interrupt-parent: phandle of the parent interrupt controller.
> @@ -13,6 +13,9 @@ Required Properties:
>  - #interrupt-cells : Specifies the number of cells needed to encode interrupt
>  		     source, should be 1
>  
> +Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
> +use ar7240 for all other SoCs.
> +
>  Please refer to interrupts.txt in this directory for details of the common
>  Interrupt Controllers bindings used by client devices.
>  
> @@ -28,3 +31,16 @@ Example:
>  		interrupt-controller;
>  		#interrupt-cells = <1>;
>  	};
> +
> +Another example:
> +
> +	interrupt-controller@18060010 {
> +		compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
> +		reg = <0x18060010 0x4>;
> +
> +		interrupt-parent = <&cpuintc>;
> +		interrupts = <6>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +	};
> diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
> index 1917f55..7b38958 100644
> --- a/arch/mips/ath79/irq.c
> +++ b/arch/mips/ath79/irq.c
> @@ -320,6 +320,16 @@ static int __init ar7100_misc_intc_of_init(
>  IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
>  		ar7100_misc_intc_of_init);
>  
> +static int __init ar7240_misc_intc_of_init(
> +	struct device_node *node, struct device_node *parent)
> +{
> +	ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
> +	return ath79_misc_intc_of_init(node, parent);
> +}
> +
> +IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
> +		ar7240_misc_intc_of_init);
> +
>  static int __init ar79_cpu_intc_of_init(
>  	struct device_node *node, struct device_node *parent)
>  {
> -- 
> 2.4.0
> 
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[PATCH 2/2] MIPS: ath79: add irq chip ar7240-misc-intc

[Alexander Couzens]

The ar7240 misc irq chip use ack handler
instead of ack_mask handler. All new ath79 chips use
the ar7240 misc irq chip

Signed-off-by: Alexander Couzens <lynxis-qyMx1GtpvWw@public.gmane.org>
Acked-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
---
 .../interrupt-controller/qca,ath79-misc-intc.txt     | 20 ++++++++++++++++++--
 arch/mips/ath79/irq.c                                | 10 ++++++++++
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
index 391717a..ec96b1f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
@@ -4,8 +4,8 @@ The MISC interrupt controller is a secondary controller for lower priority
 interrupt.
 
 Required Properties:
-- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"
-  as fallback
+- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
+  "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
 - reg: Base address and size of the controllers memory area
 - interrupt-parent: phandle of the parent interrupt controller.
 - interrupts: Interrupt specifier for the controllers interrupt.
@@ -13,6 +13,9 @@ Required Properties:
 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
 		     source, should be 1
 
+Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
+use ar7240 for all other SoCs.
+
 Please refer to interrupts.txt in this directory for details of the common
 Interrupt Controllers bindings used by client devices.
 
@@ -28,3 +31,16 @@ Example:
 		interrupt-controller;
 		#interrupt-cells = <1>;
 	};
+
+Another example:
+
+	interrupt-controller@18060010 {
+		compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
+		reg = <0x18060010 0x4>;
+
+		interrupt-parent = <&cpuintc>;
+		interrupts = <6>;
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index c9c0124..fd58f8b 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -319,6 +319,16 @@ static int __init ar7100_misc_intc_of_init(
 IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
 		ar7100_misc_intc_of_init);
 
+static int __init ar7240_misc_intc_of_init(
+	struct device_node *node, struct device_node *parent)
+{
+	ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+	return ath79_misc_intc_of_init(node, parent);
+}
+
+IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
+		ar7240_misc_intc_of_init);
+
 static int __init ar79_cpu_intc_of_init(
 	struct device_node *node, struct device_node *parent)
 {
-- 
2.4.0

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Re: [PATCH 2/2] MIPS: ath79: add irq chip ar7240-misc-intc

[Thomas Gleixner]

On Sat, 19 Sep 2015, Alexander Couzens wrote:

> The ar7240 misc irq chip use ack handler
> instead of ack_mask handler. All new ath79 chips use
> the ar7240 misc irq chip
> 
> Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
> Acked-by: Alban Bedel <albeu@free.fr>
> ---
>  .../interrupt-controller/qca,ath79-misc-intc.txt     | 20 ++++++++++++++++++--
>  arch/mips/ath79/irq.c                                | 10 ++++++++++

That driver should probably move into drivers/irqchip.

Other than that.

Acked-by: Thomas Gleixner <tglx@linutronix.de>

Re: [PATCH 2/2] MIPS: ath79: add irq chip ar7240-misc-intc

[Ralf Baechle]

On Tue, Sep 22, 2015 at 12:24:26PM +0200, Thomas Gleixner wrote:

> > The ar7240 misc irq chip use ack handler
> > instead of ack_mask handler. All new ath79 chips use
> > the ar7240 misc irq chip
> > 
> > Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
> > Acked-by: Alban Bedel <albeu@free.fr>
> > ---
> >  .../interrupt-controller/qca,ath79-misc-intc.txt     | 20 ++++++++++++++++++--
> >  arch/mips/ath79/irq.c                                | 10 ++++++++++
> 
> That driver should probably move into drivers/irqchip.

Like a fair number of other irq.c type files in arch/mips that could
reasonably easily be rewritten to go to drivers/irqchip.

> Other than that.
> 
> Acked-by: Thomas Gleixner <tglx@linutronix.de>

Thanks, I replaced the previous version of this patch with this one.

  Ralf