From: Olof Johansson <olof@lixom.net>
To: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: arm@kernel.org, Russell King <linux@arm.linux.org.uk>,
devicetree@vger.kernel.org, Kumar Gala <galak@codeaurora.org>,
linux-kernel@vger.kernel.org,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
Date: Thu, 20 Aug 2015 18:28:48 -0700 [thread overview]
Message-ID: <20150821012848.GA4865@localhost> (raw)
In-Reply-To: <1439963366-4848-1-git-send-email-yamada.masahiro@socionext.com>
On Wed, Aug 19, 2015 at 02:49:26PM +0900, Masahiro Yamada wrote:
> This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
> document says that the bits[15:8] of the 3rd cell of the interrupts
> property represents PPI interrupt CPU mask. Because the timer
> interrupts are wired to all of the 4 cores, bits[15:8] should be set
> to 0xf.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
>
> Changes in v2:
> - Fix git-description
Thanks, applied.
-Olof
prev parent reply other threads:[~2015-08-21 1:28 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-19 5:49 [PATCH v2] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes Masahiro Yamada
2015-08-21 1:28 ` Olof Johansson [this message]
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