[PATCH 0/5] Add Marvell berlin4ct clk support

[PATCH 0/5] Add Marvell berlin4ct clk support

[Jisheng Zhang]

Add berlin4ct clk driver. The berlin4ct SoC contains:

two kinds of PLL: normal PLL and AVPLL. The normal PLL support is done.
The AVPLL support is in TODO list.

two kinds of clk: normal clk and gate clk. The normal clk supports changing
divider, selecting clock source, disabling/enabling etc. The gate clk only
supports disabling/enabling. Both are supported in this series.

Jisheng Zhang (5):
  clk: berlin: add common pll driver
  clk: berlin: add common clk driver for newer SoCs
  clk: berlin: add clk support for berlin4ct
  dt-bindings: add binding for marvell berlin4ct SoC
  arm64: dts: berlin4ct: add pll and clock nodes

 .../bindings/clock/marvell,berlin4ct.txt           |  38 +++++
 arch/arm64/boot/dts/marvell/berlin4ct.dtsi         |  38 +++++
 drivers/clk/berlin/Makefile                        |   2 +-
 drivers/clk/berlin/clk-berlin4ct.c                 | 164 +++++++++++++++++++++
 drivers/clk/berlin/clk.c                           | 147 ++++++++++++++++++
 drivers/clk/berlin/clk.h                           |  38 +++++
 drivers/clk/berlin/pll.c                           | 119 +++++++++++++++
 include/dt-bindings/clock/berlin4ct.h              |  56 +++++++
 8 files changed, 601 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/marvell,berlin4ct.txt
 create mode 100644 drivers/clk/berlin/clk-berlin4ct.c
 create mode 100644 drivers/clk/berlin/clk.c
 create mode 100644 drivers/clk/berlin/clk.h
 create mode 100644 drivers/clk/berlin/pll.c
 create mode 100644 include/dt-bindings/clock/berlin4ct.h

-- 
2.5.3

[PATCH 1/5] clk: berlin: add common pll driver

[Jisheng Zhang]

Add pll driver for Marvell SoCs newer than BG2, BG2CD, BG2Q.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/clk/berlin/Makefile |   2 +-
 drivers/clk/berlin/pll.c    | 119 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 120 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/berlin/pll.c

diff --git a/drivers/clk/berlin/Makefile b/drivers/clk/berlin/Makefile
index 2a36ab7..747700d 100644
--- a/drivers/clk/berlin/Makefile
+++ b/drivers/clk/berlin/Makefile
@@ -1,4 +1,4 @@
-obj-y += berlin2-avpll.o berlin2-pll.o berlin2-div.o
+obj-y += pll.o berlin2-avpll.o berlin2-pll.o berlin2-div.o
 obj-$(CONFIG_MACH_BERLIN_BG2)	+= bg2.o
 obj-$(CONFIG_MACH_BERLIN_BG2CD)	+= bg2.o
 obj-$(CONFIG_MACH_BERLIN_BG2Q)	+= bg2q.o
diff --git a/drivers/clk/berlin/pll.c b/drivers/clk/berlin/pll.c
new file mode 100644
index 0000000..9aad0b6
--- /dev/null
+++ b/drivers/clk/berlin/pll.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2015 Marvell Technology Group Ltd.
+ *
+ * Author: Jisheng Zhang <jszhang@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+
+#define PLL_CTRL0	0x0
+#define PLL_CTRL1	0x4
+#define PLL_CTRL2	0x8
+#define PLL_CTRL3	0xC
+#define PLL_CTRL4	0x10
+#define PLL_STATUS	0x14
+
+#define PLL_SOURCE_MAX	2
+
+struct berlin_pll {
+	struct clk_hw	hw;
+	void __iomem	*ctrl;
+	void __iomem	*bypass;
+	u8		bypass_shift;
+};
+
+#define to_berlin_pll(hw)       container_of(hw, struct berlin_pll, hw)
+
+static u8 vcodiv_berlin[] = {1, 2, 4, 8, 16, 32, 64, 128};
+
+static unsigned long berlin_pll_recalc_rate(struct clk_hw *hw,
+					    unsigned long parent_rate)
+{
+	u32 val, fbdiv, rfdiv, vcodivsel, bypass;
+	struct berlin_pll *pll = to_berlin_pll(hw);
+
+	bypass = readl_relaxed(pll->bypass);
+	if (bypass & (1 << pll->bypass_shift))
+		return parent_rate;
+
+	val = readl_relaxed(pll->ctrl + PLL_CTRL0);
+	fbdiv = (val >> 12) & 0x1FF;
+	rfdiv = (val >> 3) & 0x1FF;
+	val = readl_relaxed(pll->ctrl + PLL_CTRL1);
+	vcodivsel = (val >> 9) & 0x7;
+	return parent_rate * fbdiv * 4 / rfdiv /
+		vcodiv_berlin[vcodivsel];
+}
+
+static u8 berlin_pll_get_parent(struct clk_hw *hw)
+{
+	struct berlin_pll *pll = to_berlin_pll(hw);
+	u32 bypass = readl_relaxed(pll->bypass);
+
+	if (bypass & (1 << pll->bypass_shift))
+		return 1;
+	else
+		return 0;
+}
+
+static const struct clk_ops berlin_pll_ops = {
+	.recalc_rate	= berlin_pll_recalc_rate,
+	.get_parent	= berlin_pll_get_parent,
+};
+
+void __init berlin_pll_setup(struct device_node *np)
+{
+	struct clk_init_data init;
+	struct berlin_pll *pll;
+	const char *parent_names[PLL_SOURCE_MAX];
+	struct clk *clk;
+	int ret, num_parents;
+
+	num_parents = of_clk_get_parent_count(np);
+	if (num_parents <= 0 || num_parents > PLL_SOURCE_MAX)
+		return;
+
+	of_clk_parent_fill(np, parent_names, num_parents);
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (WARN_ON(!pll))
+		return;
+
+	pll->ctrl = of_iomap(np, 0);
+	pll->bypass = of_iomap(np, 1);
+	ret = of_property_read_u8(np, "bypass-shift", &pll->bypass_shift);
+	if (WARN_ON(!pll->ctrl || !pll->bypass || ret))
+		return;
+
+	init.name = np->name;
+	init.ops = &berlin_pll_ops;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	pll->hw.init = &init;
+
+	clk = clk_register(NULL, &pll->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return;
+
+	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
+	if (WARN_ON(ret))
+		return;
+}
+CLK_OF_DECLARE(berlin_pll, "marvell,berlin-pll", berlin_pll_setup);
-- 
2.5.3

[PATCH 2/5] clk: berlin: add common clk driver for newer SoCs

[Jisheng Zhang]

Add berlin-clk driver for Marvell SoCs newer than BG2, BG2CD, BG2Q.
berlin_clk_register() is provided for registering such kind of clk.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/clk/berlin/Makefile |   2 +-
 drivers/clk/berlin/clk.c    | 147 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/berlin/clk.h    |  38 ++++++++++++
 3 files changed, 186 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/berlin/clk.c
 create mode 100644 drivers/clk/berlin/clk.h

diff --git a/drivers/clk/berlin/Makefile b/drivers/clk/berlin/Makefile
index 747700d..741ba22 100644
--- a/drivers/clk/berlin/Makefile
+++ b/drivers/clk/berlin/Makefile
@@ -1,4 +1,4 @@
-obj-y += pll.o berlin2-avpll.o berlin2-pll.o berlin2-div.o
+obj-y += pll.o clk.o berlin2-avpll.o berlin2-pll.o berlin2-div.o
 obj-$(CONFIG_MACH_BERLIN_BG2)	+= bg2.o
 obj-$(CONFIG_MACH_BERLIN_BG2CD)	+= bg2.o
 obj-$(CONFIG_MACH_BERLIN_BG2Q)	+= bg2q.o
diff --git a/drivers/clk/berlin/clk.c b/drivers/clk/berlin/clk.c
new file mode 100644
index 0000000..6d64faf
--- /dev/null
+++ b/drivers/clk/berlin/clk.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2013 Marvell Technology Group Ltd.
+ *
+ * Author: Jisheng Zhang <jszhang@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+#define CLKEN		(1 << 0)
+#define CLKPLLSEL_MASK	7
+#define CLKPLLSEL_SHIFT	1
+#define CLKPLLSWITCH	(1 << 4)
+#define CLKSWITCH	(1 << 5)
+#define CLKD3SWITCH	(1 << 6)
+#define CLKSEL_MASK	7
+#define CLKSEL_SHIFT	7
+
+struct berlin_clk {
+	struct clk_hw hw;
+	void __iomem *base;
+};
+
+#define to_berlin_clk(hw)	container_of(hw, struct berlin_clk, hw)
+
+static u8 clk_div[] = {1, 2, 4, 6, 8, 12, 1, 1};
+
+static unsigned long berlin_clk_recalc_rate(struct clk_hw *hw,
+					unsigned long parent_rate)
+{
+	u32 val, divider;
+	struct berlin_clk *clk = to_berlin_clk(hw);
+
+	val = readl_relaxed(clk->base);
+	if (val & CLKD3SWITCH)
+		divider = 3;
+	else {
+		if (val & CLKSWITCH) {
+			val >>= CLKSEL_SHIFT;
+			val &= CLKSEL_MASK;
+			divider = clk_div[val];
+		} else
+			divider = 1;
+	}
+
+	return parent_rate / divider;
+}
+
+static u8 berlin_clk_get_parent(struct clk_hw *hw)
+{
+	u32 val;
+	struct berlin_clk *clk = to_berlin_clk(hw);
+
+	val = readl_relaxed(clk->base);
+	if (val & CLKPLLSWITCH) {
+		val >>= CLKPLLSEL_SHIFT;
+		val &= CLKPLLSEL_MASK;
+		return val;
+	}
+
+	return 0;
+}
+
+static int berlin_clk_enable(struct clk_hw *hw)
+{
+	u32 val;
+	struct berlin_clk *clk = to_berlin_clk(hw);
+
+	val = readl_relaxed(clk->base);
+	val |= CLKEN;
+	writel_relaxed(val, clk->base);
+
+	return 0;
+}
+
+static void berlin_clk_disable(struct clk_hw *hw)
+{
+	u32 val;
+	struct berlin_clk *clk = to_berlin_clk(hw);
+
+	val = readl_relaxed(clk->base);
+	val &= ~CLKEN;
+	writel_relaxed(val, clk->base);
+}
+
+static int berlin_clk_is_enabled(struct clk_hw *hw)
+{
+	u32 val;
+	struct berlin_clk *clk = to_berlin_clk(hw);
+
+	val = readl_relaxed(clk->base);
+	val &= CLKEN;
+
+	return val ? 1 : 0;
+}
+
+static const struct clk_ops berlin_clk_ops = {
+	.recalc_rate	= berlin_clk_recalc_rate,
+	.get_parent	= berlin_clk_get_parent,
+	.enable		= berlin_clk_enable,
+	.disable	= berlin_clk_disable,
+	.is_enabled	= berlin_clk_is_enabled,
+};
+
+struct clk * __init berlin_clk_register(const char *name, int num_parents,
+			const char **parent_names, unsigned long flags,
+			void __iomem *base)
+{
+	struct clk *clk;
+	struct berlin_clk *bclk;
+	struct clk_init_data init;
+
+	bclk = kzalloc(sizeof(*bclk), GFP_KERNEL);
+	if (!bclk)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = name;
+	init.ops = &berlin_clk_ops;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+	init.flags = flags;
+
+	bclk->base = base;
+	bclk->hw.init = &init;
+
+	clk = clk_register(NULL, &bclk->hw);
+	if (IS_ERR(clk))
+		kfree(bclk);
+
+	return clk;
+}
diff --git a/drivers/clk/berlin/clk.h b/drivers/clk/berlin/clk.h
new file mode 100644
index 0000000..502689e
--- /dev/null
+++ b/drivers/clk/berlin/clk.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2015 Marvell Technology Group Ltd.
+ *
+ * Author: Jisheng Zhang <jszhang@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __BERLIN_CLK_H
+#define __BERLIN_CLK_H
+
+struct gateclk_desc {
+	const char	*name;
+	const char	*parent_name;
+	u8		bit_idx;
+	unsigned long	flags;
+};
+
+struct clk_desc {
+	const char	*name;
+	u32		offset;
+	unsigned long	flags;
+};
+
+struct clk * __init berlin_clk_register(const char *name, int num_parents,
+			const char **parent_names, unsigned long flags,
+			void __iomem *base);
+#endif
-- 
2.5.3

[PATCH 3/5] clk: berlin: add clk support for berlin4ct

[Jisheng Zhang]

This patch supports the gate-clk and berlin-clk in berlin4ct SoC.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 drivers/clk/berlin/Makefile        |   2 +-
 drivers/clk/berlin/clk-berlin4ct.c | 164 +++++++++++++++++++++++++++++++++++++
 2 files changed, 165 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/berlin/clk-berlin4ct.c

diff --git a/drivers/clk/berlin/Makefile b/drivers/clk/berlin/Makefile
index 741ba22..fe29dd3 100644
--- a/drivers/clk/berlin/Makefile
+++ b/drivers/clk/berlin/Makefile
@@ -1,4 +1,4 @@
-obj-y += pll.o clk.o berlin2-avpll.o berlin2-pll.o berlin2-div.o
+obj-y += pll.o clk.o clk-berlin4ct.o berlin2-avpll.o berlin2-pll.o berlin2-div.o
 obj-$(CONFIG_MACH_BERLIN_BG2)	+= bg2.o
 obj-$(CONFIG_MACH_BERLIN_BG2CD)	+= bg2.o
 obj-$(CONFIG_MACH_BERLIN_BG2Q)	+= bg2q.o
diff --git a/drivers/clk/berlin/clk-berlin4ct.c b/drivers/clk/berlin/clk-berlin4ct.c
new file mode 100644
index 0000000..b9d4a9b
--- /dev/null
+++ b/drivers/clk/berlin/clk-berlin4ct.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2015 Marvell Technology Group Ltd.
+ *
+ * Author: Jisheng Zhang <jszhang@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+#define CLK_SOURCE_MAX	5
+
+static struct clk_onecell_data gateclk_data;
+static struct clk_onecell_data clk_data;
+
+static DEFINE_SPINLOCK(lock);
+
+static const struct gateclk_desc berlin4ct_gates[] __initconst = {
+	{ "tspsysclk",		"perifsysclk",	0 },
+	{ "usb0coreclk",	"perifsysclk",	1 },
+	{ "zspsysclk",		"perifsysclk",	2 },
+	{ "sdiosysclk",		"perifsysclk",	3 },
+	{ "ethcoreclk",		"perifsysclk",	4 },
+	{ "pcie0sys",		"perifsysclk",	6 },
+	{ "sata0core",		"perifsysclk",	7 },
+	{ "nfcsysclk",		"perifsysclk",	8 },
+	{ "emmcsysclk",		"perifsysclk",	9 },
+	{ "ihb0sysclk",		"perifsysclk",	10 },
+};
+
+static const struct clk_desc berlin4ct_descs[] __initconst = {
+	{ "cpufastrefclk",	0x0 },
+	{ "memfastrefclk",	0x4 },
+	{ "cfgclk",		0x20,	CLK_IGNORE_UNUSED },
+	{ "perifsysclk",	0x24,	CLK_IGNORE_UNUSED },
+	{ "hbclk",		0x28 },
+	{ "atbclk",		0x2c },
+	{ "decoderclk",		0x40 },
+	{ "decoderm3clk",	0x44 },
+	{ "decoderpcubeclk",	0x48 },
+	{ "encoderclk",		0x4c },
+	{ "ovpcoreclk",		0x50 },
+	{ "gfx2dcoreclk",	0x60 },
+	{ "gfx3dcoreclk",	0x64 },
+	{ "gfx3dshclk",		0x68 },
+	{ "gfx3dsysclk",	0x6c },
+	{ "gfx2dsysclk",	0x70 },
+	{ "aviosysclk",		0x80 },
+	{ "vppsysclk",		0x84 },
+	{ "eddcclk",		0x88 },
+	{ "aviobiuclk",		0x8c },
+	{ "zspclk",		0xa0 },
+	{ "tspclk",		0xc0 },
+	{ "tsprefclk",		0xc4 },
+	{ "ndsclk",		0xc8 },
+	{ "nocsclk",		0xcc },
+	{ "apbcoreclk",		0xd0,	CLK_IGNORE_UNUSED },
+	{ "emmcclk",		0xe0 },
+	{ "sd0clk",		0xe4 },
+	{ "sd1clk",		0xe8 },
+	{ "dllmstrefclk",	0xec },
+	{ "gethrgmiiclk",	0xf0 },
+	{ "gethrgmiisysclk",	0xf4 },
+	{ "usim0clk",		0x100 },
+	{ "pcietestclk",	0x110 },
+	{ "usb2testclk",	0x120 },
+	{ "usb3testclk",	0x124 },
+	{ "usb3coreclk",	0x128 },
+	{ "nfceccclk",		0x130 },
+	{ "bcmclk",		0x140 },
+};
+
+static void __init berlin4ct_gateclk_setup(struct device_node *np)
+{
+	int i, n, ret;
+	void __iomem *base;
+	struct clk **clks;
+
+	base = of_iomap(np, 0);
+	if (WARN_ON(!base))
+		return;
+
+	n = ARRAY_SIZE(berlin4ct_gates);
+	clks = kzalloc(n * sizeof(struct clk *), GFP_KERNEL);
+	if (WARN_ON(!clks))
+		return;
+
+	for (i = 0; i < n; i++) {
+		clks[i] = clk_register_gate(NULL, berlin4ct_gates[i].name,
+				berlin4ct_gates[i].parent_name,
+				berlin4ct_gates[i].flags, base,
+				berlin4ct_gates[i].bit_idx, 0, &lock);
+		WARN_ON(IS_ERR(clks[i]));
+	}
+
+	gateclk_data.clks = clks;
+	gateclk_data.clk_num = i;
+
+	ret = of_clk_add_provider(np, of_clk_src_onecell_get,
+				  &gateclk_data);
+	if (WARN_ON(ret))
+		return;
+
+}
+CLK_OF_DECLARE(berlin4ct_gateclk, "marvell,berlin4ct-gateclk",
+	       berlin4ct_gateclk_setup);
+
+static void __init berlin4ct_clk_setup(struct device_node *np)
+{
+	int i, n, ret, num_parents;
+	void __iomem *base;
+	struct clk **clks;
+	const char *parent_names[CLK_SOURCE_MAX];
+
+	num_parents = of_clk_get_parent_count(np);
+	if (num_parents <= 0 || num_parents > CLK_SOURCE_MAX)
+		return;
+
+	of_clk_parent_fill(np, parent_names, num_parents);
+
+	base = of_iomap(np, 0);
+	if (WARN_ON(!base))
+		return;
+
+	n = ARRAY_SIZE(berlin4ct_descs);
+	clks = kzalloc(n * sizeof(struct clk *), GFP_KERNEL);
+	if (WARN_ON(!clks))
+		return;
+
+	for (i = 0; i < n; i++) {
+		clks[i] = berlin_clk_register(berlin4ct_descs[i].name,
+				num_parents, parent_names,
+				berlin4ct_descs[i].flags,
+				base + berlin4ct_descs[i].offset);
+		WARN_ON(IS_ERR(clks[i]));
+	}
+
+	clk_data.clks = clks;
+	clk_data.clk_num = i;
+
+	ret = of_clk_add_provider(np, of_clk_src_onecell_get,
+				  &clk_data);
+	if (WARN_ON(ret))
+		return;
+
+}
+CLK_OF_DECLARE(berlin4ct_clk, "marvell,berlin4ct-clk",
+	       berlin4ct_clk_setup);
-- 
2.5.3

[PATCH 4/5] dt-bindings: add binding for marvell berlin4ct SoC

[Jisheng Zhang]

This adds a dt-binding include for Marvell berlin4ct clock IDs.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 .../bindings/clock/marvell,berlin4ct.txt           | 38 +++++++++++++++
 include/dt-bindings/clock/berlin4ct.h              | 56 ++++++++++++++++++++++
 2 files changed, 94 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/marvell,berlin4ct.txt
 create mode 100644 include/dt-bindings/clock/berlin4ct.h

diff --git a/Documentation/devicetree/bindings/clock/marvell,berlin4ct.txt b/Documentation/devicetree/bindings/clock/marvell,berlin4ct.txt
new file mode 100644
index 0000000..a489473
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/marvell,berlin4ct.txt
@@ -0,0 +1,38 @@
+* Marvell berlin4ct Clock Controllers
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The berlin4ct clock subsystem generates and supplies clock to various
+controllers within the berlin4ct SoC. The berlin4ct contains 3 clock controller
+blocks: pll, gateclk, berlin-clk.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,berlin-pll" - pll compatible
+  - "marvell,berlin4ct-clk" - berlin clk compatible
+  - "marvell,berlin4ct-gateclk" - gateclk compatible
+- reg: physical base address of the clock controller and length of memory mapped
+  region. For pll, the second reg defines the bypass register base address and
+  length of memory mapped region.
+- #clock-cells: for pll should 0, for gateclk and berlin clk should be 1.
+- #bypass-shift: the bypass bit in bypass register.
+
+Example:
+
+syspll: syspll {
+	compatible = "marvell,berlin-pll";
+	reg = <0xea0200 0x14>, <0xea0710 4>;
+	#clock-cells = <0>;
+	clocks = <&osc>;
+	bypass-shift = /bits/ 8 <0>;
+};
+
+clk: clk {
+	compatible = "marvell,berlin4ct-clk";
+	reg = <0xea0720 0x144>;
+	#clock-cells = <1>;
+	clocks = <&syspll>;
+};
diff --git a/include/dt-bindings/clock/berlin4ct.h b/include/dt-bindings/clock/berlin4ct.h
new file mode 100644
index 0000000..f742f6b
--- /dev/null
+++ b/include/dt-bindings/clock/berlin4ct.h
@@ -0,0 +1,56 @@
+/*
+ * Berlin2 BG2Q clock tree IDs
+ */
+
+/* GATE CLK */
+#define GATECLK_TSPSYS		0
+#define GATECLK_USB0CORE	1
+#define GATECLK_ZSPSYS		2
+#define GATECLK_SDIOSYS		3
+#define GATECLK_ETHCORE		4
+#define GATECLK_PCIE0SYS	5
+#define GATECLK_SATA0CORE	6
+#define GATECLK_NFCSYS		7
+#define GATECLK_EMMCSYS		8
+#define GATECLK_IHB0SYS		9
+
+/* BERLIN CLK */
+#define CLK_CPUFASTREF		0
+#define CLK_MEMFASTREF		1
+#define CLK_CFG			2
+#define CLK_PERIFSYS		3
+#define CLK_HB			4
+#define CLK_ATB			5
+#define CLK_DECODER		6
+#define CLK_DECODERM3		7
+#define CLK_DECODERPCUBE	8
+#define CLK_ENCODER		9
+#define CLK_OVPCORE		10
+#define CLK_GFX2DCORE		11
+#define CLK_GFX3DCORE		12
+#define CLK_GFX3DSH		13
+#define CLK_GFX3DSYS		14
+#define CLK_GFX2DSYS		15
+#define CLK_AVIOSYS		16
+#define CLK_VPPSYS		17
+#define CLK_EDDC		18
+#define CLK_AVIOBIU		19
+#define CLK_ZSP			20
+#define CLK_TSP			21
+#define CLK_TSPREF		22
+#define CLK_NDS			23
+#define CLK_NOCS		24
+#define CLK_APBCORE		25
+#define CLK_EMMC		26
+#define CLK_SD0			27
+#define CLK_SD1			28
+#define CLK_DLLMSTREF		29
+#define CLK_GETHRGMII		30
+#define CLK_GETHRGMIISYS	31
+#define CLK_USIM0		32
+#define CLK_PCIETEST		33
+#define CLK_USB2TEST		34
+#define CLK_USB3TEST		35
+#define CLK_USB3CORE		36
+#define CLK_NFCECC		37
+#define CLK_BCM			38
-- 
2.5.3

[PATCH 5/5] arm64: dts: berlin4ct: add pll and clock nodes

[Jisheng Zhang]

Add syspll, mempll, cpupll, gate-clk and berlin-clk nodes.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
 arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 38 ++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
index e9409ec..92a1cf2 100644
--- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
+++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
@@ -42,6 +42,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/clock/berlin4ct.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -135,6 +136,22 @@
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
+		cpupll: cpupll {
+			compatible = "marvell,berlin-pll";
+			reg = <0x922000 0x14>, <0xea0710 4>;
+			#clock-cells = <0>;
+			clocks = <&osc>, <&clk CLK_CPUFASTREF>;
+			bypass-shift = /bits/ 8 <2>;
+		};
+
+		mempll: mempll {
+			compatible = "marvell,berlin-pll";
+			reg = <0x940034 0x14>, <0xea0710 4>;
+			#clock-cells = <0>;
+			clocks = <&osc>, <&clk CLK_MEMFASTREF>;
+			bypass-shift = /bits/ 8 <1>;
+		};
+
 		apb@e80000 {
 			compatible = "simple-bus";
 			#address-cells = <1>;
@@ -225,6 +242,27 @@
 			};
 		};
 
+		syspll: syspll {
+			compatible = "marvell,berlin-pll";
+			reg = <0xea0200 0x14>, <0xea0710 4>;
+			#clock-cells = <0>;
+			clocks = <&osc>;
+			bypass-shift = /bits/ 8 <0>;
+		};
+
+		gateclk: gateclk {
+			compatible = "marvell,berlin4ct-gateclk";
+			reg = <0xea0700 4>;
+			#clock-cells = <1>;
+		};
+
+		clk: clk {
+			compatible = "marvell,berlin4ct-clk";
+			reg = <0xea0720 0x144>;
+			#clock-cells = <1>;
+			clocks = <&syspll>;
+		};
+
 		soc_pinctrl: pinctrl@ea8000 {
 			compatible = "marvell,berlin4ct-soc-pinctrl";
 			reg = <0xea8000 0x14>;
-- 
2.5.3

Re: [PATCH 0/5] Add Marvell berlin4ct clk support

[Jisheng Zhang]

+ CLK maintainers

sorry, yesterday I pressed ENTER quickly before --to list is completed

On Tue, 22 Sep 2015 22:12:31 +0800
Jisheng Zhang <jszhang@marvell.com> wrote:

> Add berlin4ct clk driver. The berlin4ct SoC contains:
> 
> two kinds of PLL: normal PLL and AVPLL. The normal PLL support is done.
> The AVPLL support is in TODO list.
> 
> two kinds of clk: normal clk and gate clk. The normal clk supports changing
> divider, selecting clock source, disabling/enabling etc. The gate clk only
> supports disabling/enabling. Both are supported in this series.
> 
> Jisheng Zhang (5):
>   clk: berlin: add common pll driver
>   clk: berlin: add common clk driver for newer SoCs
>   clk: berlin: add clk support for berlin4ct
>   dt-bindings: add binding for marvell berlin4ct SoC
>   arm64: dts: berlin4ct: add pll and clock nodes
> 
>  .../bindings/clock/marvell,berlin4ct.txt           |  38 +++++
>  arch/arm64/boot/dts/marvell/berlin4ct.dtsi         |  38 +++++
>  drivers/clk/berlin/Makefile                        |   2 +-
>  drivers/clk/berlin/clk-berlin4ct.c                 | 164 +++++++++++++++++++++
>  drivers/clk/berlin/clk.c                           | 147 ++++++++++++++++++
>  drivers/clk/berlin/clk.h                           |  38 +++++
>  drivers/clk/berlin/pll.c                           | 119 +++++++++++++++
>  include/dt-bindings/clock/berlin4ct.h              |  56 +++++++
>  8 files changed, 601 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/marvell,berlin4ct.txt
>  create mode 100644 drivers/clk/berlin/clk-berlin4ct.c
>  create mode 100644 drivers/clk/berlin/clk.c
>  create mode 100644 drivers/clk/berlin/clk.h
>  create mode 100644 drivers/clk/berlin/pll.c
>  create mode 100644 include/dt-bindings/clock/berlin4ct.h
> 

Re: [PATCH 1/5] clk: berlin: add common pll driver

[Stephen Boyd]

On 09/22, Jisheng Zhang wrote:
> diff --git a/drivers/clk/berlin/pll.c b/drivers/clk/berlin/pll.c
> new file mode 100644
> index 0000000..9aad0b6
> --- /dev/null
> +++ b/drivers/clk/berlin/pll.c
> @@ -0,0 +1,119 @@
> +
> +#define to_berlin_pll(hw)       container_of(hw, struct berlin_pll, hw)
> +
> +static u8 vcodiv_berlin[] = {1, 2, 4, 8, 16, 32, 64, 128};

This is an array of 1 << index position...

> +
> +static unsigned long berlin_pll_recalc_rate(struct clk_hw *hw,
> +					    unsigned long parent_rate)
> +{
> +	u32 val, fbdiv, rfdiv, vcodivsel, bypass;
> +	struct berlin_pll *pll = to_berlin_pll(hw);
> +
> +	bypass = readl_relaxed(pll->bypass);
> +	if (bypass & (1 << pll->bypass_shift))
> +		return parent_rate;
> +
> +	val = readl_relaxed(pll->ctrl + PLL_CTRL0);
> +	fbdiv = (val >> 12) & 0x1FF;
> +	rfdiv = (val >> 3) & 0x1FF;
> +	val = readl_relaxed(pll->ctrl + PLL_CTRL1);
> +	vcodivsel = (val >> 9) & 0x7;
> +	return parent_rate * fbdiv * 4 / rfdiv /
> +		vcodiv_berlin[vcodivsel];

so we can replace this with 1 << vcodivsel?

> +}
> +
> +static u8 berlin_pll_get_parent(struct clk_hw *hw)
> +{
> +	struct berlin_pll *pll = to_berlin_pll(hw);
> +	u32 bypass = readl_relaxed(pll->bypass);
> +
> +	if (bypass & (1 << pll->bypass_shift))
> +		return 1;
> +	else
> +		return 0;

Simplify this to 

	if (bypass & (1 << pll->bypass_shift))
		return 1;
	return 0;

or

	return !!(bypass & (1 << pll->bypass_shift)) 

> +}
> +
> +static const struct clk_ops berlin_pll_ops = {
> +	.recalc_rate	= berlin_pll_recalc_rate,
> +	.get_parent	= berlin_pll_get_parent,
> +};
> +
> +void __init berlin_pll_setup(struct device_node *np)

static?

> +{
> +	struct clk_init_data init;
> +	struct berlin_pll *pll;
> +	const char *parent_names[PLL_SOURCE_MAX];
> +	struct clk *clk;
> +	int ret, num_parents;
> +
> +	num_parents = of_clk_get_parent_count(np);
> +	if (num_parents <= 0 || num_parents > PLL_SOURCE_MAX)
> +		return;
> +
> +	of_clk_parent_fill(np, parent_names, num_parents);
> +
> +	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> +	if (WARN_ON(!pll))

We already print a big warning on allocation failures, so drop
the WARN_ON please.

> +		return;
> +
> +	pll->ctrl = of_iomap(np, 0);
> +	pll->bypass = of_iomap(np, 1);
> +	ret = of_property_read_u8(np, "bypass-shift", &pll->bypass_shift);
> +	if (WARN_ON(!pll->ctrl || !pll->bypass || ret))
> +		return;
> +
> +	init.name = np->name;
> +	init.ops = &berlin_pll_ops;
> +	init.parent_names = parent_names;
> +	init.num_parents = num_parents;

init.flags is not initialized. Please initialize the init struct
on the stack to 0 to avoid future problems.

> +
> +	pll->hw.init = &init;
> +
> +	clk = clk_register(NULL, &pll->hw);
> +	if (WARN_ON(IS_ERR(clk)))
> +		return;
> +
> +	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +	if (WARN_ON(ret))
> +		return;

This return is useless.

> +}

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 2/5] clk: berlin: add common clk driver for newer SoCs

[Stephen Boyd]

On 09/22, Jisheng Zhang wrote:
> +
> +static u8 clk_div[] = {1, 2, 4, 6, 8, 12, 1, 1};
> +
> +static unsigned long berlin_clk_recalc_rate(struct clk_hw *hw,
> +					unsigned long parent_rate)
> +{
> +	u32 val, divider;
> +	struct berlin_clk *clk = to_berlin_clk(hw);
> +
> +	val = readl_relaxed(clk->base);
> +	if (val & CLKD3SWITCH)
> +		divider = 3;
> +	else {
> +		if (val & CLKSWITCH) {
> +			val >>= CLKSEL_SHIFT;
> +			val &= CLKSEL_MASK;
> +			divider = clk_div[val];
> +		} else
> +			divider = 1;
> +	}

How about we drop the clk_div array and use code?

		if (val & CLKSWITCH) {
			val >>= CLKSEL_SHIFT;
			val &= CLKSEL_MASK;
		}

		divider = 1
		if (val < 6)
			divider <<= val;

> +
> +	return parent_rate / divider;
> +}

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 3/5] clk: berlin: add clk support for berlin4ct

[Stephen Boyd]

On 09/22, Jisheng Zhang wrote:
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +
> +#include "clk.h"
> +
> +#define CLK_SOURCE_MAX	5
> +
> +static struct clk_onecell_data gateclk_data;
> +static struct clk_onecell_data clk_data;
> +
> +static DEFINE_SPINLOCK(lock);

This is really generic. How about berlin4ct_lock? That will make
lockdep happy because the name for the key will have some
meaning.

> +static void __init berlin4ct_gateclk_setup(struct device_node *np)
> +{
> +	int i, n, ret;
> +	void __iomem *base;
> +	struct clk **clks;
> +
> +	base = of_iomap(np, 0);
> +	if (WARN_ON(!base))
> +		return;
> +
> +	n = ARRAY_SIZE(berlin4ct_gates);
> +	clks = kzalloc(n * sizeof(struct clk *), GFP_KERNEL);

kcalloc()

> +	if (WARN_ON(!clks))

Same comment about dropping WARN_ON for an allocation failure.

> +		return;
> +
> +	for (i = 0; i < n; i++) {
> +		clks[i] = clk_register_gate(NULL, berlin4ct_gates[i].name,
> +				berlin4ct_gates[i].parent_name,
> +				berlin4ct_gates[i].flags, base,
> +				berlin4ct_gates[i].bit_idx, 0, &lock);
> +		WARN_ON(IS_ERR(clks[i]));
> +	}
> +
> +	gateclk_data.clks = clks;
> +	gateclk_data.clk_num = i;
> +
> +	ret = of_clk_add_provider(np, of_clk_src_onecell_get,
> +				  &gateclk_data);
> +	if (WARN_ON(ret))
> +		return;

Drop that return please.

> +
> +}
> +CLK_OF_DECLARE(berlin4ct_gateclk, "marvell,berlin4ct-gateclk",
> +	       berlin4ct_gateclk_setup);
> +
> +static void __init berlin4ct_clk_setup(struct device_node *np)
> +{
> +	int i, n, ret, num_parents;
> +	void __iomem *base;
> +	struct clk **clks;
> +	const char *parent_names[CLK_SOURCE_MAX];
> +
> +	num_parents = of_clk_get_parent_count(np);
> +	if (num_parents <= 0 || num_parents > CLK_SOURCE_MAX)
> +		return;
> +
> +	of_clk_parent_fill(np, parent_names, num_parents);
> +
> +	base = of_iomap(np, 0);
> +	if (WARN_ON(!base))
> +		return;
> +
> +	n = ARRAY_SIZE(berlin4ct_descs);
> +	clks = kzalloc(n * sizeof(struct clk *), GFP_KERNEL);

kcalloc()

> +	if (WARN_ON(!clks))

Same comment about dropping WARN_ON for an allocation failure.

> +		return;
> +
> +	for (i = 0; i < n; i++) {
> +		clks[i] = berlin_clk_register(berlin4ct_descs[i].name,
> +				num_parents, parent_names,
> +				berlin4ct_descs[i].flags,
> +				base + berlin4ct_descs[i].offset);
> +		WARN_ON(IS_ERR(clks[i]));
> +	}
> +
> +	clk_data.clks = clks;
> +	clk_data.clk_num = i;
> +
> +	ret = of_clk_add_provider(np, of_clk_src_onecell_get,
> +				  &clk_data);
> +	if (WARN_ON(ret))
> +		return;

Drop that return please.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 4/5] dt-bindings: add binding for marvell berlin4ct SoC

[Stephen Boyd]

On 09/22, Jisheng Zhang wrote:
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +The berlin4ct clock subsystem generates and supplies clock to various
> +controllers within the berlin4ct SoC. The berlin4ct contains 3 clock controller
> +blocks: pll, gateclk, berlin-clk.
> +
> +Required Properties:
> +
> +- compatible: should be one of the following.
> +  - "marvell,berlin-pll" - pll compatible
> +  - "marvell,berlin4ct-clk" - berlin clk compatible
> +  - "marvell,berlin4ct-gateclk" - gateclk compatible
> +- reg: physical base address of the clock controller and length of memory mapped
> +  region. For pll, the second reg defines the bypass register base address and
> +  length of memory mapped region.
> +- #clock-cells: for pll should 0, for gateclk and berlin clk should be 1.
> +- #bypass-shift: the bypass bit in bypass register.
> +
> +Example:
> +
> +syspll: syspll {
> +	compatible = "marvell,berlin-pll";
> +	reg = <0xea0200 0x14>, <0xea0710 4>;
> +	#clock-cells = <0>;
> +	clocks = <&osc>;
> +	bypass-shift = /bits/ 8 <0>;
> +};
> +
> +clk: clk {
> +	compatible = "marvell,berlin4ct-clk";
> +	reg = <0xea0720 0x144>;
> +	#clock-cells = <1>;
> +	clocks = <&syspll>;
> +};

Is there one clock controller at 0xea0000 of size 0x1000? We've
been trying to push people towards using the device model and
writing drivers with probe instead of using CLK_OF_DECLARE() for
their platform clocks. From the looks of this binding, we're
splitting up the different types of clocks into their own nodes
and then registering them with CLK_OF_DECLARE.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 1/5] clk: berlin: add common pll driver

[Jisheng Zhang]

Hi Stephen,

On Thu, 1 Oct 2015 15:32:20 -0700
Stephen Boyd <sboyd@codeaurora.org> wrote:

> On 09/22, Jisheng Zhang wrote:
> > diff --git a/drivers/clk/berlin/pll.c b/drivers/clk/berlin/pll.c
> > new file mode 100644
> > index 0000000..9aad0b6
> > --- /dev/null
> > +++ b/drivers/clk/berlin/pll.c
> > @@ -0,0 +1,119 @@
> > +
> > +#define to_berlin_pll(hw)       container_of(hw, struct berlin_pll, hw)
> > +
> > +static u8 vcodiv_berlin[] = {1, 2, 4, 8, 16, 32, 64, 128};
> 
> This is an array of 1 << index position...

oops, yes! I didn't realize this before! Accept all the comments below, will
update in v2.

Thanks a lot for review,
Jisheng

> 
> > +
> > +static unsigned long berlin_pll_recalc_rate(struct clk_hw *hw,
> > +					    unsigned long parent_rate)
> > +{
> > +	u32 val, fbdiv, rfdiv, vcodivsel, bypass;
> > +	struct berlin_pll *pll = to_berlin_pll(hw);
> > +
> > +	bypass = readl_relaxed(pll->bypass);
> > +	if (bypass & (1 << pll->bypass_shift))
> > +		return parent_rate;
> > +
> > +	val = readl_relaxed(pll->ctrl + PLL_CTRL0);
> > +	fbdiv = (val >> 12) & 0x1FF;
> > +	rfdiv = (val >> 3) & 0x1FF;
> > +	val = readl_relaxed(pll->ctrl + PLL_CTRL1);
> > +	vcodivsel = (val >> 9) & 0x7;
> > +	return parent_rate * fbdiv * 4 / rfdiv /
> > +		vcodiv_berlin[vcodivsel];
> 
> so we can replace this with 1 << vcodivsel?
> 
> > +}
> > +
> > +static u8 berlin_pll_get_parent(struct clk_hw *hw)
> > +{
> > +	struct berlin_pll *pll = to_berlin_pll(hw);
> > +	u32 bypass = readl_relaxed(pll->bypass);
> > +
> > +	if (bypass & (1 << pll->bypass_shift))
> > +		return 1;
> > +	else
> > +		return 0;
> 
> Simplify this to 
> 
> 	if (bypass & (1 << pll->bypass_shift))
> 		return 1;
> 	return 0;
> 
> or
> 
> 	return !!(bypass & (1 << pll->bypass_shift)) 
> 
> > +}
> > +
> > +static const struct clk_ops berlin_pll_ops = {
> > +	.recalc_rate	= berlin_pll_recalc_rate,
> > +	.get_parent	= berlin_pll_get_parent,
> > +};
> > +
> > +void __init berlin_pll_setup(struct device_node *np)
> 
> static?
> 
> > +{
> > +	struct clk_init_data init;
> > +	struct berlin_pll *pll;
> > +	const char *parent_names[PLL_SOURCE_MAX];
> > +	struct clk *clk;
> > +	int ret, num_parents;
> > +
> > +	num_parents = of_clk_get_parent_count(np);
> > +	if (num_parents <= 0 || num_parents > PLL_SOURCE_MAX)
> > +		return;
> > +
> > +	of_clk_parent_fill(np, parent_names, num_parents);
> > +
> > +	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> > +	if (WARN_ON(!pll))
> 
> We already print a big warning on allocation failures, so drop
> the WARN_ON please.
> 
> > +		return;
> > +
> > +	pll->ctrl = of_iomap(np, 0);
> > +	pll->bypass = of_iomap(np, 1);
> > +	ret = of_property_read_u8(np, "bypass-shift", &pll->bypass_shift);
> > +	if (WARN_ON(!pll->ctrl || !pll->bypass || ret))
> > +		return;
> > +
> > +	init.name = np->name;
> > +	init.ops = &berlin_pll_ops;
> > +	init.parent_names = parent_names;
> > +	init.num_parents = num_parents;
> 
> init.flags is not initialized. Please initialize the init struct
> on the stack to 0 to avoid future problems.
> 
> > +
> > +	pll->hw.init = &init;
> > +
> > +	clk = clk_register(NULL, &pll->hw);
> > +	if (WARN_ON(IS_ERR(clk)))
> > +		return;
> > +
> > +	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
> > +	if (WARN_ON(ret))
> > +		return;
> 
> This return is useless.
> 
> > +}
> 

Re: [PATCH 4/5] dt-bindings: add binding for marvell berlin4ct SoC

[Jisheng Zhang]

Hi Stephen,

On Thu, 1 Oct 2015 15:50:27 -0700
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:

> On 09/22, Jisheng Zhang wrote:
> > +This binding uses the common clock binding[1].
> > +
> > +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> > +
> > +The berlin4ct clock subsystem generates and supplies clock to various
> > +controllers within the berlin4ct SoC. The berlin4ct contains 3 clock controller
> > +blocks: pll, gateclk, berlin-clk.
> > +
> > +Required Properties:
> > +
> > +- compatible: should be one of the following.
> > +  - "marvell,berlin-pll" - pll compatible
> > +  - "marvell,berlin4ct-clk" - berlin clk compatible
> > +  - "marvell,berlin4ct-gateclk" - gateclk compatible
> > +- reg: physical base address of the clock controller and length of memory mapped
> > +  region. For pll, the second reg defines the bypass register base address and
> > +  length of memory mapped region.
> > +- #clock-cells: for pll should 0, for gateclk and berlin clk should be 1.
> > +- #bypass-shift: the bypass bit in bypass register.
> > +
> > +Example:
> > +
> > +syspll: syspll {
> > +	compatible = "marvell,berlin-pll";
> > +	reg = <0xea0200 0x14>, <0xea0710 4>;
> > +	#clock-cells = <0>;
> > +	clocks = <&osc>;
> > +	bypass-shift = /bits/ 8 <0>;
> > +};
> > +
> > +clk: clk {
> > +	compatible = "marvell,berlin4ct-clk";
> > +	reg = <0xea0720 0x144>;
> > +	#clock-cells = <1>;
> > +	clocks = <&syspll>;
> > +};
> 
> Is there one clock controller at 0xea0000 of size 0x1000? We've

there's no clock controller at 0xea0000 with so big size. In BG4CT, we have
the following different kind of plls/clks

1. cpupll/syspll/mempll: the same IP, the pll register is put with the user
together, plus one shared bypass control register. For example: mempll register
is put with DDR controller registers together. cpupll, syspll and mempll share
the same bypass register: 0xea0710. 

2. gateclks: the clk can only be enabled or disabled, the control bits are put
into one(or two) register(s)

3. clks: can be disabled/enabled, change the divider, etc.. all these clks
registers are put together. In this register space, some space may not be used.


[PATCH 5/5] shows the layout of the clk/pll registers

> been trying to push people towards using the device model and
> writing drivers with probe instead of using CLK_OF_DECLARE() for

Is there any existing clk drivers switched to this type. I'll grep and
take that for an example.

> their platform clocks. From the looks of this binding, we're
> splitting up the different types of clocks into their own nodes
> and then registering them with CLK_OF_DECLARE.

Could you please kindly give advice about how to avoid the splitting?

Thanks a lot for review,
Jisheng
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