From mboxrd@z Thu Jan  1 00:00:00 1970
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Subject: Re: [PATCH 2/4] pinctrl: sunxi: add allwinner A83T PIO controller
 support
Date: Thu, 24 Sep 2015 12:15:03 +0200
Message-ID: <20150924101503.GQ4684@lukather>
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To: Chen-Yu Tsai <wens@csie.org>
Cc: Vishnu Patekar <vishnupatekar0510@gmail.com>, Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Kumar Gala <galak@codeaurora.org>, Russell King - ARM Linux <linux@arm.linux.org.uk>, Emilio Lopez <emilio@elopez.com.ar>, Linus Walleij <linus.walleij@linaro.org>, Jens Kuske <jenskuske@gmail.com>, Hans De Goede <hdegoede@redhat.com>, devicetree <devicetree@vger.kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, linux-kernel <linux-kernel@vger.kernel.org>, linux-sunxi <linux-sunxi@googlegroups.com>, "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>
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On Wed, Sep 23, 2015 at 12:06:56AM +0800, Chen-Yu Tsai wrote:
> > +static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data =3D {
> > +       .pins =3D sun8i_a83t_pins,
> > +       .npins =3D ARRAY_SIZE(sun8i_a83t_pins),
> > +       .irq_banks =3D 3,
>=20
> Do you know if there's a hole at where PA_EINT interrupt registers
> should be? AFAIK we aren't handling that properly, but that is outside
> the scope of this patch.

Judging from the A83t datasheet, PB seems to be the first IRQ bank, so
it should be fine.

Maxime

--=20
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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