Re: [PATCH 01/10] clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks

[Michael Turquette <mturquette@baylibre.com>]

Quoting Andrzej Hajda (2015-10-20 02:22:32)
> HDMI driver must re-parent respective muxes during HDMI-PHY on/off
> to HDMI-PHY output clocks. To reference those clocks their
> definitions should be added.
> 
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5433.c   | 6 ++++--
>  include/dt-bindings/clock/exynos5433.h | 5 ++++-
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index 650ec13..e037406 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -2614,8 +2614,10 @@ static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
>         FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
>                         100000000),
>         /* PHY clocks from HDMI_PHY */
> -       FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
> -       FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
> +       FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
> +                       NULL, CLK_IS_ROOT, 300000000),
> +       FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
> +                       NULL, CLK_IS_ROOT, 166000000),
>  };
>  
>  static struct samsung_mux_clock disp_mux_clks[] __initdata = {
> diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
> index 5bd80d5..4f0d566 100644
> --- a/include/dt-bindings/clock/exynos5433.h
> +++ b/include/dt-bindings/clock/exynos5433.h
> @@ -765,7 +765,10 @@
>  #define CLK_SCLK_RGB_VCLK                              109
>  #define CLK_SCLK_RGB_TV_VCLK                           110
>  
> -#define DISP_NR_CLK                                    111
> +#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY              111
> +#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY               112
> +
> +#define DISP_NR_CLK                                    113

Why break compatibility with older DTBs?

Regards,
Mike

>  
>  /* CMU_AUD */
>  #define CLK_MOUT_AUD_PLL_USER                          1
> -- 
> 1.9.1
> 
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