From mboxrd@z Thu Jan  1 00:00:00 1970
From: Wolfram Sang <wsa@the-dreams.de>
Subject: Re: [PATCH v2] i2c: davinci: Optimize clock generation on Keystone
 SoC
Date: Tue, 20 Oct 2015 17:05:46 +0200
Message-ID: <20151020150545.GF5379@katana>
References: <55F68D76.1060207@nokia.com>
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To: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>, linux-i2c@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Kumar Gala <galak@codeaurora.org>, Sekhar Nori <nsekhar@ti.com>, Kevin Hilman <khilman@deeprootsystems.com>, devicetree@vger.kernel.org, Hemanth Guruva Reddy <hemanth.guruva_reddy@nokia.com>, Lukasz Gemborowski <lukasz.gemborowski@nokia.com>
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On Mon, Sep 14, 2015 at 11:03:50AM +0200, Alexander Sverdlin wrote:
> According to "KeyStone Architecture Inter-IC Control Bus User Guide", fix=
ed
> additive part of frequency divisors (referred as "d" in the code and data=
sheet)
> always equals to 6, independent of module clock prescaler.
>=20
>                          module clock frequency

Applied to for-next, thanks!


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