From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Date: Thu, 22 Oct 2015 11:14:10 +0200 Message-ID: <20151022091410.GW10947@lukather> References: <1445444428-4652-1-git-send-email-jenskuske@gmail.com> <1445444428-4652-2-git-send-email-jenskuske@gmail.com> <20151022080508.GN10947@lukather> <20151022102959.09f0a1f4@OPI2> <20151022084735.GR10947@lukather> <20151022105745.2cc158a3@OPI2> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="WjpOG6URjntW8FAF" Return-path: Content-Disposition: inline In-Reply-To: <20151022105745.2cc158a3@OPI2> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Jean-Francois Moine Cc: Jens Kuske , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Vishnu Patekar , Emilio =?iso-8859-1?Q?L=F3pez?= , Michael Turquette , linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Hans de Goede , Chen-Yu Tsai , Rob Herring , Philipp Zabel , Linus Walleij , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org --WjpOG6URjntW8FAF Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Thu, Oct 22, 2015 at 10:57:45AM +0200, Jean-Francois Moine wrote: > On Thu, 22 Oct 2015 10:47:35 +0200 > Maxime Ripard wrote: > > > Not really. The uart0 reset is the bit 16, in the reset register 4. > > > > 4 * 32 + 16 = 44. > > > > Not 112, but still not 208 either. > > The registers are numbered 1..5, then > > (4 - 1) * 32 + 16 = 112 Not on my version, and even then, UARTs are on the last reset register, which would still make 144. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --WjpOG6URjntW8FAF--