From: Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Zhou Wang <wangzhou1-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Cc: Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
pratyush.anand-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>,
linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org,
gabriele.paoloni-hv44wF8Li93QT0dZR+AlfA@public.gmane.org,
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Subject: Re: [PATCH v11 4/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05
Date: Thu, 22 Oct 2015 13:46:22 -0500 [thread overview]
Message-ID: <20151022184622.GD21237@localhost> (raw)
In-Reply-To: <1444991021-109306-5-git-send-email-wangzhou1-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Hi Zhou,
This looks pretty good to me; just a mask question and add a printk.
On Fri, Oct 16, 2015 at 06:23:39PM +0800, Zhou Wang wrote:
> This patch adds PCIe host support for HiSilicon SoC Hip05.
> ...
> +#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
> +#define PCIE_LTSSM_LINKUP_STATE 0x11
> +#define PCIE_LTSSM_STATE_MASK 0x3F
Fabio unified some of this; see
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=pci/host-designware&id=4788fe6ebf4594c9a95b620cbff05147c8504823
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=pci/host-designware&id=b09464f77dd252a782da1f4e9925c1dbce4540ac
So the question is, why do you use a 6-bit (0x3f) LTSSM_STATE_MASK?
We think we can use a 5-bit mask (0x1f) for all the other
DesignWare-based systems.
> +/* Hip05 PCIe host only supports 32-bit config access */
Thanks for the comment asserting that Hip05 only supports 32-bit
config access. I assume you confirmed that with the hardware
designers. As far as I can tell, this *is* a hardware defect, and at
the minimum, I want a printk at driver probe-time so a dmesg log will
have a clue that read/modify/write on config space might do the wrong
thing.
> +static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
> + u32 *val)
> ...
Bjorn
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next prev parent reply other threads:[~2015-10-22 18:46 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-16 10:23 [PATCH v11 0/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 Zhou Wang
2015-10-16 10:23 ` [PATCH v11 1/6] PCI: designware: move calculation of bus addresses to DRA7xx Zhou Wang
2015-10-21 22:15 ` Bjorn Helgaas
2015-10-22 7:21 ` Gabriele Paoloni
2015-10-22 16:35 ` Bjorn Helgaas
2015-10-22 16:37 ` Gabriele Paoloni
2015-10-26 7:27 ` Zhou Wang
2015-10-16 10:23 ` [PATCH v11 2/6] ARM/PCI: remove align_resource in pci_sys_data Zhou Wang
2015-10-16 10:23 ` [PATCH v11 3/6] PCI: designware: Add ARM64 support Zhou Wang
[not found] ` <1444991021-109306-4-git-send-email-wangzhou1-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
2015-10-22 18:28 ` Bjorn Helgaas
2015-10-26 7:37 ` Zhou Wang
2015-10-16 10:23 ` [PATCH v11 4/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 Zhou Wang
[not found] ` <1444991021-109306-5-git-send-email-wangzhou1-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
2015-10-22 18:46 ` Bjorn Helgaas [this message]
2015-10-26 8:24 ` Zhou Wang
2015-10-16 10:23 ` [PATCH v11 5/6] Documentation: DT: Add HiSilicon PCIe host binding Zhou Wang
2015-10-16 10:23 ` [PATCH v11 6/6] MAINTAINERS: Add pcie-hisi maintainer Zhou Wang
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