From: Brian Norris <computersforpeace@gmail.com>
To: Jaedon Shin <jaedon.shin@gmail.com>
Cc: Tejun Heo <tj@kernel.org>, Kishon Vijay Abraham I <kishon@ti.com>,
Ralf Baechle <ralf@linux-mips.org>,
Florian Fainelli <f.fainelli@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
linux-ide@vger.kernel.org, linux-mips@linux-mips.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 03/10] ata: ahci_brcmstb: add support 40nm platforms
Date: Fri, 23 Oct 2015 14:25:58 -0700 [thread overview]
Message-ID: <20151023212558.GS13239@google.com> (raw)
In-Reply-To: <1445564663-66824-4-git-send-email-jaedon.shin@gmail.com>
Hi Jadeon,
Hmm, my suspicions about the PHY driver are probably meant to be applied
here. I don't think this change is sufficient.
On Fri, Oct 23, 2015 at 10:44:16AM +0900, Jaedon Shin wrote:
> Add offsets for 40nm BMIPS based set-top box platforms.
>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
> drivers/ata/ahci_brcmstb.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
> index 8cf6f7d4798f..59eb526cf4f6 100644
> --- a/drivers/ata/ahci_brcmstb.c
> +++ b/drivers/ata/ahci_brcmstb.c
> @@ -50,7 +50,8 @@
> #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2)
> #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3)
> #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
> - #define SATA_TOP_CTRL_PHY_OFFS 0x8
> + #define SATA_TOP_CTRL_28NM_PHY_OFFS 0x8
> + #define SATA_TOP_CTRL_40NM_PHY_OFFS 0x4
I don't remember the exact 40nm vs. 28nm map that well, but judging by
the code-is-the-documentation, the 28nm layout is like this:
base + 0x0C = port 0, phy control 1
base + 0x10 = port 0, phy control 2
base + 0x14 = port 1, phy control 1
base + 0x18 = port 1, phy control 2
but the 40nm layout is differnt, where the ports are interleaved:
base + 0x0C = port 0, phy control 1
base + 0x10 = port 1, phy control 1
base + 0x14 = port 0, phy control 2
base + 0x18 = port 1, phy control 2
So, your patch gets phy control 1 correct for both ports, but it doesn't
get phy control 2 correct. (Or at least, even if my guess at the 40nm
layout is wrong, your patch makes "port 0, phy control 2" collide with
"port 1, phy control 1", which is most certainly a bug.)
Are you sure you're testing this properly? Did you try using both ports
at the same time? And please, apply the same scrutiny to the PHY driver.
(e.g., did you test SSC? did you test both ports?)
Brian
> #define SATA_TOP_MAX_PHYS 2
> #define SATA_TOP_CTRL_SATA_TP_OUT 0x1c
> #define SATA_TOP_CTRL_CLIENT_INIT_CTRL 0x20
> @@ -237,7 +238,13 @@ static int brcm_ahci_resume(struct device *dev)
>
> static const struct of_device_id ahci_of_match[] = {
> {.compatible = "brcm,bcm7445-ahci",
> - .data = (void *)SATA_TOP_CTRL_PHY_OFFS},
> + .data = (void *)SATA_TOP_CTRL_28NM_PHY_OFFS},
> + {.compatible = "brcm,bcm7346-ahci",
> + .data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
> + {.compatible = "brcm,bcm7360-ahci",
> + .data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
> + {.compatible = "brcm,bcm7362-ahci",
> + .data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
> {},
> };
> MODULE_DEVICE_TABLE(of, ahci_of_match);
> --
> 2.6.2
>
> --
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next prev parent reply other threads:[~2015-10-23 21:25 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-23 1:44 [PATCH 00/10] add support SATA for BMIPS_GENERIC Jaedon Shin
2015-10-23 1:44 ` [PATCH 01/10] ata: ahci_brcmstb: make the driver buildable on BMIPS_GENERIC Jaedon Shin
2015-10-23 4:52 ` Florian Fainelli
2015-10-23 21:26 ` Brian Norris
2015-10-23 1:44 ` [PATCH 03/10] ata: ahci_brcmstb: add support 40nm platforms Jaedon Shin
2015-10-23 5:01 ` Florian Fainelli
2015-10-23 21:25 ` Brian Norris [this message]
[not found] ` <20151023212558.GS13239-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
2015-10-24 4:50 ` Jaedon Shin
2015-10-26 17:47 ` Brian Norris
2015-10-23 1:44 ` [PATCH 04/10] phy: phy_brcmstb_sata: make the driver buildable on BMIPS_GENERIC Jaedon Shin
[not found] ` <1445564663-66824-5-git-send-email-jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-10-23 5:01 ` Florian Fainelli
2015-10-23 14:47 ` Kishon Vijay Abraham I
2015-10-23 21:10 ` Brian Norris
2015-10-23 1:44 ` [PATCH 05/10] phy: phy_brcmstb_sata: remove unused definitions Jaedon Shin
2015-10-23 5:02 ` Florian Fainelli
2015-10-23 20:40 ` Brian Norris
[not found] ` <1445564663-66824-1-git-send-email-jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-10-23 1:44 ` [PATCH 02/10] ata: ahch_brcmstb: add data for port offset Jaedon Shin
2015-10-23 4:54 ` Florian Fainelli
2015-10-23 21:28 ` Brian Norris
2015-10-23 1:44 ` [PATCH 06/10] phy: phy_brcmstb_sata: add data for phy offset Jaedon Shin
2015-10-23 5:04 ` Florian Fainelli
2015-10-23 21:09 ` Brian Norris
2015-10-23 1:44 ` [PATCH 07/10] phy: phy_brcmstb_sata: add support 40nm platforms Jaedon Shin
[not found] ` <1445564663-66824-8-git-send-email-jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-10-23 5:06 ` Florian Fainelli
2015-10-23 21:09 ` Brian Norris
2015-10-23 1:44 ` [PATCH 08/10] MIPS: BMIPS: brcmstb: add SATA nodes for bcm7346 Jaedon Shin
2015-10-23 1:44 ` [PATCH 09/10] MIPS: BMIPS: brcmstb: add SATA nodes for bcm7360 Jaedon Shin
2015-10-23 1:44 ` [PATCH 10/10] MIPS: BMIPS: brcmstb: add SATA nodes for bcm7362 Jaedon Shin
2015-10-23 3:58 ` [PATCH 00/10] add support SATA for BMIPS_GENERIC Tejun Heo
2015-10-23 4:51 ` Florian Fainelli
2015-10-23 20:35 ` Brian Norris
[not found] ` <20151023203511.GN13239-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
2015-10-23 21:30 ` Kevin Cernekee
2015-10-24 4:51 ` Jaedon Shin
2015-10-24 20:43 ` Florian Fainelli
2015-10-27 10:21 ` Ralf Baechle
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