From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH 02/19] clk: sunxi: Add PLL3 clock Date: Fri, 30 Oct 2015 14:32:01 -0700 Message-ID: <20151030213155.GH19782@codeaurora.org> References: <1446214865-3972-1-git-send-email-maxime.ripard@free-electrons.com> <1446214865-3972-3-git-send-email-maxime.ripard@free-electrons.com> Reply-To: sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: Content-Disposition: inline In-Reply-To: <1446214865-3972-3-git-send-email-maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Maxime Ripard Cc: Mike Turquette , David Airlie , Thierry Reding , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Laurent Pinchart , Chen-Yu Tsai , Hans de Goede , Alexander Kaplan , Wynter Woods , Boris Brezillon , Thomas Petazzoni , Rob Clark , Daniel Vetter List-Id: devicetree@vger.kernel.org On 10/30, Maxime Ripard wrote: > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > index a9e1a5885846..40c32ffd912c 100644 > --- a/drivers/clk/sunxi/Makefile > +++ b/drivers/clk/sunxi/Makefile > @@ -9,8 +9,9 @@ obj-y += clk-a10-mod1.o > obj-y += clk-a10-pll2.o > obj-y += clk-a20-gmac.o > obj-y += clk-mod0.o > -obj-y += clk-sun4i-display.o > obj-y += clk-simple-gates.o > +obj-y += clk-sun4i-display.o Put this in the right place in patch 1 please. > +obj-y += clk-sun4i-pll3.o > obj-y += clk-sun8i-mbus.o > obj-y += clk-sun9i-core.o > obj-y += clk-sun9i-mmc.o > diff --git a/drivers/clk/sunxi/clk-sun4i-pll3.c b/drivers/clk/sunxi/clk-sun4i-pll3.c > new file mode 100644 > index 000000000000..7ea178bf19fa > --- /dev/null > +++ b/drivers/clk/sunxi/clk-sun4i-pll3.c > @@ -0,0 +1,84 @@ > +/* > + * Copyright 2015 Maxime Ripard > + * > + * Maxime Ripard > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include > +#include #include for of_property_read_string() > +#include > +#include > + > +#define SUN4I_A10_PLL3_GATE_BIT 31 [...] > + > + clk = clk_register_composite(NULL, clk_name, > + &parent, 1, > + NULL, NULL, > + &mult->hw, &clk_factor_ops, > + &gate->hw, &clk_gate_ops, > + 0); > + if (IS_ERR(clk)) { > + pr_err("%s: Couldn't register the clock\n", clk_name); > + goto free_mult; > + } > + > + of_clk_add_provider(node, of_clk_src_simple_get, clk); I hope this doesn't fail. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project