From mboxrd@z Thu Jan  1 00:00:00 1970
From: Liviu Dudau <Liviu.Dudau-5wv7dgnIgG8@public.gmane.org>
Subject: Re: [PATCH v2 1/4] drm: arm: Add DT bindings documentation for HDLCD
 driver.
Date: Thu, 12 Nov 2015 11:09:37 +0000
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To: "Jon Medhurst (Tixy)" <tixy-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
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On Thu, Nov 12, 2015 at 10:52:25AM +0000, Jon Medhurst (Tixy) wrote:
> On Thu, 2015-11-12 at 10:42 +0000, Liviu Dudau wrote:
> > > This is on-chip RAM or nornal system RAM? We already have binding=
s
> > for=20
> > > both.
> >
> > Juno has a set of TLX (ThinLinks) connectors on the board where an
> > FPGA can be attached. On r1
> > the code running on FPGA can even participate as an AXI master with
> > full coherency. The FPGA
> > has local memory that we want to share with the HDLCD to be used as=
 a
> > framebuffer.
>=20
> The HDLCD on the Juno chip or one implemented in the FPGA? I assume y=
ou
> mean the latter but just wanted to check.

You can have a GPU on the FPGA, and you want to read the framebuffer
off the FPGA's memory to render it on screen using the SoC's HDLCD. Hop=
e
this makes sense.

Best regards,
Liviu

>=20
> --=20
> Tixy
>=20

--=20
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---------------
    =C2=AF\_(=E3=83=84)_/=C2=AF
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