From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?utf-8?B?U8O2cmVu?= Brinkmann Subject: Re: [PATCH] ARM64: ZynqMP: DT: Fix GIC's 'reg' property Date: Tue, 15 Dec 2015 01:14:50 -0800 Message-ID: <20151215091450.GI3358@xsjsorenbubuntu> References: <1450110700-14152-1-git-send-email-soren.brinkmann@xilinx.com> <20151214164613.GH21356@leverpostej> <566EF5CC.4070000@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <566EF5CC.4070000-5wv7dgnIgG8@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Marc Zyngier Cc: Mark Rutland , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Pawel Moll , Ian Campbell , Catalin Marinas , Will Deacon , Michal Simek , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , Kumar Gala , Alistair Francis , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org On Mon, 2015-12-14 at 05:01PM +0000, Marc Zyngier wrote: > Mark, >=20 > On 14/12/15 16:46, Mark Rutland wrote: > > On Mon, Dec 14, 2015 at 08:31:40AM -0800, Soren Brinkmann wrote: > >> Signed-off-by: Soren Brinkmann > >> --- > >> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 6 +++--- > >> 1 file changed, 3 insertions(+), 3 deletions(-) > >> > >> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/b= oot/dts/xilinx/zynqmp.dtsi > >> index 857eda5c7217..b5d1facadf16 100644 > >> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > >> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > >> @@ -80,10 +80,10 @@ > >> gic: interrupt-controller@f9010000 { > >> compatible =3D "arm,gic-400", "arm,cortex-a15-gic"; > >> #interrupt-cells =3D <3>; > >> - reg =3D <0x0 0xf9010000 0x10000>, > >> - <0x0 0xf902f000 0x2000>, > >> + reg =3D <0x0 0xf9010000 0x1000>, > >> + <0x0 0xf9020000 0x20000>, > >> <0x0 0xf9040000 0x20000>, > >> - <0x0 0xf906f000 0x2000>; > >> + <0x0 0xf9060000 0x20000>; > >=20 > > I'm confused. These sizes don't look right for GIC-400. Is this a c= ustom > > GIC? >=20 > Probably an implementation that obey the SBSA requirement of aliasing > the first 4kB of the CPU interface on a 64kB page, and the second one= on > the following 64kB page. See the APM system for an example of such a > thing. I'm more concerned about the GICH region (3rd one), which has = no > reason to be bigger than 4kB. Xilinx didn't publish the memory map yet (at least I didn't see it in t= he public docs), so, let me give some excerpts: GICD: GICD_CTLR 0xF9010000 32 rw 0x00000000 Distributor Control Register =2E.. GICD_CIDR3 0xF9010FFC 32 ro 0x000000B1 Component ID3 Register GICC: GICC_CTLR 0xF9020000 32 rw 0x00000000 CPU Interface Control Regist= er =2E.. GICC_DIR 0xF9030000 32 wo x Deactivate Interrupt Register GICH: GICH_HCR 0xF9040000 32 rw 0x00000000 Hypervisor Control Register =2E.. GICH_LR3_Alias7 0xF9050F0C 32 rw 0x00000000 List Register 3 GICV: GICV_CTLR 0xF9060000 32 rw 0x00000000 Virtual Machine Control Regi= ster =2E.. GICV_DIR 0xF9070000 32 wo x VM Deactivate Interrupt Register Regarding the GICH area, it looks like it starts at 0xF9040000 and the alias blocks to access the other processor interfaces start at 0xF9050000. >=20 > > Did this ever work wit hteh old offsets and sizes? >=20 > It probably dies when trying to use EOImode=3D=3D1. Without knowing what parts we really exercise, yes, the system comes up fine so far, but I recently found Linux boot hanging on QEMU and it seemed to be related to time not progressing (fast enough). I found a different DT using the values proposed here and that fixed th= e hang for me. Thanks, S=C3=B6ren -- To unsubscribe from this list: send the line "unsubscribe devicetree" i= n the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html