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From: Mark Rutland <mark.rutland@arm.com>
To: John Garry <john.garry@huawei.com>
Cc: JBottomley@odin.com, martin.petersen@oracle.com,
	robh+dt@kernel.org, pawel.moll@arm.com,
	ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
	linuxarm@huawei.com, zhangfei.gao@linaro.org,
	xuwei5@hisilicon.com, john.garry2@mail.dcu.ie,
	linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org,
	arnd@arndb.de, devicetree@vger.kernel.org
Subject: Re: [PATCH 01/23] devicetree: bindings: hisi_sas: add v2 HW bindings
Date: Fri, 8 Jan 2016 15:19:35 +0000	[thread overview]
Message-ID: <20160108151934.GA32692@leverpostej> (raw)
In-Reply-To: <568FD281.4050207@huawei.com>

> >>@@ -25,11 +26,28 @@ Main node required properties:
> >>  		The phy interrupts are ordered into groups of 3 per phy
> >>  		(broadcast, phyup, and abnormal) in increasing order.
> >>  		Completion queue interrupts : each completion queue has 1
> >>-			interrupt source.
> >>-			The interrupts are ordered in increasing order.
> >>+			interrupt source. The interrupts are ordered in
> >>+			increasing order.
> >>  		Fatal interrupts : the fatal interrupts are ordered as follows:
> >>  			- ECC
> >>  			- AXI bus
> >>+		For v2 hw: Interrupts for phys, Sata, and completion queues;
> >>+		the interrupts are ordered in 3 groups, as follows:
> >>+		  - Phy interrupts
> >>+		  - Sata interrupts
> >>+		  - Completion queue interrupts
> >>+		Phy interrupts : Each controller has 2 phy interrupts:
> >>+			- phy up/down
> >>+			- channel interrupt
> >>+		Sata interrupts : Each phy on the controller has 1 Sata
> >>+			interrupt. The interrupts are ordered in increasing
> >>+			order.
> >>+		Completion queue interrupts : each completion queue has 1
> >>+			interrupt source. The interrupts are ordered in
> >>+			increasing order.
> >
> >There are no fatal interrupts in V2?
> 
> For v2 hardware, broadcast and fatal interrupts are mutliplexed into
> the general purpose channel interrupt line.

Ok, that sounds fine, just thought I should check.

> >>+Optional main node properties:
> >>+ - am-max-trans : limit controller for am max transmissions
> >
> >Is this a boolean? Number?
> >
> 
> This is a boolean. It is for dealing with a quirk in the chipset: an
> instance of the controller in the hip06 chipset requires registers
> set with a different init value.

Ok. I think the property at needs a better description for that.

It's not clear to me how "limit controller for am max transmissions"
maps to writing a specific value to some registers, but I don't know
much about SAS.

Is this some well-known thing, or values specific to hip06?

Thanks,
Mark.

  reply	other threads:[~2016-01-08 15:19 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-08 14:15 [PATCH 00/23] HiSilicon SAS v2 hw support John Garry
2016-01-08 14:15 ` [PATCH 01/23] devicetree: bindings: hisi_sas: add v2 HW bindings John Garry
     [not found]   ` <1452262542-64589-2-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2016-01-08 14:52     ` Mark Rutland
2016-01-08 15:15       ` John Garry
2016-01-08 15:19         ` Mark Rutland [this message]
2016-01-08 15:34           ` John Garry
2016-01-08 16:49             ` Mark Rutland
2016-01-11 14:00               ` John Garry
     [not found]                 ` <5693B59A.6000705-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2016-01-12 12:16                   ` John Garry
2016-01-08 14:15 ` [PATCH 03/23] hisi_sas: set max commands as configurable John Garry
2016-01-08 14:15 ` [PATCH 04/23] hisi_sas: reduce max itct entries John Garry
2016-01-08 14:15 ` [PATCH 05/23] hisi_sas: add hisi_sas_err_record_v1 John Garry
2016-01-08 14:15 ` [PATCH 06/23] hisi_sas: rename some fields in hisi_sas_itct John Garry
2016-01-08 14:15 ` [PATCH 07/23] hisi_sas: add bare v2 hw driver John Garry
2016-01-08 14:15 ` [PATCH 08/23] hisi_sas: add v2 register definitions John Garry
2016-01-08 14:15 ` [PATCH 10/23] hisi_sas: add init_id_frame_v2_hw() John Garry
2016-01-08 14:15 ` [PATCH 11/23] hisi_sas: add v2 phy init code John Garry
2016-01-08 14:15 ` [PATCH 12/23] hisi_sas: add v2 int init and phy up handler John Garry
     [not found] ` <1452262542-64589-1-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2016-01-08 14:15   ` [PATCH 02/23] hisi_sas: relocate DEV_IS_EXPANDER John Garry
2016-01-08 14:15   ` [PATCH 09/23] hisi_sas: add v2 hw init John Garry
2016-01-08 15:07     ` Mark Rutland
2016-01-08 14:15   ` [PATCH 13/23] hisi_sas: add v2 phy down handler John Garry
2016-01-08 14:15   ` [PATCH 18/23] hisi_sas: add v2 code to send smp command John Garry
2016-01-08 14:15   ` [PATCH 20/23] hisi_sas: add v2 path to send ATA command John Garry
2016-01-08 14:31   ` [PATCH 00/23] HiSilicon SAS v2 hw support John Garry
2016-01-08 14:15 ` [PATCH 14/23] hisi_sas: add v2 channel interrupt handler John Garry
2016-01-08 14:15 ` [PATCH 15/23] hisi_sas: add v2 SATA " John Garry
2016-01-08 14:15 ` [PATCH 16/23] hisi_sas: add v2 cq " John Garry
2016-01-08 17:29   ` kbuild test robot
2016-01-08 14:15 ` [PATCH 17/23] hisi_sas: add v2 path to send ssp frame John Garry
2016-01-08 14:15 ` [PATCH 19/23] hisi_sas: add v2 code for itct setup and free John Garry
2016-01-08 14:15 ` [PATCH 21/23] hisi_sas: add v2 slot error handler John Garry
2016-01-08 14:15 ` [PATCH 22/23] hisi_sas: add v2 tmf functions John Garry
2016-01-08 14:15 ` [PATCH 23/23] hisi_sas: update driver version to 1.1 John Garry
2016-01-11 13:43 ` [PATCH 00/23] HiSilicon SAS v2 hw support Hannes Reinecke

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