From: Mark Rutland <mark.rutland@arm.com>
To: John Garry <john.garry@huawei.com>
Cc: JBottomley@odin.com, martin.petersen@oracle.com,
robh+dt@kernel.org, pawel.moll@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
linuxarm@huawei.com, zhangfei.gao@linaro.org,
xuwei5@hisilicon.com, john.garry2@mail.dcu.ie,
linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org,
arnd@arndb.de, devicetree@vger.kernel.org
Subject: Re: [PATCH 01/23] devicetree: bindings: hisi_sas: add v2 HW bindings
Date: Fri, 8 Jan 2016 16:49:10 +0000 [thread overview]
Message-ID: <20160108164910.GD32692@leverpostej> (raw)
In-Reply-To: <568FD70D.1090303@huawei.com>
On Fri, Jan 08, 2016 at 03:34:37PM +0000, John Garry wrote:
>
> >>>>+Optional main node properties:
> >>>>+ - am-max-trans : limit controller for am max transmissions
> >>>
> >>>Is this a boolean? Number?
> >>>
> >>
> >>This is a boolean. It is for dealing with a quirk in the chipset: an
> >>instance of the controller in the hip06 chipset requires registers
> >>set with a different init value.
> >
> >Ok. I think the property at needs a better description for that.
> >
> >It's not clear to me how "limit controller for am max transmissions"
> >maps to writing a specific value to some registers, but I don't know
> >much about SAS.
> >
> >Is this some well-known thing, or values specific to hip06?
> >
> >Thanks,
> >Mark.
> >
>
> This is a specific issue for hip06 chipset.
Ok. So is this:
* a bug within the SAS controller in hip06, or:
* a requirement/bug of an endpoint attached to the controller, or:
* a requirement/bug of some interconnect between the controller and
endpoint, or:
* some other integration bug?
Please describe what the issue is that you're trying to work around, not
only your solution to it.
> There is a bug in the HW on hip06 where controller #1 has to set to 2
> registers to non-default values to limit "am-max-transmissions".
I got that. However, I have no idea what "am-max-transmissions" is, no
idea why you need to limit it (hopefully you can describe that a little
better above), nor what the semantics are for "limit".
The description of the property is an imperative, which reads like a
description of a specific driver behaviour rather than a property of the
hardware that leads to that behaviour being necessary. That's a warning
sign that the property is ill-defined, and we may encounter problems in
future due to changes in Linux.
Without knowing _why_ it's necessary to limit this, it's not possible to
know if the property is both necessary and sufficient to solve the
problem such that it doesn't rear its ugly head in future.
For example, if this is simply one way to work around a hip06-specific
integration bug that we cannot imagine occurring elsewhere, it may be
better to instead key off of a platform-specific compatible string for
the v2 SAS controller in hip06. That gives us more freedom to apply
different workarounds if we have to.
I see that the presence of this property will cause the driver to writes
hard-coded values two two registers. Not knowing the format of those
registers, their default values, nor how they respond to writes, I can't
tell:
* If the writes have other effects.
* If the limit is a single bit being flipped (i.e. this is a boolean in
hardware too).
* If the limit is some arbitrary chosen value which is not described in
the property or the binding, nor what that value is. If we encounter a
similar bug requiring a different bound in future, it may be
problematic to have chosen an arbitrary fixed value, and it may make
more sense to describe the value in the DT.
So, please:
* Update the DT property description to describe the specific HW issue
that needs to be worked around, with a full description in the commit
message.
* Add a comment to the driver to explain what the effect of the register
writes is intended to be, i.e. what value am max transmissions is
being set to, and why that value isn't arbitrary.
> This would not be a common SAS/SCSI controller property and is
> specific to our HW.
Ok.
Thanks,
Mark.
next prev parent reply other threads:[~2016-01-08 16:49 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-08 14:15 [PATCH 00/23] HiSilicon SAS v2 hw support John Garry
2016-01-08 14:15 ` [PATCH 01/23] devicetree: bindings: hisi_sas: add v2 HW bindings John Garry
[not found] ` <1452262542-64589-2-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2016-01-08 14:52 ` Mark Rutland
2016-01-08 15:15 ` John Garry
2016-01-08 15:19 ` Mark Rutland
2016-01-08 15:34 ` John Garry
2016-01-08 16:49 ` Mark Rutland [this message]
2016-01-11 14:00 ` John Garry
[not found] ` <5693B59A.6000705-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2016-01-12 12:16 ` John Garry
2016-01-08 14:15 ` [PATCH 03/23] hisi_sas: set max commands as configurable John Garry
2016-01-08 14:15 ` [PATCH 04/23] hisi_sas: reduce max itct entries John Garry
2016-01-08 14:15 ` [PATCH 05/23] hisi_sas: add hisi_sas_err_record_v1 John Garry
2016-01-08 14:15 ` [PATCH 06/23] hisi_sas: rename some fields in hisi_sas_itct John Garry
2016-01-08 14:15 ` [PATCH 07/23] hisi_sas: add bare v2 hw driver John Garry
2016-01-08 14:15 ` [PATCH 08/23] hisi_sas: add v2 register definitions John Garry
[not found] ` <1452262542-64589-1-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2016-01-08 14:15 ` [PATCH 02/23] hisi_sas: relocate DEV_IS_EXPANDER John Garry
2016-01-08 14:15 ` [PATCH 09/23] hisi_sas: add v2 hw init John Garry
2016-01-08 15:07 ` Mark Rutland
2016-01-08 14:15 ` [PATCH 13/23] hisi_sas: add v2 phy down handler John Garry
2016-01-08 14:15 ` [PATCH 18/23] hisi_sas: add v2 code to send smp command John Garry
2016-01-08 14:15 ` [PATCH 20/23] hisi_sas: add v2 path to send ATA command John Garry
2016-01-08 14:31 ` [PATCH 00/23] HiSilicon SAS v2 hw support John Garry
2016-01-08 14:15 ` [PATCH 10/23] hisi_sas: add init_id_frame_v2_hw() John Garry
2016-01-08 14:15 ` [PATCH 11/23] hisi_sas: add v2 phy init code John Garry
2016-01-08 14:15 ` [PATCH 12/23] hisi_sas: add v2 int init and phy up handler John Garry
2016-01-08 14:15 ` [PATCH 14/23] hisi_sas: add v2 channel interrupt handler John Garry
2016-01-08 14:15 ` [PATCH 15/23] hisi_sas: add v2 SATA " John Garry
2016-01-08 14:15 ` [PATCH 16/23] hisi_sas: add v2 cq " John Garry
2016-01-08 17:29 ` kbuild test robot
2016-01-08 14:15 ` [PATCH 17/23] hisi_sas: add v2 path to send ssp frame John Garry
2016-01-08 14:15 ` [PATCH 19/23] hisi_sas: add v2 code for itct setup and free John Garry
2016-01-08 14:15 ` [PATCH 21/23] hisi_sas: add v2 slot error handler John Garry
2016-01-08 14:15 ` [PATCH 22/23] hisi_sas: add v2 tmf functions John Garry
2016-01-08 14:15 ` [PATCH 23/23] hisi_sas: update driver version to 1.1 John Garry
2016-01-11 13:43 ` [PATCH 00/23] HiSilicon SAS v2 hw support Hannes Reinecke
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