From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nicolin Chen Subject: Re: [PATCH RFC 1/1] ASoC: fsl_ssi: Make fifo watermark and maxburst settings device tree options Date: Thu, 14 Jan 2016 18:45:35 -0800 Message-ID: <20160115024534.GB29132@Asurada-Nvidia> References: <1452788982-11583-1-git-send-email-caleb@crome.org> <20160114201858.GA17567@Asurada-Nvidia> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Caleb Crome Cc: Timur Tabi , Xiubo Li , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, "alsa-devel@alsa-project.org" List-Id: devicetree@vger.kernel.org On Thu, Jan 14, 2016 at 01:26:24PM -0800, Caleb Crome wrote: > As for optimal settings, I finally came to a setting of 4 for depth & > maxburst, which will result in more DMA requests, but it's the only > way that works at 48kHz for me. The default settings is 13 (15 - 2) > for the ones of the 15 item fifo, which is a pretty dramatic > difference. I just don't know if other chips will behave badly in > that case. What's your final configuration for TFWM0 bits, 4?