[PATCH V2 0/5] PCIe Xilinx generic driver for Microblaze and

[PATCH V2 0/5] PCIe Xilinx generic driver for Microblaze and

[Bharat Kumar Gogada]

This patch series does modifications to pcie-xilinx.c, to support common
driver on both Zynq and Microblaze architectures.
Microblaze pci-common.c has been modified to support generic driver.

I'm aware Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> has also sent patches
related to pcie-xilinx.c, but I'm unable to comment on them. 
I request Paul Burton to please add me in cc list so that I can comment on
those patches.

Bharat Kumar Gogada (5):
  PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function
  PCI: xilinx: Removing struct hw_irq structure.
  PCI: xilinx: Modifying AXI PCIe Host Bridge driver to      work on
    both  Zynq and Microblaze
  PCI: xilinx: Updating Zynq PCI binding documentation with     
    Microblaze node.
  Microblaze: Modifying microblaze PCI subsytem to support      generic
    Xilinx  AXI PCIe Host Bridge IP driver

 .../devicetree/bindings/pci/xilinx-pcie.txt        |  36 +++-
 arch/microblaze/Kconfig                            |   3 +
 arch/microblaze/pci/pci-common.c                   |  61 +++---
 drivers/pci/host/Kconfig                           |   2 +-
 drivers/pci/host/pcie-xilinx.c                     | 210 ++++-----------------
 5 files changed, 98 insertions(+), 214 deletions(-)

-- 
2.1.1

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[PATCH V2 1/5] PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function

[Bharat Kumar Gogada]

Removing xilinx_pcie_parse_and_add_res function replacing with
of_pci_get_host_bridge_resources API.

Signed-off-by: Bharat Kumar Gogada <bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Ravi Kiran Gummaluri <rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
Changes:
Solved issue with build failure.
Removing xilinx_pcie_parse_and_add_res function and replacing it
with of_pci_get_host_bridge_resources kernel API which does the same.
---
 drivers/pci/host/pcie-xilinx.c | 107 ++---------------------------------------
 1 file changed, 5 insertions(+), 102 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 3c7a0d5..f02cfe7 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -94,8 +94,6 @@
 /* Number of MSI IRQs */
 #define XILINX_NUM_MSI_IRQS		128
 
-/* Number of Memory Resources */
-#define XILINX_MAX_NUM_RESOURCES	3
 
 /**
  * struct xilinx_pcie_port - PCIe port information
@@ -105,7 +103,6 @@
  * @root_busno: Root Bus number
  * @dev: Device pointer
  * @irq_domain: IRQ domain pointer
- * @bus_range: Bus range
  * @resources: Bus Resources
  */
 struct xilinx_pcie_port {
@@ -115,7 +112,6 @@ struct xilinx_pcie_port {
 	u8 root_busno;
 	struct device *dev;
 	struct irq_domain *irq_domain;
-	struct resource bus_range;
 	struct list_head resources;
 };
 
@@ -659,97 +655,6 @@ static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 }
 
 /**
- * xilinx_pcie_parse_and_add_res - Add resources by parsing ranges
- * @port: PCIe port information
- *
- * Return: '0' on success and error value on failure
- */
-static int xilinx_pcie_parse_and_add_res(struct xilinx_pcie_port *port)
-{
-	struct device *dev = port->dev;
-	struct device_node *node = dev->of_node;
-	struct resource *mem;
-	resource_size_t offset;
-	struct of_pci_range_parser parser;
-	struct of_pci_range range;
-	struct resource_entry *win;
-	int err = 0, mem_resno = 0;
-
-	/* Get the ranges */
-	if (of_pci_range_parser_init(&parser, node)) {
-		dev_err(dev, "missing \"ranges\" property\n");
-		return -EINVAL;
-	}
-
-	/* Parse the ranges and add the resources found to the list */
-	for_each_of_pci_range(&parser, &range) {
-
-		if (mem_resno >= XILINX_MAX_NUM_RESOURCES) {
-			dev_err(dev, "Maximum memory resources exceeded\n");
-			return -EINVAL;
-		}
-
-		mem = devm_kmalloc(dev, sizeof(*mem), GFP_KERNEL);
-		if (!mem) {
-			err = -ENOMEM;
-			goto free_resources;
-		}
-
-		of_pci_range_to_resource(&range, node, mem);
-
-		switch (mem->flags & IORESOURCE_TYPE_BITS) {
-		case IORESOURCE_MEM:
-			offset = range.cpu_addr - range.pci_addr;
-			mem_resno++;
-			break;
-		default:
-			err = -EINVAL;
-			break;
-		}
-
-		if (err < 0) {
-			dev_warn(dev, "Invalid resource found %pR\n", mem);
-			continue;
-		}
-
-		err = request_resource(&iomem_resource, mem);
-		if (err)
-			goto free_resources;
-
-		pci_add_resource_offset(&port->resources, mem, offset);
-	}
-
-	/* Get the bus range */
-	if (of_pci_parse_bus_range(node, &port->bus_range)) {
-		u32 val = pcie_read(port, XILINX_PCIE_REG_BIR);
-		u8 last;
-
-		last = (val & XILINX_PCIE_BIR_ECAM_SZ_MASK) >>
-			XILINX_PCIE_BIR_ECAM_SZ_SHIFT;
-
-		port->bus_range = (struct resource) {
-			.name	= node->name,
-			.start	= 0,
-			.end	= last,
-			.flags	= IORESOURCE_BUS,
-		};
-	}
-
-	/* Register bus resource */
-	pci_add_resource(&port->resources, &port->bus_range);
-
-	return 0;
-
-free_resources:
-	release_child_resources(&iomem_resource);
-	resource_list_for_each_entry(win, &port->resources)
-		devm_kfree(dev, win->res);
-	pci_free_resource_list(&port->resources);
-
-	return err;
-}
-
-/**
  * xilinx_pcie_parse_dt - Parse Device tree
  * @port: PCIe port information
  *
@@ -802,6 +707,8 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
 	struct hw_pci hw;
 	struct device *dev = &pdev->dev;
 	int err;
+	resource_size_t iobase = 0;
+	LIST_HEAD(res);
 
 	if (!dev->of_node)
 		return -ENODEV;
@@ -826,14 +733,10 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
 		return err;
 	}
 
-	/*
-	 * Parse PCI ranges, configuration bus range and
-	 * request their resources
-	 */
-	INIT_LIST_HEAD(&port->resources);
-	err = xilinx_pcie_parse_and_add_res(port);
+	err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff, &res,
+					       &iobase);
 	if (err) {
-		dev_err(dev, "Failed adding resources\n");
+		dev_err(dev, "Getting bridge resources failed\n");
 		return err;
 	}
 
-- 
2.1.1

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[PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bharat Kumar Gogada]

This patch does required modifications to microblaze PCI subsystem, to
work with generic driver (drivers/pci/host/pcie-xilinx.c) on Microblaze
and Zynq.

Signed-off-by: Bharat Kumar Gogada <bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Ravi Kiran Gummaluri <rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
Changes:
Modified pcibios_fixup_bus in pci-common.c, as per generic architecuture.
Modified pcibios_align_resource in pci-common.c, as per generic
architecuture.
Modified pcibios_get_phb_of_node function in pci-common.c, to remove
dependency on struct pci_controller.
Removed pci_domain_nr in pci-common.c, instead using generic code.
Added pcibios_add_device in pci-common.c, as per generic architecuture.
Adding Kernel configuration in arch/microblaze as required for generic PCI
domains.
Added kernel configuration for driver to support Microblaze.
---
 arch/microblaze/Kconfig          |  3 ++
 arch/microblaze/pci/pci-common.c | 61 +++++++++++++++-------------------------
 drivers/pci/host/Kconfig         |  2 +-
 3 files changed, 27 insertions(+), 39 deletions(-)

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 0bce820..c3702b9 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -271,6 +271,9 @@ config PCI
 config PCI_DOMAINS
 	def_bool PCI
 
+config PCI_DOMAINS_GENERIC
+	def_bool PCI_DOMAINS
+
 config PCI_SYSCALL
 	def_bool PCI
 
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index ae838ed..bc72856 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t address)
 }
 EXPORT_SYMBOL_GPL(pci_address_to_pio);
 
-/*
- * Return the domain number for this bus.
- */
-int pci_domain_nr(struct pci_bus *bus)
-{
-	struct pci_controller *hose = pci_bus_to_host(bus);
-
-	return hose->global_number;
-}
-EXPORT_SYMBOL(pci_domain_nr);
-
 /* This routine is meant to be used early during boot, when the
  * PCI bus numbers have not yet been assigned, and you need to
  * issue PCI config cycles to an OF device.
@@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus *bus)
 
 void pcibios_fixup_bus(struct pci_bus *bus)
 {
-	/* When called from the generic PCI probe, read PCI<->PCI bridge
-	 * bases. This is -not- called when generating the PCI tree from
-	 * the OF device-tree.
-	 */
-	if (bus->self != NULL)
-		pci_read_bridge_bases(bus);
-
-	/* Now fixup the bus bus */
-	pcibios_setup_bus_self(bus);
-
-	/* Now fixup devices on that bus */
-	pcibios_setup_bus_devices(bus);
+	/* nothing to do */
 }
 EXPORT_SYMBOL(pcibios_fixup_bus);
 
-static int skip_isa_ioresource_align(struct pci_dev *dev)
-{
-	return 0;
-}
-
 /*
  * We need to avoid collisions with `mirrored' VGA ports
  * and other strange ISA hardware, so we always want the
@@ -899,20 +872,20 @@ static int skip_isa_ioresource_align(struct pci_dev *dev)
 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 				resource_size_t size, resource_size_t align)
 {
-	struct pci_dev *dev = data;
 	resource_size_t start = res->start;
 
-	if (res->flags & IORESOURCE_IO) {
-		if (skip_isa_ioresource_align(dev))
-			return start;
-		if (start & 0x300)
-			start = (start + 0x3ff) & ~0x3ff;
-	}
-
 	return start;
 }
 EXPORT_SYMBOL(pcibios_align_resource);
 
+int pcibios_add_device(struct pci_dev *dev)
+{
+	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
+
+	return 0;
+}
+EXPORT_SYMBOL(pcibios_add_device);
+
 /*
  * Reparent resource children of pr that conflict with res
  * under res, and make res replace those children.
@@ -1335,9 +1308,21 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose,
 
 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
 {
-	struct pci_controller *hose = bus->sysdata;
+	struct device_node *np;
+
+	for_each_node_by_type(np, "pci") {
+		const void *prop;
+		unsigned int bus_min;
+
+		prop = of_get_property(np, "bus-range", NULL);
+		if (!prop)
+			continue;
+		bus_min = be32_to_cpup(prop);
+		if (bus->number == bus_min)
+			return np;
+	}
 
-	return of_node_get(hose->dn);
+	return NULL;
 }
 
 static void pcibios_scan_phb(struct pci_controller *hose)
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d5e58ba..7c56c2e 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -79,7 +79,7 @@ config PCI_KEYSTONE
 
 config PCIE_XILINX
 	bool "Xilinx AXI PCIe host bridge support"
-	depends on ARCH_ZYNQ
+	depends on ARCH_ZYNQ || MICROBLAZE
 	help
 	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
 	  Host Bridge driver.
-- 
2.1.1

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RE: [PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bharat Kumar Gogada]

Ping
 
> This patch does required modifications to microblaze PCI subsystem, to
> work with generic driver (drivers/pci/host/pcie-xilinx.c) on Microblaze
> and Zynq.
> 
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> ---
> Changes:
> Modified pcibios_fixup_bus in pci-common.c, as per generic architecuture.
> Modified pcibios_align_resource in pci-common.c, as per generic
> architecuture.
> Modified pcibios_get_phb_of_node function in pci-common.c, to remove
> dependency on struct pci_controller.
> Removed pci_domain_nr in pci-common.c, instead using generic code.
> Added pcibios_add_device in pci-common.c, as per generic architecuture.
> Adding Kernel configuration in arch/microblaze as required for generic PCI
> domains.
> Added kernel configuration for driver to support Microblaze.
> ---
>  arch/microblaze/Kconfig          |  3 ++
>  arch/microblaze/pci/pci-common.c | 61 +++++++++++++++--------------------
> -----
>  drivers/pci/host/Kconfig         |  2 +-
>  3 files changed, 27 insertions(+), 39 deletions(-)
> 
> diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
> index 0bce820..c3702b9 100644
> --- a/arch/microblaze/Kconfig
> +++ b/arch/microblaze/Kconfig
> @@ -271,6 +271,9 @@ config PCI
>  config PCI_DOMAINS
>  	def_bool PCI
> 
> +config PCI_DOMAINS_GENERIC
> +	def_bool PCI_DOMAINS
> +
>  config PCI_SYSCALL
>  	def_bool PCI
> 
> diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-
> common.c
> index ae838ed..bc72856 100644
> --- a/arch/microblaze/pci/pci-common.c
> +++ b/arch/microblaze/pci/pci-common.c
> @@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t
> address)
>  }
>  EXPORT_SYMBOL_GPL(pci_address_to_pio);
> 
> -/*
> - * Return the domain number for this bus.
> - */
> -int pci_domain_nr(struct pci_bus *bus)
> -{
> -	struct pci_controller *hose = pci_bus_to_host(bus);
> -
> -	return hose->global_number;
> -}
> -EXPORT_SYMBOL(pci_domain_nr);
> -
>  /* This routine is meant to be used early during boot, when the
>   * PCI bus numbers have not yet been assigned, and you need to
>   * issue PCI config cycles to an OF device.
> @@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus
> *bus)
> 
>  void pcibios_fixup_bus(struct pci_bus *bus)
>  {
> -	/* When called from the generic PCI probe, read PCI<->PCI bridge
> -	 * bases. This is -not- called when generating the PCI tree from
> -	 * the OF device-tree.
> -	 */
> -	if (bus->self != NULL)
> -		pci_read_bridge_bases(bus);
> -
> -	/* Now fixup the bus bus */
> -	pcibios_setup_bus_self(bus);
> -
> -	/* Now fixup devices on that bus */
> -	pcibios_setup_bus_devices(bus);
> +	/* nothing to do */
>  }
>  EXPORT_SYMBOL(pcibios_fixup_bus);
> 
> -static int skip_isa_ioresource_align(struct pci_dev *dev)
> -{
> -	return 0;
> -}
> -
>  /*
>   * We need to avoid collisions with `mirrored' VGA ports
>   * and other strange ISA hardware, so we always want the
> @@ -899,20 +872,20 @@ static int skip_isa_ioresource_align(struct pci_dev
> *dev)
>  resource_size_t pcibios_align_resource(void *data, const struct resource
> *res,
>  				resource_size_t size, resource_size_t align)
>  {
> -	struct pci_dev *dev = data;
>  	resource_size_t start = res->start;
> 
> -	if (res->flags & IORESOURCE_IO) {
> -		if (skip_isa_ioresource_align(dev))
> -			return start;
> -		if (start & 0x300)
> -			start = (start + 0x3ff) & ~0x3ff;
> -	}
> -
>  	return start;
>  }
>  EXPORT_SYMBOL(pcibios_align_resource);
> 
> +int pcibios_add_device(struct pci_dev *dev)
> +{
> +	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(pcibios_add_device);
> +
>  /*
>   * Reparent resource children of pr that conflict with res
>   * under res, and make res replace those children.
> @@ -1335,9 +1308,21 @@ static void pcibios_setup_phb_resources(struct
> pci_controller *hose,
> 
>  struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
>  {
> -	struct pci_controller *hose = bus->sysdata;
> +	struct device_node *np;
> +
> +	for_each_node_by_type(np, "pci") {
> +		const void *prop;
> +		unsigned int bus_min;
> +
> +		prop = of_get_property(np, "bus-range", NULL);
> +		if (!prop)
> +			continue;
> +		bus_min = be32_to_cpup(prop);
> +		if (bus->number == bus_min)
> +			return np;
> +	}
> 
> -	return of_node_get(hose->dn);
> +	return NULL;
>  }
> 
>  static void pcibios_scan_phb(struct pci_controller *hose)
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index d5e58ba..7c56c2e 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -79,7 +79,7 @@ config PCI_KEYSTONE
> 
>  config PCIE_XILINX
>  	bool "Xilinx AXI PCIe host bridge support"
> -	depends on ARCH_ZYNQ
> +	depends on ARCH_ZYNQ || MICROBLAZE
>  	help
>  	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
>  	  Host Bridge driver.
> --
> 2.1.1

Re: [PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bjorn Helgaas]

Hi Bharat,

On Wed, Feb 03, 2016 at 03:40:21PM +0000, Bharat Kumar Gogada wrote:
> Ping

You said you were going to do another revision, so I'm waiting for r3.

> > This patch does required modifications to microblaze PCI subsystem, to
> > work with generic driver (drivers/pci/host/pcie-xilinx.c) on Microblaze
> > and Zynq.
> > 
> > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> > ---
> > Changes:
> > Modified pcibios_fixup_bus in pci-common.c, as per generic architecuture.
> > Modified pcibios_align_resource in pci-common.c, as per generic
> > architecuture.
> > Modified pcibios_get_phb_of_node function in pci-common.c, to remove
> > dependency on struct pci_controller.
> > Removed pci_domain_nr in pci-common.c, instead using generic code.
> > Added pcibios_add_device in pci-common.c, as per generic architecuture.
> > Adding Kernel configuration in arch/microblaze as required for generic PCI
> > domains.
> > Added kernel configuration for driver to support Microblaze.
> > ---
> >  arch/microblaze/Kconfig          |  3 ++
> >  arch/microblaze/pci/pci-common.c | 61 +++++++++++++++--------------------
> > -----
> >  drivers/pci/host/Kconfig         |  2 +-
> >  3 files changed, 27 insertions(+), 39 deletions(-)
> > 
> > diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
> > index 0bce820..c3702b9 100644
> > --- a/arch/microblaze/Kconfig
> > +++ b/arch/microblaze/Kconfig
> > @@ -271,6 +271,9 @@ config PCI
> >  config PCI_DOMAINS
> >  	def_bool PCI
> > 
> > +config PCI_DOMAINS_GENERIC
> > +	def_bool PCI_DOMAINS
> > +
> >  config PCI_SYSCALL
> >  	def_bool PCI
> > 
> > diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-
> > common.c
> > index ae838ed..bc72856 100644
> > --- a/arch/microblaze/pci/pci-common.c
> > +++ b/arch/microblaze/pci/pci-common.c
> > @@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t
> > address)
> >  }
> >  EXPORT_SYMBOL_GPL(pci_address_to_pio);
> > 
> > -/*
> > - * Return the domain number for this bus.
> > - */
> > -int pci_domain_nr(struct pci_bus *bus)
> > -{
> > -	struct pci_controller *hose = pci_bus_to_host(bus);
> > -
> > -	return hose->global_number;
> > -}
> > -EXPORT_SYMBOL(pci_domain_nr);
> > -
> >  /* This routine is meant to be used early during boot, when the
> >   * PCI bus numbers have not yet been assigned, and you need to
> >   * issue PCI config cycles to an OF device.
> > @@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus
> > *bus)
> > 
> >  void pcibios_fixup_bus(struct pci_bus *bus)
> >  {
> > -	/* When called from the generic PCI probe, read PCI<->PCI bridge
> > -	 * bases. This is -not- called when generating the PCI tree from
> > -	 * the OF device-tree.
> > -	 */
> > -	if (bus->self != NULL)
> > -		pci_read_bridge_bases(bus);
> > -
> > -	/* Now fixup the bus bus */
> > -	pcibios_setup_bus_self(bus);
> > -
> > -	/* Now fixup devices on that bus */
> > -	pcibios_setup_bus_devices(bus);
> > +	/* nothing to do */
> >  }
> >  EXPORT_SYMBOL(pcibios_fixup_bus);
> > 
> > -static int skip_isa_ioresource_align(struct pci_dev *dev)
> > -{
> > -	return 0;
> > -}
> > -
> >  /*
> >   * We need to avoid collisions with `mirrored' VGA ports
> >   * and other strange ISA hardware, so we always want the
> > @@ -899,20 +872,20 @@ static int skip_isa_ioresource_align(struct pci_dev
> > *dev)
> >  resource_size_t pcibios_align_resource(void *data, const struct resource
> > *res,
> >  				resource_size_t size, resource_size_t align)
> >  {
> > -	struct pci_dev *dev = data;
> >  	resource_size_t start = res->start;
> > 
> > -	if (res->flags & IORESOURCE_IO) {
> > -		if (skip_isa_ioresource_align(dev))
> > -			return start;
> > -		if (start & 0x300)
> > -			start = (start + 0x3ff) & ~0x3ff;
> > -	}
> > -
> >  	return start;
> >  }
> >  EXPORT_SYMBOL(pcibios_align_resource);
> > 
> > +int pcibios_add_device(struct pci_dev *dev)
> > +{
> > +	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> > +
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL(pcibios_add_device);
> > +
> >  /*
> >   * Reparent resource children of pr that conflict with res
> >   * under res, and make res replace those children.
> > @@ -1335,9 +1308,21 @@ static void pcibios_setup_phb_resources(struct
> > pci_controller *hose,
> > 
> >  struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
> >  {
> > -	struct pci_controller *hose = bus->sysdata;
> > +	struct device_node *np;
> > +
> > +	for_each_node_by_type(np, "pci") {
> > +		const void *prop;
> > +		unsigned int bus_min;
> > +
> > +		prop = of_get_property(np, "bus-range", NULL);
> > +		if (!prop)
> > +			continue;
> > +		bus_min = be32_to_cpup(prop);
> > +		if (bus->number == bus_min)
> > +			return np;
> > +	}
> > 
> > -	return of_node_get(hose->dn);
> > +	return NULL;
> >  }
> > 
> >  static void pcibios_scan_phb(struct pci_controller *hose)
> > diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> > index d5e58ba..7c56c2e 100644
> > --- a/drivers/pci/host/Kconfig
> > +++ b/drivers/pci/host/Kconfig
> > @@ -79,7 +79,7 @@ config PCI_KEYSTONE
> > 
> >  config PCIE_XILINX
> >  	bool "Xilinx AXI PCIe host bridge support"
> > -	depends on ARCH_ZYNQ
> > +	depends on ARCH_ZYNQ || MICROBLAZE
> >  	help
> >  	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
> >  	  Host Bridge driver.
> > --
> > 2.1.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bharat Kumar Gogada]

> You said you were going to do another revision, so I'm waiting for r3.
Hi Bjorn, 
Do you have any comments on this patch (5/5), I will address other patches comments along with this patch, if any, in v3.

Bharat
> 
> > > This patch does required modifications to microblaze PCI subsystem,
> > > to work with generic driver (drivers/pci/host/pcie-xilinx.c) on
> > > Microblaze and Zynq.
> > >
> > > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> > > ---
> > > Changes:
> > > Modified pcibios_fixup_bus in pci-common.c, as per generic
> architecuture.
> > > Modified pcibios_align_resource in pci-common.c, as per generic
> > > architecuture.
> > > Modified pcibios_get_phb_of_node function in pci-common.c, to
> remove
> > > dependency on struct pci_controller.
> > > Removed pci_domain_nr in pci-common.c, instead using generic code.
> > > Added pcibios_add_device in pci-common.c, as per generic
> architecuture.
> > > Adding Kernel configuration in arch/microblaze as required for
> > > generic PCI domains.
> > > Added kernel configuration for driver to support Microblaze.
> > > ---
> > >  arch/microblaze/Kconfig          |  3 ++
> > >  arch/microblaze/pci/pci-common.c | 61
> > > +++++++++++++++--------------------
> > > -----
> > >  drivers/pci/host/Kconfig         |  2 +-
> > >  3 files changed, 27 insertions(+), 39 deletions(-)
> > >
> > > diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index
> > > 0bce820..c3702b9 100644
> > > --- a/arch/microblaze/Kconfig
> > > +++ b/arch/microblaze/Kconfig
> > > @@ -271,6 +271,9 @@ config PCI
> > >  config PCI_DOMAINS
> > >  	def_bool PCI
> > >
> > > +config PCI_DOMAINS_GENERIC
> > > +	def_bool PCI_DOMAINS
> > > +
> > >  config PCI_SYSCALL
> > >  	def_bool PCI
> > >
> > > diff --git a/arch/microblaze/pci/pci-common.c
> > > b/arch/microblaze/pci/pci- common.c index ae838ed..bc72856 100644
> > > --- a/arch/microblaze/pci/pci-common.c
> > > +++ b/arch/microblaze/pci/pci-common.c
> > > @@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t
> > > address)
> > >  }
> > >  EXPORT_SYMBOL_GPL(pci_address_to_pio);
> > >
> > > -/*
> > > - * Return the domain number for this bus.
> > > - */
> > > -int pci_domain_nr(struct pci_bus *bus) -{
> > > -	struct pci_controller *hose = pci_bus_to_host(bus);
> > > -
> > > -	return hose->global_number;
> > > -}
> > > -EXPORT_SYMBOL(pci_domain_nr);
> > > -
> > >  /* This routine is meant to be used early during boot, when the
> > >   * PCI bus numbers have not yet been assigned, and you need to
> > >   * issue PCI config cycles to an OF device.
> > > @@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus
> > > *bus)
> > >
> > >  void pcibios_fixup_bus(struct pci_bus *bus)  {
> > > -	/* When called from the generic PCI probe, read PCI<->PCI bridge
> > > -	 * bases. This is -not- called when generating the PCI tree from
> > > -	 * the OF device-tree.
> > > -	 */
> > > -	if (bus->self != NULL)
> > > -		pci_read_bridge_bases(bus);
> > > -
> > > -	/* Now fixup the bus bus */
> > > -	pcibios_setup_bus_self(bus);
> > > -
> > > -	/* Now fixup devices on that bus */
> > > -	pcibios_setup_bus_devices(bus);
> > > +	/* nothing to do */
> > >  }
> > >  EXPORT_SYMBOL(pcibios_fixup_bus);
> > >
> > > -static int skip_isa_ioresource_align(struct pci_dev *dev) -{
> > > -	return 0;
> > > -}
> > > -
> > >  /*
> > >   * We need to avoid collisions with `mirrored' VGA ports
> > >   * and other strange ISA hardware, so we always want the @@ -899,20
> > > +872,20 @@ static int skip_isa_ioresource_align(struct pci_dev
> > > *dev)
> > >  resource_size_t pcibios_align_resource(void *data, const struct
> > > resource *res,
> > >  				resource_size_t size, resource_size_t align)  {
> > > -	struct pci_dev *dev = data;
> > >  	resource_size_t start = res->start;
> > >
> > > -	if (res->flags & IORESOURCE_IO) {
> > > -		if (skip_isa_ioresource_align(dev))
> > > -			return start;
> > > -		if (start & 0x300)
> > > -			start = (start + 0x3ff) & ~0x3ff;
> > > -	}
> > > -
> > >  	return start;
> > >  }
> > >  EXPORT_SYMBOL(pcibios_align_resource);
> > >
> > > +int pcibios_add_device(struct pci_dev *dev) {
> > > +	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> > > +
> > > +	return 0;
> > > +}
> > > +EXPORT_SYMBOL(pcibios_add_device);
> > > +
> > >  /*
> > >   * Reparent resource children of pr that conflict with res
> > >   * under res, and make res replace those children.
> > > @@ -1335,9 +1308,21 @@ static void
> > > pcibios_setup_phb_resources(struct
> > > pci_controller *hose,
> > >
> > >  struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)  {
> > > -	struct pci_controller *hose = bus->sysdata;
> > > +	struct device_node *np;
> > > +
> > > +	for_each_node_by_type(np, "pci") {
> > > +		const void *prop;
> > > +		unsigned int bus_min;
> > > +
> > > +		prop = of_get_property(np, "bus-range", NULL);
> > > +		if (!prop)
> > > +			continue;
> > > +		bus_min = be32_to_cpup(prop);
> > > +		if (bus->number == bus_min)
> > > +			return np;
> > > +	}
> > >
> > > -	return of_node_get(hose->dn);
> > > +	return NULL;
> > >  }
> > >
> > >  static void pcibios_scan_phb(struct pci_controller *hose) diff
> > > --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index
> > > d5e58ba..7c56c2e 100644
> > > --- a/drivers/pci/host/Kconfig
> > > +++ b/drivers/pci/host/Kconfig
> > > @@ -79,7 +79,7 @@ config PCI_KEYSTONE
> > >
> > >  config PCIE_XILINX
> > >  	bool "Xilinx AXI PCIe host bridge support"
> > > -	depends on ARCH_ZYNQ
> > > +	depends on ARCH_ZYNQ || MICROBLAZE
> > >  	help
> > >  	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
> > >  	  Host Bridge driver.
> > > --
> > > 2.1.1
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-pci"
> > in the body of a message to majordomo@vger.kernel.org More
> majordomo
> > info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bjorn Helgaas]

[+cc Ben, pcibios_get_phb_of_node() question]

On Tue, Jan 12, 2016 at 11:06:13PM +0530, Bharat Kumar Gogada wrote:
> This patch does required modifications to microblaze PCI subsystem, to
> work with generic driver (drivers/pci/host/pcie-xilinx.c) on Microblaze
> and Zynq.
> 
> Signed-off-by: Bharat Kumar Gogada <bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> Signed-off-by: Ravi Kiran Gummaluri <rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
>...

>  resource_size_t pcibios_align_resource(void *data, const struct resource *res,
>  				resource_size_t size, resource_size_t align)
>  {
> -	struct pci_dev *dev = data;
>  	resource_size_t start = res->start;
>  
> -	if (res->flags & IORESOURCE_IO) {
> -		if (skip_isa_ioresource_align(dev))
> -			return start;
> -		if (start & 0x300)
> -			start = (start + 0x3ff) & ~0x3ff;
> -	}
> -
>  	return start;

"return res->start;" is sufficient; no need for a temporary variable.

>  }
>  EXPORT_SYMBOL(pcibios_align_resource);
>  
> +int pcibios_add_device(struct pci_dev *dev)
> +{
> +	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(pcibios_add_device);
> +
>  /*
>   * Reparent resource children of pr that conflict with res
>   * under res, and make res replace those children.
> @@ -1335,9 +1308,21 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose,
>  
>  struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
>  {
> -	struct pci_controller *hose = bus->sysdata;
> +	struct device_node *np;
> +
> +	for_each_node_by_type(np, "pci") {
> +		const void *prop;
> +		unsigned int bus_min;
> +
> +		prop = of_get_property(np, "bus-range", NULL);
> +		if (!prop)
> +			continue;
> +		bus_min = be32_to_cpup(prop);
> +		if (bus->number == bus_min)
> +			return np;
> +	}
>  
> -	return of_node_get(hose->dn);
> +	return NULL;

Hmmm.  The old microblaze code ("return of_node_get(hose->dn);") is
basically the same as the mips and powerpc versions.  The new code is
basically the same as the x86 version.

I like the generic weak version in drivers/pci/of.c because it doesn't
use any arch-specific data, and it looks like if we just set the
struct device.of_node members correctly, everything should Just Work.

But Ben added both the generic and the x86 versions the same day, so
there must be some complication:

  98d9f30c820d ("pci/of: Match PCI devices to OF nodes dynamically")
  3d5fe5a65af9 ("x86/devicetree: Use generic PCI <-> OF matching")

So I guess my question is, why do we need a microblaze-specific
version at all?

Bjorn
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Re: [PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bjorn Helgaas]

[+cc Ben for real this time]

On Wed, Feb 03, 2016 at 10:32:07AM -0600, Bjorn Helgaas wrote:
> [+cc Ben, pcibios_get_phb_of_node() question]
> 
> On Tue, Jan 12, 2016 at 11:06:13PM +0530, Bharat Kumar Gogada wrote:
> > This patch does required modifications to microblaze PCI subsystem, to
> > work with generic driver (drivers/pci/host/pcie-xilinx.c) on Microblaze
> > and Zynq.
> > 
> > Signed-off-by: Bharat Kumar Gogada <bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> > Signed-off-by: Ravi Kiran Gummaluri <rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> >...
> 
> >  resource_size_t pcibios_align_resource(void *data, const struct resource *res,
> >  				resource_size_t size, resource_size_t align)
> >  {
> > -	struct pci_dev *dev = data;
> >  	resource_size_t start = res->start;
> >  
> > -	if (res->flags & IORESOURCE_IO) {
> > -		if (skip_isa_ioresource_align(dev))
> > -			return start;
> > -		if (start & 0x300)
> > -			start = (start + 0x3ff) & ~0x3ff;
> > -	}
> > -
> >  	return start;
> 
> "return res->start;" is sufficient; no need for a temporary variable.
> 
> >  }
> >  EXPORT_SYMBOL(pcibios_align_resource);
> >  
> > +int pcibios_add_device(struct pci_dev *dev)
> > +{
> > +	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> > +
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL(pcibios_add_device);
> > +
> >  /*
> >   * Reparent resource children of pr that conflict with res
> >   * under res, and make res replace those children.
> > @@ -1335,9 +1308,21 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose,
> >  
> >  struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
> >  {
> > -	struct pci_controller *hose = bus->sysdata;
> > +	struct device_node *np;
> > +
> > +	for_each_node_by_type(np, "pci") {
> > +		const void *prop;
> > +		unsigned int bus_min;
> > +
> > +		prop = of_get_property(np, "bus-range", NULL);
> > +		if (!prop)
> > +			continue;
> > +		bus_min = be32_to_cpup(prop);
> > +		if (bus->number == bus_min)
> > +			return np;
> > +	}
> >  
> > -	return of_node_get(hose->dn);
> > +	return NULL;
> 
> Hmmm.  The old microblaze code ("return of_node_get(hose->dn);") is
> basically the same as the mips and powerpc versions.  The new code is
> basically the same as the x86 version.
> 
> I like the generic weak version in drivers/pci/of.c because it doesn't
> use any arch-specific data, and it looks like if we just set the
> struct device.of_node members correctly, everything should Just Work.
> 
> But Ben added both the generic and the x86 versions the same day, so
> there must be some complication:
> 
>   98d9f30c820d ("pci/of: Match PCI devices to OF nodes dynamically")
>   3d5fe5a65af9 ("x86/devicetree: Use generic PCI <-> OF matching")
> 
> So I guess my question is, why do we need a microblaze-specific
> version at all?
> 
> Bjorn
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RE: [PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bharat Kumar Gogada]

> Subject: Re: [PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem
> to support generic Xilinx AXI PCIe Host Bridge IP driver
> 
> [+cc Ben for real this time]
> 
> On Wed, Feb 03, 2016 at 10:32:07AM -0600, Bjorn Helgaas wrote:
> > [+cc Ben, pcibios_get_phb_of_node() question]
> >
> > On Tue, Jan 12, 2016 at 11:06:13PM +0530, Bharat Kumar Gogada wrote:
> > > This patch does required modifications to microblaze PCI subsystem,
> > > to work with generic driver (drivers/pci/host/pcie-xilinx.c) on
> > > Microblaze and Zynq.
> > >
> > > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> ...
> >
> > >  resource_size_t pcibios_align_resource(void *data, const struct resource
> *res,
> > >  				resource_size_t size, resource_size_t align)  {
> > > -	struct pci_dev *dev = data;
> > >  	resource_size_t start = res->start;
> > >
> > > -	if (res->flags & IORESOURCE_IO) {
> > > -		if (skip_isa_ioresource_align(dev))
> > > -			return start;
> > > -		if (start & 0x300)
> > > -			start = (start + 0x3ff) & ~0x3ff;
> > > -	}
> > > -
> > >  	return start;
> >
> > "return res->start;" is sufficient; no need for a temporary variable.
> >
Agreed will address in next patch.
> > >  }
> > >  EXPORT_SYMBOL(pcibios_align_resource);
> > >
> > > +int pcibios_add_device(struct pci_dev *dev) {
> > > +	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> > > +
> > > +	return 0;
> > > +}
> > > +EXPORT_SYMBOL(pcibios_add_device);
> > > +
> > >  /*
> > >   * Reparent resource children of pr that conflict with res
> > >   * under res, and make res replace those children.
> > > @@ -1335,9 +1308,21 @@ static void
> > > pcibios_setup_phb_resources(struct pci_controller *hose,
> > >
> > >  struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)  {
> > > -	struct pci_controller *hose = bus->sysdata;
> > > +	struct device_node *np;
> > > +
> > > +	for_each_node_by_type(np, "pci") {
> > > +		const void *prop;
> > > +		unsigned int bus_min;
> > > +
> > > +		prop = of_get_property(np, "bus-range", NULL);
> > > +		if (!prop)
> > > +			continue;
> > > +		bus_min = be32_to_cpup(prop);
> > > +		if (bus->number == bus_min)
> > > +			return np;
> > > +	}
> > >
> > > -	return of_node_get(hose->dn);
> > > +	return NULL;
> >
> > Hmmm.  The old microblaze code ("return of_node_get(hose->dn);") is
> > basically the same as the mips and powerpc versions.  The new code is
> > basically the same as the x86 version.
> >
> > I like the generic weak version in drivers/pci/of.c because it doesn't
> > use any arch-specific data, and it looks like if we just set the
> > struct device.of_node members correctly, everything should Just Work.
> >
> > But Ben added both the generic and the x86 versions the same day, so
> > there must be some complication:
> >
> >   98d9f30c820d ("pci/of: Match PCI devices to OF nodes dynamically")
> >   3d5fe5a65af9 ("x86/devicetree: Use generic PCI <-> OF matching")
> >
> > So I guess my question is, why do we need a microblaze-specific
> > version at all?
> >
I did not notice the weak version in /pci/of.c, I have tested with weak version also and it is working.  We might not need this microblaze specific version, but will wait for ben's reply.  

Bharat

Re: [PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bjorn Helgaas]

On Thu, Feb 04, 2016 at 05:49:20AM +0000, Bharat Kumar Gogada wrote:
> > Subject: Re: [PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem
> > to support generic Xilinx AXI PCIe Host Bridge IP driver
> > 
> > [+cc Ben for real this time]
> > 
> > On Wed, Feb 03, 2016 at 10:32:07AM -0600, Bjorn Helgaas wrote:
> > > [+cc Ben, pcibios_get_phb_of_node() question]
> > >
> > > On Tue, Jan 12, 2016 at 11:06:13PM +0530, Bharat Kumar Gogada wrote:
> > > > This patch does required modifications to microblaze PCI subsystem,
> > > > to work with generic driver (drivers/pci/host/pcie-xilinx.c) on
> > > > Microblaze and Zynq.
> > > >
> > > > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > > > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> ...
> > >
> > > >  resource_size_t pcibios_align_resource(void *data, const struct resource
> > *res,
> > > >  				resource_size_t size, resource_size_t align)  {
> > > > -	struct pci_dev *dev = data;
> > > >  	resource_size_t start = res->start;
> > > >
> > > > -	if (res->flags & IORESOURCE_IO) {
> > > > -		if (skip_isa_ioresource_align(dev))
> > > > -			return start;
> > > > -		if (start & 0x300)
> > > > -			start = (start + 0x3ff) & ~0x3ff;
> > > > -	}
> > > > -
> > > >  	return start;
> > >
> > > "return res->start;" is sufficient; no need for a temporary variable.
> > >
> Agreed will address in next patch.
> > > >  }
> > > >  EXPORT_SYMBOL(pcibios_align_resource);
> > > >
> > > > +int pcibios_add_device(struct pci_dev *dev) {
> > > > +	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> > > > +
> > > > +	return 0;
> > > > +}
> > > > +EXPORT_SYMBOL(pcibios_add_device);
> > > > +
> > > >  /*
> > > >   * Reparent resource children of pr that conflict with res
> > > >   * under res, and make res replace those children.
> > > > @@ -1335,9 +1308,21 @@ static void
> > > > pcibios_setup_phb_resources(struct pci_controller *hose,
> > > >
> > > >  struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)  {
> > > > -	struct pci_controller *hose = bus->sysdata;
> > > > +	struct device_node *np;
> > > > +
> > > > +	for_each_node_by_type(np, "pci") {
> > > > +		const void *prop;
> > > > +		unsigned int bus_min;
> > > > +
> > > > +		prop = of_get_property(np, "bus-range", NULL);
> > > > +		if (!prop)
> > > > +			continue;
> > > > +		bus_min = be32_to_cpup(prop);
> > > > +		if (bus->number == bus_min)
> > > > +			return np;
> > > > +	}
> > > >
> > > > -	return of_node_get(hose->dn);
> > > > +	return NULL;
> > >
> > > Hmmm.  The old microblaze code ("return of_node_get(hose->dn);") is
> > > basically the same as the mips and powerpc versions.  The new code is
> > > basically the same as the x86 version.
> > >
> > > I like the generic weak version in drivers/pci/of.c because it doesn't
> > > use any arch-specific data, and it looks like if we just set the
> > > struct device.of_node members correctly, everything should Just Work.
> > >
> > > But Ben added both the generic and the x86 versions the same day, so
> > > there must be some complication:
> > >
> > >   98d9f30c820d ("pci/of: Match PCI devices to OF nodes dynamically")
> > >   3d5fe5a65af9 ("x86/devicetree: Use generic PCI <-> OF matching")
> > >
> > > So I guess my question is, why do we need a microblaze-specific
> > > version at all?
> > >
> I did not notice the weak version in /pci/of.c, I have tested with
> weak version also and it is working.  We might not need this
> microblaze specific version, but will wait for ben's reply.  

If the generic version works, and you don't need the microblaze-
specific version, just remove it and we'll get this wrapped up.  No
need to wait for Ben.

Bjorn

RE: [PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bharat Kumar Gogada]

> Subject: Re: [PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem
> to support generic Xilinx AXI PCIe Host Bridge IP driver
> 
> On Thu, Feb 04, 2016 at 05:49:20AM +0000, Bharat Kumar Gogada wrote:
> > > Subject: Re: [PATCH V2 5/5] Microblaze: Modifying microblaze PCI
> > > subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver
> > >
> > > [+cc Ben for real this time]
> > >
> > > On Wed, Feb 03, 2016 at 10:32:07AM -0600, Bjorn Helgaas wrote:
> > > > [+cc Ben, pcibios_get_phb_of_node() question]
> > > >
> > > > On Tue, Jan 12, 2016 at 11:06:13PM +0530, Bharat Kumar Gogada wrote:
> > > > > This patch does required modifications to microblaze PCI
> > > > > subsystem, to work with generic driver
> > > > > (drivers/pci/host/pcie-xilinx.c) on Microblaze and Zynq.
> > > > >
> > > > > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > > > > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> ...
> > > >
> > > > >  resource_size_t pcibios_align_resource(void *data, const struct
> > > > > resource
> > > *res,
> > > > >  				resource_size_t size, resource_size_t
> align)  {
> > > > > -	struct pci_dev *dev = data;
> > > > >  	resource_size_t start = res->start;
> > > > >
> > > > > -	if (res->flags & IORESOURCE_IO) {
> > > > > -		if (skip_isa_ioresource_align(dev))
> > > > > -			return start;
> > > > > -		if (start & 0x300)
> > > > > -			start = (start + 0x3ff) & ~0x3ff;
> > > > > -	}
> > > > > -
> > > > >  	return start;
> > > >
> > > > "return res->start;" is sufficient; no need for a temporary variable.
> > > >
> > Agreed will address in next patch.
> > > > >  }
> > > > >  EXPORT_SYMBOL(pcibios_align_resource);
> > > > >
> > > > > +int pcibios_add_device(struct pci_dev *dev) {
> > > > > +	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> > > > > +
> > > > > +	return 0;
> > > > > +}
> > > > > +EXPORT_SYMBOL(pcibios_add_device);
> > > > > +
> > > > >  /*
> > > > >   * Reparent resource children of pr that conflict with res
> > > > >   * under res, and make res replace those children.
> > > > > @@ -1335,9 +1308,21 @@ static void
> > > > > pcibios_setup_phb_resources(struct pci_controller *hose,
> > > > >
> > > > >  struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
> {
> > > > > -	struct pci_controller *hose = bus->sysdata;
> > > > > +	struct device_node *np;
> > > > > +
> > > > > +	for_each_node_by_type(np, "pci") {
> > > > > +		const void *prop;
> > > > > +		unsigned int bus_min;
> > > > > +
> > > > > +		prop = of_get_property(np, "bus-range", NULL);
> > > > > +		if (!prop)
> > > > > +			continue;
> > > > > +		bus_min = be32_to_cpup(prop);
> > > > > +		if (bus->number == bus_min)
> > > > > +			return np;
> > > > > +	}
> > > > >
> > > > > -	return of_node_get(hose->dn);
> > > > > +	return NULL;
> > > >
> > > > Hmmm.  The old microblaze code ("return of_node_get(hose->dn);")
> > > > is basically the same as the mips and powerpc versions.  The new
> > > > code is basically the same as the x86 version.
> > > >
> > > > I like the generic weak version in drivers/pci/of.c because it
> > > > doesn't use any arch-specific data, and it looks like if we just
> > > > set the struct device.of_node members correctly, everything should
> Just Work.
> > > >
> > > > But Ben added both the generic and the x86 versions the same day,
> > > > so there must be some complication:
> > > >
> > > >   98d9f30c820d ("pci/of: Match PCI devices to OF nodes dynamically")
> > > >   3d5fe5a65af9 ("x86/devicetree: Use generic PCI <-> OF matching")
> > > >
> > > > So I guess my question is, why do we need a microblaze-specific
> > > > version at all?
> > > >
> > I did not notice the weak version in /pci/of.c, I have tested with
> > weak version also and it is working.  We might not need this
> > microblaze specific version, but will wait for ben's reply.
> 
> If the generic version works, and you don't need the microblaze- specific
> version, just remove it and we'll get this wrapped up.  No need to wait for
> Ben.
>
Ok Bjorn, I will remove it and send next series of patches.

Bharat

[PATCH V2 2/5] PCI: xilinx: Removing struct hw_irq structure.

[Bharat Kumar Gogada]

Removing struct hw_irq and adding generic PCI core API's.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Removing architecure dependecy structure struct hw_irq which is ARM 32-bit
specific structure, and adding generic PCI core API's to register to
PCI subsytem.
Removing funtions which are not being used with generic API's.
---
 drivers/pci/host/pcie-xilinx.c | 81 +++++++++---------------------------------
 1 file changed, 16 insertions(+), 65 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index f02cfe7..3e3757f 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -117,11 +117,6 @@ struct xilinx_pcie_port {
 
 static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
 
-static inline struct xilinx_pcie_port *sys_to_pcie(struct pci_sys_data *sys)
-{
-	return sys->private_data;
-}
-
 static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
 {
 	return readl(port->reg_base + reg);
@@ -163,7 +158,7 @@ static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
  */
 static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 {
-	struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
+	struct xilinx_pcie_port *port = bus->sysdata;
 
 	/* Check if link is up when trying to access downstream ports */
 	if (bus->number != port->root_busno)
@@ -196,7 +191,7 @@ static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
 					 unsigned int devfn, int where)
 {
-	struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
+	struct xilinx_pcie_port *port = bus->sysdata;
 	int relbus;
 
 	if (!xilinx_pcie_valid_device(bus, devfn))
@@ -228,7 +223,7 @@ static void xilinx_pcie_destroy_msi(unsigned int irq)
 
 	if (!test_bit(irq, msi_irq_in_use)) {
 		msi = irq_get_msi_desc(irq);
-		port = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
+		port = msi_desc_to_pci_sysdata(msi);
 		dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
 	} else {
 		clear_bit(irq, msi_irq_in_use);
@@ -277,7 +272,7 @@ static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
 				     struct pci_dev *pdev,
 				     struct msi_desc *desc)
 {
-	struct xilinx_pcie_port *port = sys_to_pcie(pdev->bus->sysdata);
+	struct xilinx_pcie_port *port = pdev->bus->sysdata;
 	unsigned int irq;
 	int hwirq;
 	struct msi_msg msg;
@@ -614,47 +609,6 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
 }
 
 /**
- * xilinx_pcie_setup - Setup memory resources
- * @nr: Bus number
- * @sys: Per controller structure
- *
- * Return: '1' on success and error value on failure
- */
-static int xilinx_pcie_setup(int nr, struct pci_sys_data *sys)
-{
-	struct xilinx_pcie_port *port = sys_to_pcie(sys);
-
-	list_splice_init(&port->resources, &sys->resources);
-
-	return 1;
-}
-
-/**
- * xilinx_pcie_scan_bus - Scan PCIe bus for devices
- * @nr: Bus number
- * @sys: Per controller structure
- *
- * Return: Valid Bus pointer on success and NULL on failure
- */
-static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
-{
-	struct xilinx_pcie_port *port = sys_to_pcie(sys);
-	struct pci_bus *bus;
-
-	port->root_busno = sys->busnr;
-
-	if (IS_ENABLED(CONFIG_PCI_MSI))
-		bus = pci_scan_root_bus_msi(port->dev, sys->busnr,
-					    &xilinx_pcie_ops, sys,
-					    &sys->resources,
-					    &xilinx_pcie_msi_chip);
-	else
-		bus = pci_scan_root_bus(port->dev, sys->busnr,
-					&xilinx_pcie_ops, sys, &sys->resources);
-	return bus;
-}
-
-/**
  * xilinx_pcie_parse_dt - Parse Device tree
  * @port: PCIe port information
  *
@@ -704,8 +658,9 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
 static int xilinx_pcie_probe(struct platform_device *pdev)
 {
 	struct xilinx_pcie_port *port;
-	struct hw_pci hw;
 	struct device *dev = &pdev->dev;
+	struct pci_bus *bus;
+
 	int err;
 	resource_size_t iobase = 0;
 	LIST_HEAD(res);
@@ -739,24 +694,20 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
 		dev_err(dev, "Getting bridge resources failed\n");
 		return err;
 	}
-
-	platform_set_drvdata(pdev, port);
-
-	/* Register the device */
-	memset(&hw, 0, sizeof(hw));
-	hw = (struct hw_pci) {
-		.nr_controllers	= 1,
-		.private_data	= (void **)&port,
-		.setup		= xilinx_pcie_setup,
-		.map_irq	= of_irq_parse_and_map_pci,
-		.scan		= xilinx_pcie_scan_bus,
-		.ops		= &xilinx_pcie_ops,
-	};
+	bus = pci_create_root_bus(&pdev->dev, 0,
+				  &xilinx_pcie_ops, port, &res);
+	if (!bus)
+		return -ENOMEM;
 
 #ifdef CONFIG_PCI_MSI
 	xilinx_pcie_msi_chip.dev = port->dev;
+	bus->msi = &xilinx_pcie_msi_chip;
 #endif
-	pci_common_init_dev(dev, &hw);
+	pci_scan_child_bus(bus);
+	pci_assign_unassigned_bus_resources(bus);
+	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
+	pci_bus_add_devices(bus);
+	platform_set_drvdata(pdev, port);
 
 	return 0;
 }
-- 
2.1.1

Re: [PATCH V2 2/5] PCI: xilinx: Removing struct hw_irq structure.

[Arnd Bergmann]

On Tuesday 12 January 2016 23:06:10 Bharat Kumar Gogada wrote:
> Removing struct hw_irq and adding generic PCI core API's.
> 
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> ---
> Removing architecure dependecy structure struct hw_irq which is ARM 32-bit
> specific structure, and adding generic PCI core API's to register to
> PCI subsytem.
> Removing funtions which are not being used with generic API's.
> 

typo: s/hw_irq/hw_pci/

	Arnd

RE: [PATCH V2 2/5] PCI: xilinx: Removing struct hw_irq structure.

[Bharat Kumar Gogada]

> Subject: Re: [PATCH V2 2/5] PCI: xilinx: Removing struct hw_irq structure.
> 
> On Tuesday 12 January 2016 23:06:10 Bharat Kumar Gogada wrote:
> > Removing struct hw_irq and adding generic PCI core API's.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> > ---
> > Removing architecure dependecy structure struct hw_irq which is ARM
> > 32-bit specific structure, and adding generic PCI core API's to
> > register to PCI subsytem.
> > Removing funtions which are not being used with generic API's.
> >
> 
> typo: s/hw_irq/hw_pci/
> 
Yes, its struct hw_pci, will correct it in next patch.

[PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Bharat Kumar Gogada]

Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both
Zynq and Microblaze Architectures.
With these modifications drivers/pci/host/pcie-xilinx.c, will
work on both Zynq and Microblaze Architectures.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Changes:
Changed Total number of MSI IRQ count logic according to both architectures.
Updated MSI assigning functions accordingly to new count.
Modified irq_domain_add_linear with new MSI IRQ count.
Added #ifdef to pci_fixup_irqs which is ARM specific API.
---
 drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 3e3757f..1981948 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -92,7 +92,12 @@
 #define ECAM_DEV_NUM_SHIFT		12
 
 /* Number of MSI IRQs */
-#define XILINX_NUM_MSI_IRQS		128
+#define XILINX_NUM_MSI_IRQS	128
+#ifdef CONFIG_ARM
+#define TOT_NR_IRQS		XILINX_NUM_MSI_IRQS
+#else
+#define TOT_NR_IRQS		(NR_IRQS + XILINX_NUM_MSI_IRQS)
+#endif
 
 
 /**
@@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int irq)
  */
 static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
 {
+	int irq;
 	int pos;
 
 	pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
-	if (pos < XILINX_NUM_MSI_IRQS)
+	irq = pos;
+#ifdef CONFIG_MICROBLAZE
+	irq = XILINX_NUM_MSI_IRQS + pos;
+#endif
+	if (irq < TOT_NR_IRQS)
 		set_bit(pos, msi_irq_in_use);
 	else
 		return -ENOSPC;
 
-	return pos;
+	return irq;
 }
 
 /**
@@ -520,7 +530,7 @@ static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
 
 		free_pages(port->msi_pages, 0);
 
-		num_irqs = XILINX_NUM_MSI_IRQS;
+		num_irqs = TOT_NR_IRQS;
 	} else {
 		/* INTx */
 		num_irqs = 4;
@@ -565,7 +575,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
 	/* Setup MSI */
 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
 		port->irq_domain = irq_domain_add_linear(node,
-							 XILINX_NUM_MSI_IRQS,
+							 TOT_NR_IRQS,
 							 &msi_domain_ops,
 							 &xilinx_pcie_msi_chip);
 		if (!port->irq_domain) {
@@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
 #endif
 	pci_scan_child_bus(bus);
 	pci_assign_unassigned_bus_resources(bus);
+#ifdef CONFIG_ARM
 	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
+#endif
 	pci_bus_add_devices(bus);
 	platform_set_drvdata(pdev, port);
 
-- 
2.1.1

Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Arnd Bergmann]

On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote:
> Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both
> Zynq and Microblaze Architectures.
> With these modifications drivers/pci/host/pcie-xilinx.c, will
> work on both Zynq and Microblaze Architectures.
> 
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>

I think this patch should be split into three, as you are doing three
unrelated things here.

> ---
> Changes:
> Changed Total number of MSI IRQ count logic according to both architectures.
> Updated MSI assigning functions accordingly to new count.
> Modified irq_domain_add_linear with new MSI IRQ count.
> Added #ifdef to pci_fixup_irqs which is ARM specific API.
> ---
>  drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++-----
>  1 file changed, 17 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
> index 3e3757f..1981948 100644
> --- a/drivers/pci/host/pcie-xilinx.c
> +++ b/drivers/pci/host/pcie-xilinx.c
> @@ -92,7 +92,12 @@
>  #define ECAM_DEV_NUM_SHIFT		12
>  
>  /* Number of MSI IRQs */
> -#define XILINX_NUM_MSI_IRQS		128
> +#define XILINX_NUM_MSI_IRQS	128
> +#ifdef CONFIG_ARM
> +#define TOT_NR_IRQS		XILINX_NUM_MSI_IRQS
> +#else
> +#define TOT_NR_IRQS		(NR_IRQS + XILINX_NUM_MSI_IRQS)
> +#endif

Something looks wrong here in the microblaze variant. What does NR_IRQS
have to do with it?

> @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int irq)
>   */
>  static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
>  {
> +	int irq;
>  	int pos;
>  
>  	pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
> -	if (pos < XILINX_NUM_MSI_IRQS)
> +	irq = pos;
> +#ifdef CONFIG_MICROBLAZE
> +	irq = XILINX_NUM_MSI_IRQS + pos;
> +#endif


	if (IS_ENABLED(CONFIG_MICROBLAZE))
		irq = XILINX_NUM_MSI_IRQS + pos;

> @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
>  #endif
>  	pci_scan_child_bus(bus);
>  	pci_assign_unassigned_bus_resources(bus);
> +#ifdef CONFIG_ARM
>  	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
> +#endif
>  	pci_bus_add_devices(bus);
>  	platform_set_drvdata(pdev, port);

Here it looks like microblaze gets it right. I'm not sure why we still
need the pci_fixup_irqs() on ARM, but my feeling is that this should be
fixed in common code.

	Arnd

Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Michal Simek]

On 12.1.2016 23:27, Arnd Bergmann wrote:
> On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote:
>> Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both
>> Zynq and Microblaze Architectures.
>> With these modifications drivers/pci/host/pcie-xilinx.c, will
>> work on both Zynq and Microblaze Architectures.
>>
>> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
>> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> 
> I think this patch should be split into three, as you are doing three
> unrelated things here.
> 
>> ---
>> Changes:
>> Changed Total number of MSI IRQ count logic according to both architectures.
>> Updated MSI assigning functions accordingly to new count.
>> Modified irq_domain_add_linear with new MSI IRQ count.
>> Added #ifdef to pci_fixup_irqs which is ARM specific API.
>> ---
>>  drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++-----
>>  1 file changed, 17 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
>> index 3e3757f..1981948 100644
>> --- a/drivers/pci/host/pcie-xilinx.c
>> +++ b/drivers/pci/host/pcie-xilinx.c
>> @@ -92,7 +92,12 @@
>>  #define ECAM_DEV_NUM_SHIFT		12
>>  
>>  /* Number of MSI IRQs */
>> -#define XILINX_NUM_MSI_IRQS		128
>> +#define XILINX_NUM_MSI_IRQS	128
>> +#ifdef CONFIG_ARM
>> +#define TOT_NR_IRQS		XILINX_NUM_MSI_IRQS
>> +#else
>> +#define TOT_NR_IRQS		(NR_IRQS + XILINX_NUM_MSI_IRQS)
>> +#endif
> 
> Something looks wrong here in the microblaze variant. What does NR_IRQS
> have to do with it?

Arnd: What was the story regarding NR_IRQS?
I remember some discussion about it but just forget.

Default value in include/asm-generic/irq.h is 64.
Current value is 32 because microblaze primary interrupt controller is
axi_intc core which has up to 32 input lines.

Thanks,
Michal

Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Arnd Bergmann]

On Tuesday 26 January 2016 10:59:12 Michal Simek wrote:
> >> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
> >> index 3e3757f..1981948 100644
> >> --- a/drivers/pci/host/pcie-xilinx.c
> >> +++ b/drivers/pci/host/pcie-xilinx.c
> >> @@ -92,7 +92,12 @@
> >>  #define ECAM_DEV_NUM_SHIFT          12
> >>  
> >>  /* Number of MSI IRQs */
> >> -#define XILINX_NUM_MSI_IRQS         128
> >> +#define XILINX_NUM_MSI_IRQS 128
> >> +#ifdef CONFIG_ARM
> >> +#define TOT_NR_IRQS         XILINX_NUM_MSI_IRQS
> >> +#else
> >> +#define TOT_NR_IRQS         (NR_IRQS + XILINX_NUM_MSI_IRQS)
> >> +#endif
> > 
> > Something looks wrong here in the microblaze variant. What does NR_IRQS
> > have to do with it?
> 
> Arnd: What was the story regarding NR_IRQS?
> I remember some discussion about it but just forget.
> 
> Default value in include/asm-generic/irq.h is 64.
> Current value is 32 because microblaze primary interrupt controller is
> axi_intc core which has up to 32 input lines.

The value in asm-generic is completely arbitrary, it's just something
that happens to work for a number of the simpler architectures.

Traditionally, there is a a fixed NR_IRQS which defines the maximum
number of interrupts that can be used, and each irqchip has a fixed
start offset below that number.

On modern systems, you have CONFIG_SPARSE_IRQ, which lets an irqchip
allocate its own interrupts, without an upper limit. This is more
flexible and avoids preallocating space for all irq_desc instances,
so it saves memory.

This code however doesn't do either of the two on microblaze:

+       irq = pos;
+#ifdef CONFIG_MICROBLAZE
+#define TOT_NR_IRQS            (NR_IRQS + XILINX_NUM_MSI_IRQS)
+       irq = XILINX_NUM_MSI_IRQS + pos;
+#endif
+       if (irq < TOT_NR_IRQS)
                set_bit(pos, msi_irq_in_use);

So you define XILINX_NUM_MSI_IRQS to mean the number of interrupts
that the xilinx_pcie_port can handle itself, but then pick a number
outside of this range by making the hwirq number something between
XILINX_NUM_MSI_IRQS and (2*XILINX_NUM_MSI_IRQS - 1), and in the
end compare it to (NR_IRQS + XILINX_NUM_MSI_IRQS), which is the
sum of two things that are not related: the total number of interrupts
including the MSIs and the number of MSI.

	Arnd

Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Michal Simek]

On 26.1.2016 13:11, Arnd Bergmann wrote:
> On Tuesday 26 January 2016 10:59:12 Michal Simek wrote:
>>>> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
>>>> index 3e3757f..1981948 100644
>>>> --- a/drivers/pci/host/pcie-xilinx.c
>>>> +++ b/drivers/pci/host/pcie-xilinx.c
>>>> @@ -92,7 +92,12 @@
>>>>  #define ECAM_DEV_NUM_SHIFT          12
>>>>  
>>>>  /* Number of MSI IRQs */
>>>> -#define XILINX_NUM_MSI_IRQS         128
>>>> +#define XILINX_NUM_MSI_IRQS 128
>>>> +#ifdef CONFIG_ARM
>>>> +#define TOT_NR_IRQS         XILINX_NUM_MSI_IRQS
>>>> +#else
>>>> +#define TOT_NR_IRQS         (NR_IRQS + XILINX_NUM_MSI_IRQS)
>>>> +#endif
>>>
>>> Something looks wrong here in the microblaze variant. What does NR_IRQS
>>> have to do with it?
>>
>> Arnd: What was the story regarding NR_IRQS?
>> I remember some discussion about it but just forget.
>>
>> Default value in include/asm-generic/irq.h is 64.
>> Current value is 32 because microblaze primary interrupt controller is
>> axi_intc core which has up to 32 input lines.
> 
> The value in asm-generic is completely arbitrary, it's just something
> that happens to work for a number of the simpler architectures.
> 
> Traditionally, there is a a fixed NR_IRQS which defines the maximum
> number of interrupts that can be used, and each irqchip has a fixed
> start offset below that number.
> 
> On modern systems, you have CONFIG_SPARSE_IRQ, which lets an irqchip
> allocate its own interrupts, without an upper limit. This is more
> flexible and avoids preallocating space for all irq_desc instances,
> so it saves memory.

ok. That was the story. I will look if there is any issue to enable
SPARSE_IRQ for Microblaze.

I also need to move intc driver out of arch.

Thanks,
Michal

RE: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Bharat Kumar Gogada]

> 
> On Tuesday 26 January 2016 10:59:12 Michal Simek wrote:
> > >> diff --git a/drivers/pci/host/pcie-xilinx.c
> > >> b/drivers/pci/host/pcie-xilinx.c index 3e3757f..1981948 100644
> > >> --- a/drivers/pci/host/pcie-xilinx.c
> > >> +++ b/drivers/pci/host/pcie-xilinx.c
> > >> @@ -92,7 +92,12 @@
> > >>  #define ECAM_DEV_NUM_SHIFT          12
> > >>
> > >>  /* Number of MSI IRQs */
> > >> -#define XILINX_NUM_MSI_IRQS         128
> > >> +#define XILINX_NUM_MSI_IRQS 128
> > >> +#ifdef CONFIG_ARM
> > >> +#define TOT_NR_IRQS         XILINX_NUM_MSI_IRQS
> > >> +#else
> > >> +#define TOT_NR_IRQS         (NR_IRQS + XILINX_NUM_MSI_IRQS)
> > >> +#endif
> > >
> > > Something looks wrong here in the microblaze variant. What does
> > > NR_IRQS have to do with it?
> >
> > Arnd: What was the story regarding NR_IRQS?
> > I remember some discussion about it but just forget.
> >
> > Default value in include/asm-generic/irq.h is 64.
> > Current value is 32 because microblaze primary interrupt controller is
> > axi_intc core which has up to 32 input lines.
> 
> The value in asm-generic is completely arbitrary, it's just something that
> happens to work for a number of the simpler architectures.
> 
> Traditionally, there is a a fixed NR_IRQS which defines the maximum number
> of interrupts that can be used, and each irqchip has a fixed start offset below
> that number.
> 
> On modern systems, you have CONFIG_SPARSE_IRQ, which lets an irqchip
> allocate its own interrupts, without an upper limit. This is more flexible and
> avoids preallocating space for all irq_desc instances, so it saves memory.
> 
> This code however doesn't do either of the two on microblaze:
> 
> +       irq = pos;
> +#ifdef CONFIG_MICROBLAZE
> +#define TOT_NR_IRQS            (NR_IRQS + XILINX_NUM_MSI_IRQS)
> +       irq = XILINX_NUM_MSI_IRQS + pos; #endif
> +       if (irq < TOT_NR_IRQS)
>                 set_bit(pos, msi_irq_in_use);
> 
> So you define XILINX_NUM_MSI_IRQS to mean the number of interrupts
> that the xilinx_pcie_port can handle itself, but then pick a number
> outside of this range by making the hwirq number something between
> XILINX_NUM_MSI_IRQS and (2*XILINX_NUM_MSI_IRQS - 1), and in the
> end compare it to (NR_IRQS + XILINX_NUM_MSI_IRQS), which is the
> sum of two things that are not related: the total number of interrupts
> including the MSIs and the number of MSI.
> 
Agreed, I have crosschecked something's which I missed previously, NR_IRQS have nothing to do with the count, and also no need to add, irq = XILINX_NUM_MSI_IRQS + pos; in microblaze, I will remove these checks in next patch series.

RE: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Bharat Kumar Gogada]

> Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver
> to work on both Zynq and Microblaze
> 
> On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote:
> > Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both
> > Zynq and Microblaze Architectures.
> > With these modifications drivers/pci/host/pcie-xilinx.c, will work on
> > both Zynq and Microblaze Architectures.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> > Signed-off-by: Ravi Kiran Gummaluri <rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> 
> I think this patch should be split into three, as you are doing three unrelated
> things here.
> 
Agreed, will send as different patches in next series.
> > ---
> > --- a/drivers/pci/host/pcie-xilinx.c
> > +++ b/drivers/pci/host/pcie-xilinx.c
> > @@ -92,7 +92,12 @@
> >  #define ECAM_DEV_NUM_SHIFT		12
> >
> >  /* Number of MSI IRQs */
> > -#define XILINX_NUM_MSI_IRQS		128
> > +#define XILINX_NUM_MSI_IRQS	128
> > +#ifdef CONFIG_ARM
> > +#define TOT_NR_IRQS		XILINX_NUM_MSI_IRQS
> > +#else
> > +#define TOT_NR_IRQS		(NR_IRQS + XILINX_NUM_MSI_IRQS)
> > +#endif
> 
> Something looks wrong here in the microblaze variant. What does NR_IRQS
> have to do with it?
> 
> > @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int
> irq)
> >   */
> >  static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)  {
> > +	int irq;
> >  	int pos;
> >
> >  	pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
> > -	if (pos < XILINX_NUM_MSI_IRQS)
> > +	irq = pos;
> > +#ifdef CONFIG_MICROBLAZE
> > +	irq = XILINX_NUM_MSI_IRQS + pos;
> > +#endif
> 
> 
> 	if (IS_ENABLED(CONFIG_MICROBLAZE))
> 		irq = XILINX_NUM_MSI_IRQS + pos;
> 
Agreed.
> > @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct
> > platform_device *pdev)  #endif
> >  	pci_scan_child_bus(bus);
> >  	pci_assign_unassigned_bus_resources(bus);
> > +#ifdef CONFIG_ARM
> >  	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
> > +#endif
> >  	pci_bus_add_devices(bus);
> >  	platform_set_drvdata(pdev, port);
> 
> Here it looks like microblaze gets it right. I'm not sure why we still need the
> pci_fixup_irqs() on ARM, but my feeling is that this should be fixed in
> common code.
In arm pci_fixup_irqs is called by pci_common_init_dev (arch/arm/kernel/bios32.c), since this API is removed now, I was calling it separately.

Bharat

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Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Arnd Bergmann]

On Wednesday 27 January 2016 14:33:45 Bharat Kumar Gogada wrote:
> > > @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct
> > > platform_device *pdev)  #endif
> > >     pci_scan_child_bus(bus);
> > >     pci_assign_unassigned_bus_resources(bus);
> > > +#ifdef CONFIG_ARM
> > >     pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
> > > +#endif
> > >     pci_bus_add_devices(bus);
> > >     platform_set_drvdata(pdev, port);
> > 
> > Here it looks like microblaze gets it right. I'm not sure why we still need the
> > pci_fixup_irqs() on ARM, but my feeling is that this should be fixed in
> > common code.
> In arm pci_fixup_irqs is called by pci_common_init_dev (arch/arm/kernel/bios32.c), since this API is removed now, I was calling it separately.

But who calls it in microblaze? If it works without the extra call there,
can we make it work the same way for ARM?

	Arnd

RE: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Bharat Kumar Gogada]

> Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver
> to work on both Zynq and Microblaze
> 
> On Wednesday 27 January 2016 14:33:45 Bharat Kumar Gogada wrote:
> > > > @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct
> > > > platform_device *pdev)  #endif
> > > >     pci_scan_child_bus(bus);
> > > >     pci_assign_unassigned_bus_resources(bus);
> > > > +#ifdef CONFIG_ARM
> > > >     pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
> > > > +#endif
> > > >     pci_bus_add_devices(bus);
> > > >     platform_set_drvdata(pdev, port);
> > >
> > > Here it looks like microblaze gets it right. I'm not sure why we
> > > still need the
> > > pci_fixup_irqs() on ARM, but my feeling is that this should be fixed
> > > in common code.
> > In arm pci_fixup_irqs is called by pci_common_init_dev
> (arch/arm/kernel/bios32.c), since this API is removed now, I was calling it
> separately.
> 
> But who calls it in microblaze? If it works without the extra call there, can we
> make it work the same way for ARM?
> 
In microblaze I have added pcibios_add_device call (similar to call in arch/arm64/kernel/pci.c ) in pci-common.c, which is being invoked by kernel core itself. May be we can add similar on arm and test out, but we might need some cleanup in arch/arm/kernel/bios32.c

Bharat

Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Arnd Bergmann]

On Thursday 28 January 2016 13:20:56 Bharat Kumar Gogada wrote:
> > Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver
> > to work on both Zynq and Microblaze
> > 
> > On Wednesday 27 January 2016 14:33:45 Bharat Kumar Gogada wrote:
> > > > > @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct
> > > > > platform_device *pdev)  #endif
> > > > >     pci_scan_child_bus(bus);
> > > > >     pci_assign_unassigned_bus_resources(bus);
> > > > > +#ifdef CONFIG_ARM
> > > > >     pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
> > > > > +#endif
> > > > >     pci_bus_add_devices(bus);
> > > > >     platform_set_drvdata(pdev, port);
> > > >
> > > > Here it looks like microblaze gets it right. I'm not sure why we
> > > > still need the
> > > > pci_fixup_irqs() on ARM, but my feeling is that this should be fixed
> > > > in common code.
> > > In arm pci_fixup_irqs is called by pci_common_init_dev
> > (arch/arm/kernel/bios32.c), since this API is removed now, I was calling it
> > separately.
> > 
> > But who calls it in microblaze? If it works without the extra call there, can we
> > make it work the same way for ARM?
> > 
> In microblaze I have added pcibios_add_device call (similar to call in
> arch/arm64/kernel/pci.c ) in pci-common.c, which is being invoked by
> kernel core itself.

I see. In the upstream code you seem to do it in pcibios_setup_bus_devices(),
while arm64 and powerpc do it in pcibios_add_device().

> May be we can add similar on arm and test out, but
> we might need some cleanup in arch/arm/kernel/bios32.c

I think that would still just be a half-baked solution. This should
really be fully automatic. We could do it in the __weak
pcibios_add_device() for all architectures that don't override
it when the bus was probed from DT, or we could do it in
pci_read_irq().

	Arnd

RE: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Bharat Kumar Gogada]

> Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver
> to work on both Zynq and Microblaze
> 
> On Thursday 28 January 2016 13:20:56 Bharat Kumar Gogada wrote:
> > > Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host
> > > Bridge driver to work on both Zynq and Microblaze
> > >
> > > On Wednesday 27 January 2016 14:33:45 Bharat Kumar Gogada wrote:
> > > > > > @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct
> > > > > > platform_device *pdev)  #endif
> > > > > >     pci_scan_child_bus(bus);
> > > > > >     pci_assign_unassigned_bus_resources(bus);
> > > > > > +#ifdef CONFIG_ARM
> > > > > >     pci_fixup_irqs(pci_common_swizzle,
> > > > > > of_irq_parse_and_map_pci);
> > > > > > +#endif
> > > > > >     pci_bus_add_devices(bus);
> > > > > >     platform_set_drvdata(pdev, port);
> > > > >
> > > > > Here it looks like microblaze gets it right. I'm not sure why we
> > > > > still need the
> > > > > pci_fixup_irqs() on ARM, but my feeling is that this should be
> > > > > fixed in common code.
> > > > In arm pci_fixup_irqs is called by pci_common_init_dev
> > > (arch/arm/kernel/bios32.c), since this API is removed now, I was
> > > calling it separately.
> > >
> > > But who calls it in microblaze? If it works without the extra call
> > > there, can we make it work the same way for ARM?
> > >
> > In microblaze I have added pcibios_add_device call (similar to call in
> > arch/arm64/kernel/pci.c ) in pci-common.c, which is being invoked by
> > kernel core itself.
> 
> I see. In the upstream code you seem to do it in
> pcibios_setup_bus_devices(), while arm64 and powerpc do it in
> pcibios_add_device().
> 
No that function is not getting called with generic API's, its getting called with pcibios_init flow which is tightly bound with struct pci_controller microblaze specific structure. So I added pcibios_add_device in pci-common.c.

> > May be we can add similar on arm and test out, but we might need some
> > cleanup in arch/arm/kernel/bios32.c
> 
> I think that would still just be a half-baked solution. This should really be fully
> automatic. We could do it in the __weak
> pcibios_add_device() for all architectures that don't override it when the bus
> was probed from DT, or we could do it in pci_read_irq().
When will pci_read_irq() call get invoked ?

Bharat

Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Arnd Bergmann]

On Thursday 28 January 2016 14:18:15 Bharat Kumar Gogada wrote:
> > 
> > I see. In the upstream code you seem to do it in
> > pcibios_setup_bus_devices(), while arm64 and powerpc do it in
> > pcibios_add_device().
> > 
> No that function is not getting called with generic API's, its getting called with pcibios_init flow which is tightly bound with struct pci_controller microblaze specific structure. So I added pcibios_add_device in pci-common.c.

Ok

> > > May be we can add similar on arm and test out, but we might need some
> > > cleanup in arch/arm/kernel/bios32.c
> > 
> > I think that would still just be a half-baked solution. This should really be fully
> > automatic. We could do it in the __weak
> > pcibios_add_device() for all architectures that don't override it when the bus
> > was probed from DT, or we could do it in pci_read_irq().
> When will pci_read_irq() call get invoked ?

This is called early on when a device gets created in pci_setup_device(),
so platforms can still override the value later.

The idea here is that normally a BIOS stores the interrupt number in
the PCI_INTERRUPT_LINE config space byte, and we just read it from
there. Generally speaking though, for non-PC systems we tend to not
have a BIOS that writes these values to start with, and any values
stored in here have no meaning in combination with SPARSE_IRQ
and/or IRQ_DOMAINS because the bootloader or BIOS doesn't know
what IRQ number will refer to hardware IRQ line in Linux.

	Arnd

Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Lorenzo Pieralisi]

On Thu, Jan 28, 2016 at 03:23:37PM +0100, Arnd Bergmann wrote:
> On Thursday 28 January 2016 14:18:15 Bharat Kumar Gogada wrote:
> > > 
> > > I see. In the upstream code you seem to do it in
> > > pcibios_setup_bus_devices(), while arm64 and powerpc do it in
> > > pcibios_add_device().
> > > 
> > No that function is not getting called with generic API's, its getting called with pcibios_init flow which is tightly bound with struct pci_controller microblaze specific structure. So I added pcibios_add_device in pci-common.c.
> 
> Ok
> 
> > > > May be we can add similar on arm and test out, but we might need some
> > > > cleanup in arch/arm/kernel/bios32.c
> > > 
> > > I think that would still just be a half-baked solution. This should really be fully
> > > automatic. We could do it in the __weak
> > > pcibios_add_device() for all architectures that don't override it when the bus
> > > was probed from DT, or we could do it in pci_read_irq().
> > When will pci_read_irq() call get invoked ?
> 
> This is called early on when a device gets created in pci_setup_device(),
> so platforms can still override the value later.
> 
> The idea here is that normally a BIOS stores the interrupt number in
> the PCI_INTERRUPT_LINE config space byte, and we just read it from
> there. Generally speaking though, for non-PC systems we tend to not
> have a BIOS that writes these values to start with, and any values
> stored in here have no meaning in combination with SPARSE_IRQ
> and/or IRQ_DOMAINS because the bootloader or BIOS doesn't know
> what IRQ number will refer to hardware IRQ line in Linux.

I think the best way to handle this is through Matthew's series (below),
in the interim a callback in arch code would do, we will clean it up when
Matthew's series goes upstream, it should not take too long.

http://www.spinics.net/lists/linux-pci/msg45950.html

Thanks,
Lorenzo

[PATCH V2 4/5] PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze node.

[Bharat Kumar Gogada]

Updated Zynq PCI binding documentation with Microblaze node.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Changes:
Adding Microblaze device tree node Documnetation.
---
 .../devicetree/bindings/pci/xilinx-pcie.txt        | 36 ++++++++++++++++++++--
 1 file changed, 33 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
index 02f979a..d207bf4 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -17,7 +17,10 @@ Required properties:
 	Please refer to the standard PCI bus binding document for a more
 	detailed explanation
 
-Optional properties:
+Optional properties for Zynq:
+- bus-range: PCI bus numbers covered
+
+Required property for Microblaze:
 - bus-range: PCI bus numbers covered
 
 Interrupt controller child node
@@ -38,13 +41,13 @@ the four INTx interrupts in ISR and route them to this domain.
 
 Example:
 ++++++++
-
+Zynq:
 	pci_express: axi-pcie@50000000 {
 		#address-cells = <3>;
 		#size-cells = <2>;
 		#interrupt-cells = <1>;
 		compatible = "xlnx,axi-pcie-host-1.00.a";
-		reg = < 0x50000000 0x10000000 >;
+		reg = < 0x50000000 0x1000000 >;
 		device_type = "pci";
 		interrupts = < 0 52 4 >;
 		interrupt-map-mask = <0 0 0 7>;
@@ -60,3 +63,30 @@ Example:
 			#interrupt-cells = <1>;
 		};
 	};
+
+
+Microblaze:
+	pci_express: axi-pcie@10000000 {
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		compatible = "xlnx,axi-pcie-host-1.00.a";
+		reg = <0x10000000 0x4000000>;
+		device_type = "pci";
+		interrupt-parent = <&microbalze_0_intc>;
+		interrupts = <1 2>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie_intc 1>,
+				<0 0 0 2 &pcie_intc 2>,
+				<0 0 0 3 &pcie_intc 3>,
+				<0 0 0 4 &pcie_intc 4>;
+		ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
+		bus-range = <0x00 0xff>;
+
+		pcie_intc: interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+		};
+
+	};
-- 
2.1.1

Re: [PATCH V2 4/5] PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze node.

[Rob Herring]

On Tue, Jan 12, 2016 at 11:06:12PM +0530, Bharat Kumar Gogada wrote:
> Updated Zynq PCI binding documentation with Microblaze node.
> 
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> ---
> Changes:
> Adding Microblaze device tree node Documnetation.
> ---
>  .../devicetree/bindings/pci/xilinx-pcie.txt        | 36 ++++++++++++++++++++--
>  1 file changed, 33 insertions(+), 3 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH V2 0/5] PCIe Xilinx generic driver for Microblaze and

[Arnd Bergmann]

On Tuesday 12 January 2016 23:06:08 Bharat Kumar Gogada wrote:
> This patch series does modifications to pcie-xilinx.c, to support common
> driver on both Zynq and Microblaze architectures.
> Microblaze pci-common.c has been modified to support generic driver.
> 
> I'm aware Paul Burton <paul.burton@imgtec.com> has also sent patches
> related to pcie-xilinx.c, but I'm unable to comment on them. 
> I request Paul Burton to please add me in cc list so that I can comment on
> those patches.

Very nice work overall!

I've commented on a few smaller things that I think could be improved.

	Arnd

RE: [PATCH V2 0/5] PCIe Xilinx generic driver for Microblaze and

[Bharat Kumar Gogada]

> Subject: Re: [PATCH V2 0/5] PCIe Xilinx generic driver for Microblaze and
> 
> On Tuesday 12 January 2016 23:06:08 Bharat Kumar Gogada wrote:
> > This patch series does modifications to pcie-xilinx.c, to support
> > common driver on both Zynq and Microblaze architectures.
> > Microblaze pci-common.c has been modified to support generic driver.
> >
> > I'm aware Paul Burton <paul.burton@imgtec.com> has also sent patches
> > related to pcie-xilinx.c, but I'm unable to comment on them.
> > I request Paul Burton to please add me in cc list so that I can
> > comment on those patches.
> 
> Very nice work overall!
> 
> I've commented on a few smaller things that I think could be improved.
> 
Thanks, I will do the accordingly.

Bharat